PRIORITIZED INSTRUCTION SCHEDULING FOR MULTI-STREAMING PROCESSORS

Title:

PRIORITIZED INSTRUCTION SCHEDULING FOR MULTI-STREAMING PROCESSORS

Document Type and Number:

WIPO Patent Application WO2000036487

Kind Code:

A3

Abstract:

A multi-streaming processor (14) has multiple streams (4) for processing multiple threads (1-3), and an instruction scheduler (5) including a priority record of priority codes (7, 8) for one or more of the streams (4). The priority codes (7, 8) determine in some embodiments relative access to resources (10-13) as well as which stream (4) has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip (9), according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, input from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.

Inventors:

NEMIROVSKY MARIO D
NEMIROVSKY ADOLFO M
SANKAR NARENDRA

Application Number:

PCT/US1999/029645

Publication Date:

November 23, 2000

Filing Date:

December 13, 1999

Export Citation:

Click for automatic bibliography generation Help

Assignee:

XSTREAM LOGIC INC (US)

International Classes:

G06F9/38; G06F9/46; G06F9/48; (IPC1-7): G06F9/00

Foreign References:

US5600837A	1997-02-04
US5461722A	1995-10-24
US5542088A	1996-07-30
US5748468A	1998-05-05
US5745778A	1998-04-28
US5867725A	1999-02-02

Other References: