AUTOMATIC MONITOR ALIGNMENT SYSTEM The present invention relates generally to systems for controlling the output of video display monitors or the like. More particularly, the present invention is directed to a system for measuring the distortion of a manufactured monitor and developing a set of control relationships that correct distortion during use of the monitor. BACKGROUND OF THE INVENTION Monitor design and manufacturing has long been concerned with producing a video display monitor that generates a distortion free image in accordance with the input image signals. The manufacturing process employed in the assembly line production of display monitors will invariably lead to small deviations from design specification. This is exemplified in the construction of the cathode ray tube (CRT) , forming the operative display element in most display monitors. The CRT is equipped with windings and deflection plates for imparting the controlling image signal onto the stream of electrons emanating from the electron gun prior to striking the phosphors of the display screen. The process of manufacturing these windings and deflection plates will invariable result in a small amount of deviation between each unit produced on the assembly line. Small deviations often lead to slight image distortions unless corrected by subsequent signal processing techniques.

Cost effective correction of displayed images on the monitor screen by post signal processing techniques has been limited. One method involves the use of a continuous analog function applied to compensate for the imperfections found in the signal as transmitted to the CRT. For example, conventional monitors will often be equipped with a dynamic focus circuit. This circuit creates a compensating waveform designed to correct

imperfections in focus on the displayed image. The compensating waveform from the dynamic focus circuit continuously modulates the electron beam responsive to its position during the scanning process across the screen in accordance with the governing image signal and sync pulses.

However, this dynamic waveform, which is conventionally some form of continuous parabolic curve, is fixed, with only the distance from the base to the ends of the curve adjustable. To adjust focus, the base level is adjusted for a best "center" performance, and the height and sides for the best corner performance. The corner adjustment is based on the assumption that all corners have corresponding levels of distortion, which, in fact, is not factually correct. In addition, the use of one curve for the distortion relationship between the center and corners is never a perfect match to reality, especially as applied to different type and sized CRTs. Finally, generating an analog waveform that is not frequency dependent (for multi-sync monitors) or unaffected by local field peculiarities (within the monitor) is nearly impossible.

The above issues are equally present with other efforts to remove or compensate for distortion in a monitor. These areas of distortion are well known in this industry as are the circuits for their attempted correction. In Figure 1, a selection of generic distortion types common to many CRT based monitors is presented. As can be recognized, the use of analog based functions cannot address in a pixel by pixel manner, the myriad of forms of distortion encountered in CRT displays.

In view of the problems of the prior art, there continues a search for a system that can compensate for image distortion on a CRT monitor that addresses the above design criteria; the following invention is a solution to these problems.

OBJECTS AND SUMMARY OF THE PRESENT INVENTION It is an object of the present invention to provide a CRT based display monitor that incorporates a series of digital waveforms applied to the image signal to correct for distortions in CRT geometry, deflection coils, circuits and other CRT components governing image generation.

It is another object of the present invention to provide a CRT based monitor with an ASIC control processor that is programmed with custom correction waveforms for use in correcting the image applied to the monitor display screen.

It is a further object of the present invention to provide a method for manufacturing CRT based monitors that includes the step of measuring the level of distortion on the display screen, developing a set of digital waveforms applicable on a pixel by pixel basis to the image signal, and storing the encoded digital waveforms in an ASIC control processor within the monitor for subsequent recall during operation.

It is yet another object of the present invention to provide a system for tracking the incoming sync pulses and provide dynamic corrections via phase compensation for picture position drift caused by changes in the deflection circuits as a result of ambient temperature changes thereby creating high electronic noise immunity.

The above and other objects of the present invention are realized in a specific illustrative microprocessor controlled monitor equipped with a custom designed ASIC (application specific integrated circuit) controller. A set of compensating waveforms in digital form are stored in a anti-distortion waveform table. The ASIC processes the incoming image signal thereby tracking in real time the position of the electron stream vis a vis the image display screen in matrix format. The ASIC applies the appropriate anti-distortion waveform synchronized to the

image signal to the CRT control circuits thus summing to a largely distortion free image for the monitor.

The digital anti-distortion waveforms are created during the latter stages of monitor manufacturing. The monitor is provided a select image signal having known desired positional information within the image matrix. A video camera is then positioned in front of the display image providing a feedback loop for the actual positional information associated with that monitor and image signal. A computer tracks the discrepancies between the expected and actual image for each point in the matrix array. As this discrepancy is measured, a corresponding correcting waveform is created incorporating the distinctions between the actual and desired image position within the matrix. These corrective waveforms are then stored in a look-up table within the monitor for subsequent access during operation.

In accordance with the varying aspects of the present invention, the ASIC controller further tracks the incoming sync signals (primary phase detector) and provides a separate phase correction (secondary phase detector) to the horizontal drive signal. Phase compensation is required to address image drift caused by temperature swings during operation. These temperature changes modify the performance of the horizontal deflection circuit. The primary phase detector generates system timing clocks and provides the high and low lock gain feature for fast lock- on to new timing signals. Low lock offers better signal- to-noise. The second phase detector compensates for deflection drift (auto) . This is done by comparing the phase of the horizontal retrace signal and input sync and modifying the SAW delay generator accordingly.

The foregoing features of the present invention may be fully appreciated from the following detailed description of a specific illustrative system thereof,

taken in conjunction with the associated drawings in which:

DESCRIPTION OF THE FIGURES Figure 1 is a diagram of identifiable forms of distortion associated with CRT based display monitors;

Figure 2 is functional block diagram of the elements necessary in programming a ASIC controlled monitor with the anti-distortion waveforms;

Figure 3 is a schematic block diagram of a CRT based monitor equipped with an ASIC controller with anti- distortion waveforms stored in addressable memory;

Figure 4 is a schematic block diagram of a ASIC controller used to provide anti-distortion correction signals in real time to the image signal within a display monitor;

Figure 5 is a block diagram of the vertical rate waveform generator subsystem;

Figure 6 depicts sample output waveforms associated with the five output functions in Fig. 5; Figure 7 is a block diagram of the horizontal rate waveform generator subsystem; and

Figure 8 depicts sample output waveforms associated with the three output functions in Fig. 7.

DESCRIPTION OF THE PRESENT INVENTION First briefly in overview, the present invention is directed to the use of an ASIC controller for developing a series of distortion correcting waveforms that are delivered in timed relationship with the governing image signal to the display screen, thus correcting any distortion associated with the image signal as processed by the monitor. The distortion correcting waveforms are first developed during the manufacturing process of the display monitor. In the final stages of manufacturing, a test pattern is presented on the CRT screen which is externally examined by a supplemental video system, which analyzes the test pattern and deciphers distortions

associated with its display. Using this information, one or more inverse or anti-distortion digital waveforms are generated by the calibration system software. This anti- distortion information is digitally formatted and encoded for storage in addressable memory within the monitor.

During subsequent operation of the monitor, the command logic of the ASIC controller applies the incoming video signal to provide timed output of the distortion correction waveform to the CRT circuits such as deflection, focus grids and cathodes in conjunction with the video signal.

With the foregoing discussion as background, attention is directed to Fig. 2 which depicts in block diagram format an overview of the inventive system as it applies to the manufacturing phase of monitor production. More particularly, during monitor testing, an image is directed to the screen of monitor 120. This image provides a combination of colors, gradations and line information designed to highlight image distortion that may have arisen during manufacturing. The image is read by video camera 100 with an image output signal directed via video line to auto alignment processor 110.

The auto alignment processor 110 is conventionally an IBM compatible personal computer equipped with the per se well known 80386 microprocessor or its equivalent and an image board for processing the incoming video signal from camera 100. A second image intensity sensor 140 is placed in front of the monitor screen with a second signal feeding into dedicated processor 130. This intensity probe measures the luminescence intensity of the red/green/blue components emanating from the screen; this information is linked to the auto alignment processor via RS-232 serial port.

In operation, the image measured is compared to the expected image pattern assuming proper focus, pin cushion, etc, for the monitor. The deviations are spatially

calculated and correcting values are determined as a function of on-screen position in matrix terms. These correcting values are then applied as the quantitative parameters defining one or more digital corrective waveforms which are stored in addressable monitor memory. The type of error correction addressed in this manner is graphically depicted in Fig. 1 wherein 13 separate forms of distortion are presented in three general categories, i.e., horizontal pin cushion, horizontal pin balance and vertical drive. In some instances, a single digital waveform will contain terms addressing one or more of the distinct types of distortion depicted in Fig. 1, in an integrated manner.

Turning now to Fig. 3, a more detailed presentation is provided regarding the various subsystems described above in reference to Fig. 2. More particularly, the overall operation of the CRT being manufactured is governed by the ASIC designated DMC-1000, block 200. As presented herein, this controller is connected via the indicated interconnects to the monitor subsystems, e.g., CRT 210, RGB amplifier 220, power amplifier 230, horizontal deflection processor 240 and vertical deflection processor 250, with these various elements having their expected functions within a monitor. In addition, the controller 200 is connected to auto alignment processor 110 for the development of the requisite correcting waveforms during the iterative manufacturing process. Finally, the controller 200 is connected to external memory (EEPROM) , 260 for storage and recall of the, inter alia, parameters delineating the correcting waveforms. The ASIC may include a parallel port for extra memory such as ROM, PROM, RAM, and/or EEPROM.

Referring now to Figure 4, a more detailed diagram is provided depicting an internal block diagram of the ASIC controller and its interconnects with the rest of the

monitor systems. In this context, the controller 200 has three sync inputs for generating synchronizing signals which are processed by the ASIC via sync input separator, block 310. These input signals include horizontal and composite sync, vertical sync and video sync and are TTL compatible and Schmidt triggered buffered. A priority detector, block 320, is connected to the sync input separator and automatically controls the input selection between horizontal and composite sync and video sync, with the horizontal and composite sync given priority.

It has been found that the external video generators may include serration and equalization pulses during the vertical blanking period that often cause the horizontal synchronizer to slew. To alleviate this difficulty, the controller 200 includes a serration mask, 330, for the removal of these pulses. This permits the acceptance of both interlace and non-interlace formats for image processing. Also, the mask will eliminate noise pulses that happen during the mask period providing higher noise immunity.

Continuing with Fig. 4, attention is now directed to the command processor portion of the ASIC, i.e., the brains of the controller depicted as command processor 40. As can be seen, the command processor is linked to most of the integrated subsystems via internal address/data bus 345 and provided the separated horizontal and vertical sync signals from sync input separator 310. The ASIC internal address/data bus 345 interface is depicted throughout this Figure in double line format. On power up, boot ROM, block 360, provides the initialization instructions to the command processor 340 which then looks via the serial bus interface 370 to external EEPROM 260 for programming commands and data. The instructions and data, including waveform parameters are then accessed and stored in program RAM, 380.

The foregoing diagram depicts a chip having a 44 pin interconnect; the pin number and overall circuit layout on the silicon is a matter of design choice and additional pin arrangements may be provided for more functionality or to facilitate the layout of circuitry on the chip in accordance with per se well known semi-conductor design optimization techniques.

The operation of the ASIC controller entails loading the distortion correcting waveform parameters in specific RAM locations and guiding the output of these waveforms in timed relation to the video signal. Continuing in Fig. 4, two modules for distortion correction waveforms are exemplified at block 390 (vertical rate RAM) and block 400 (horizontal rate RAM) . The timed output of these memory locations is received by the interface digital to analog convertors (DACs) , block 395 and 405, respectively. The DACs convert the digital data stream into analog waveforms that are then used in combination with the governing video signal to provide an essentially distortion free image to the monitor screen.

A more detailed presentation of how this is implemented is depicted in Fig. 5, which describes in block diagram form how the vertical rate correction waveforms are generated and applied to the display to cancel out image distortion associated with the monitor. In operation, the vertical period is divided into 256 discrete segments, each residing in a separate memory location. Accurate waveform generation is maintained by the vertical rate address clock (256VSYN) . The vertical rate is calculated by taking the horizontal line counter, block 510, divided by N, the number of horizontal lines in a vertical period, block 520. The 256_H clock (rate 256 times the horizontal sync input) is divided down by the number of horizontal sync pulses in a vertical period. By adopting this approach, the system has the flexibility to process image signals representing different timing

formats and having multiple sync frequencies (multi-sync) without frequency dependent errors.

The timed output of the digital correction waveforms is sequentially controlled by the address counter, block 530. The counter is reset at the beginning of each vertical period by VSYN or by the counter overflow output A7 + 1. The use of the overflow output ensures that the vertical deflection drive waveforms remain active even during a loss of the external timing signals. Continuing with Fig. 3, in the present implementation, the vertical rate waveforms are stored within the five RAM locations. VDY(l-5) RAM outputs include a 2X interpolator (digital) to provide an effective 256 segments to the DACs. Each RAM has 128 byte addressable registers which correspond to the segments of the display undergoing correction; these are shown in Fig. 5 in blocks 540-580. The waveforms are loaded into the appropriate RAM registers as instructed by the command processor over the internal address/data bus and outputted to a corresponding DAC in timed relationship to reconstruct the correcting waveform in analog form.

In the context of this particular implementation, the output from the DACs are depicted as VDY(l-5) ; the resulting waveforms are presented in general terms in Fig. 6. In this regard, VDY1 is a three function output for the vertical deflection drive, and specifically effects vertical linearity correction, DC centering, and vertical size. VDY2 is also a three function output used for pin cushion correction and horizontal size control. VDY(3-5) are each single function outputs for vertical focus, vertical convergence and horizontal pin cushion balance and centering.

Turning now to Fig. 7, the horizontal waveform generator is shown in block diagram form. The horizontal rate correction waveforms are digitally generated and used to align the display geometry of the image on screen. The

waveform correction parameters comprising the correction values are stored in RAM at three addressable locations. The RAM locations, blocks 610-630 each include 64 6 bit registers corresponding to specific segments in the display for timed release via clock input 64FH to the output DACs, blocks 640-660. The counter, block 600 is reset by the horizontal drive pulse HD, thus locking the waveform output to the actual scan period. These three outputs are all single function controls and in this implementation directed to horizontal focus, horizontal linearity and horizontal convergence. All waveform parameters such as amplitude and offset are included in the programming of the waveform memory.

The correction waveform outputs from each respective DAC are generally depicted in Fig. 8. In this regard, correction values in block 610 are associated with horizontal focus output VDY6. The correction values for block 620 are associated with horizontal linearity output VDY7. The correction values stored at block 630 are associated with horizontal convergence output VDY8.

Returning back to Fig. 4, the static adjustment and alignment of the monitor functions are controlled via outputs from the static RAM control, 410 as directed through DAC 415 and multiplexed sample/hold outputs 420. The primary purpose of this subsystem is the calibration of the video amplifiers and CRT bias voltage with associated outputs VST1-8. The controlling constants are loaded into RAM memory by the command processor 340 via internal data/control bus 345. Information in analog form is often collected for, e.g. , DC or slow varying time measurements of monitor controls. These inputs are selected by analog multiplexer, 430 and converted to digital form by ADC (analog to digital converter) , 435 for input to the command processor 340 via internal bus 345. These inputs

may be for such controls as contrast, brightness and automatic beam limiting compensation.

The other remaining functions for the processor 200 include primary phase detection 440 and secondary phase detection 450. Phase compensation is required to address image drift caused by temperature swings during operation.

The command processor compensates for this distortion by applying variable gain values to the phase locked oscillator 445 that has a high gain on lock, but low gain to track the signal.

The above-described arrangement is merely illustrative of the principles of the present invention.

Numerous modifications and adaptations thereof will be readily apparent to those skilled in the art without departing from the spirit and scope of the present invention.