Title:
PROCESSING DEVICE AND ERROR DETECTION METHOD
Document Type and Number:
WIPO Patent Application WO/2023/175685
Kind Code:
A1
Abstract:
This processing device comprises: a plurality of computation circuits that operate on the basis of a clock signal supplied from a clock generation circuit; a distribution circuit for branching the clock signal and outputting the branched clock signals to the plurality of computation circuits; and a detection circuit for comparing the outputs of the plurality of computation circuits and detecting errors. At least one computation circuit is connected to the distribution circuit via a conversion circuit for converting the clock signal to a clock signal for which a clock signal abnormality can be detected when an abnormality occurs in the clock signal.
Inventors:
SUGITA KENICHI (JP)
OGURI HIDEYUKI (JP)
YAMAUCHI TAKAO (JP)
MIZOSOE HIROKI (JP)
OGURI HIDEYUKI (JP)
YAMAUCHI TAKAO (JP)
MIZOSOE HIROKI (JP)
Application Number:
PCT/JP2022/011402
Publication Date:
September 21, 2023
Filing Date:
March 14, 2022
Export Citation:
Assignee:
HITACHI INFORMATION & TELECOMMUNICATION ENG LTD (JP)
International Classes:
H03K21/38; G06F1/04
Foreign References:
| JP2017033325A | 2017-02-09 | |||
| JP2006287736A | 2006-10-19 | |||
| JP2001313547A | 2001-11-09 | |||
| JPH1020961A | 1998-01-23 |
Attorney, Agent or Firm:
TOU-OU PATENT FIRM (JP)
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