Title:
PROCESSOR AND CALCULATION METHOD
Document Type and Number:
WIPO Patent Application WO/2011/162310
Kind Code:
A1
Abstract:
Disclosed is a processor that can efficiently execute DFT calculations without having part of a basic arithmetic circuit idle even during non-DFT-calculation processing. The processor (1) has a calculation means (calculation unit) (2) and a control means (control unit) (3). The calculation means (2) has a plurality of shift addition/subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) calculations can be executed. The shift adding/subtracting means also execute shift addition/subtraction processing of butterfly calculations that process shift addition/subtraction for one stage or more. The control means (3) instructs the calculation means (2) to execute either CORDIC calculations or butterfly calculations, based on a plurality of data received from the outside.
More Like This:
Inventors:
SEKI, Katsutoshi (7-1Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Application Number:
JP2011/064324
Publication Date:
December 29, 2011
Filing Date:
June 16, 2011
Export Citation:
Assignee:
NEC CORPORATION (7-1Shiba 5-chome, Minato-ku Tokyo, 01, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 〒1088001, JP)
International Classes:
G06F7/00; G06F1/02; G06F7/548; G06F17/14
Attorney, Agent or Firm:
SHIMOSAKA, Naoki (7-1Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Download PDF:
Claims: