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Patent Searching and Data


Title:
PROCESSOR ELEMENT, PROGRAMMABLE DEVICE, AND PROCESSOR ELEMENT CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2019/059153
Kind Code:
A1
Abstract:
In order to provide a processor element and a programmable device, which have little restriction on logical block arrangement and wiring, and which can improve the degree of integration, this processor element 1 includes: an arithmetic unit 11 that performs arithmetic processing on the basis of a function which has implemented an instruction set generated in accordance with a program; a register 12 that stores an argument of the function; a bypass switch 13 of the arithmetic unit 11; a bypass switch 14 of the register 12; a connection setting unit 16 that switches the connection of a function unit 20; a multiplexer 17 that switches the input to the connection setting unit 16; a de-multiplexer 18 that switches the output destination of the output from the connection setting unit 16; and a selection unit 15 that switches, in accordance with a state, the bypass switches 13, 14, the connection setting unit 16, the multiplexer 17 and the de-multiplexer 18.

Inventors:
HIHARA HIROKI (JP)
Application Number:
PCT/JP2018/034379
Publication Date:
March 28, 2019
Filing Date:
September 18, 2018
Export Citation:
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Assignee:
NEC SPACE TECH LTD (JP)
International Classes:
G06F7/57; G06F15/80; G06F9/445; G06F15/173
Foreign References:
JP2012221149A2012-11-12
JP2011008519A2011-01-13
JP2007179358A2007-07-12
JP2017183690A2017-10-05
Other References:
See also references of EP 3690666A4
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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