Title:
PROCESSOR REGISTER ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO2008110802
Kind Code:
B1
Abstract:
The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle activity from at least one specified source. The processor also comprises a thread scheduler for scheduling a plurality of threads to be executed by the execution unit, said scheduling being based on the respective activity handled by the threads; and a plurality of sets of registers connected to the execution unit. Each set of registers is arranged to store information representing a respective one of the plurality of threads, at least a part of the information being accessible by the execution unit for use in executing the respective thread when scheduled.
Inventors:
MAY DAVID (GB)
Application Number:
PCT/GB2008/000874
Publication Date:
November 13, 2008
Filing Date:
March 13, 2008
Export Citation:
Assignee:
XMOS LTD (GB)
MAY DAVID (GB)
MAY DAVID (GB)
International Classes:
G06F9/48; G06F9/38
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