Title:
PROGRAMMABLE DUAL-EDGE TRIGGERED COUNTER
Document Type and Number:
WIPO Patent Application WO2004068706
Kind Code:
A3
Abstract:
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further determine whether the falling edge of the output clock should be triggered by the rising or the falling edge of the falling edge of the input clock signal. The counter may be implemented as a M/N:D counter in which a phase accumulator is compared to predetermined values to select the rising and falling edges of the output clock signal. The designed architecture also produces an inverted output clock signal whose characteristics are identical to the non-inverted output clock signal (with the exception of duty cycle, which is inverted).
Inventors:
SEVERSON MATTHEW L (US)
Application Number:
PCT/US2004/002715
Publication Date:
November 04, 2004
Filing Date:
January 30, 2004
Export Citation:
Assignee:
QUALCOMM INC (US)
SEVERSON MATTHEW L (US)
SEVERSON MATTHEW L (US)
International Classes:
H03K5/156; H03K21/10; H03K23/68; (IPC1-7): H03K5/156; H03K23/68
Foreign References:
| US6449329B1 | 2002-09-10 | |||
| US6404840B1 | 2002-06-11 | |||
| US6489817B1 | 2002-12-03 |
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