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Title:
PROGRAMMABLE LOGIC DEVICE AND ITS DESIGNING METHOD
Document Type and Number:
WIPO Patent Application WO/2005/091357
Kind Code:
A1
Abstract:
A programmable logic device comprising programmable elements, of which the power consumption and the area can be reduced. The programmable logic device (101) comprises a first logic element (102), and a second logic element (104) having the same logic as that of the first logic element (102) and the design limit of an operating speed lower than that of the first logic element (102).

Inventors:
MORI ATSUHIRO
MARUI SHINICHI
OKAMOTO MINORU
Application Number:
PCT/JP2005/004221
Publication Date:
September 29, 2005
Filing Date:
March 10, 2005
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
MORI ATSUHIRO
MARUI SHINICHI
OKAMOTO MINORU
International Classes:
H01L21/82; H01L27/088; H01L27/118; H01L21/8234; (IPC1-7): H01L21/82; H01L21/8234; H01L27/088
Domestic Patent References:
WO2003001591A12003-01-03
Foreign References:
JPH07297291A1995-11-10
US20030016055A12003-01-23
US20020100944A12002-08-01
JPH07161938A1995-06-23
JPH0766373A1995-03-10
Attorney, Agent or Firm:
Takamatsu, Takeshi (7-13 Nishi-Shimbashi, 1-chom, Minato-ku Tokyo 03, JP)
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