Title:
PROGRAMMABLE LOGIC INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2015/141153
Kind Code:
A1
Abstract:
In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.
Inventors:
NEBASHI RYUSUKE (JP)
MIYAMURA MAKOTO (JP)
SAKIMURA NOBORU (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
MIYAMURA MAKOTO (JP)
SAKIMURA NOBORU (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
Application Number:
PCT/JP2015/001049
Publication Date:
September 24, 2015
Filing Date:
February 27, 2015
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H01L21/82; H03K19/173; H03K19/177
Domestic Patent References:
| WO2013136798A1 | 2013-09-19 | |||
| WO2007032184A1 | 2007-03-22 |
Foreign References:
| JP2002009156A | 2002-01-11 | |||
| JPH04146664A | 1992-05-20 | |||
| JPS4919780A | 1974-02-21 | |||
| JP2004214619A | 2004-07-29 |
Attorney, Agent or Firm:
SHIMOSAKA, NAOKI (JP)
Naoki Shimosaka (JP)
Naoki Shimosaka (JP)
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