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Title:
PROTECTION LAYERS FOR MAGNETIC TUNNEL JUNCTIONS
Document Type and Number:
WIPO Patent Application WO/2018/125142
Kind Code:
A1
Abstract:
Embodiments herein describe techniques for a semiconductor device, which includes a bottom electrode, and a MTJ pillar above the bottom electrode, where the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack. A portion of a surface of the bottom electrode does not overlap with the MTJ pillar. The device may further include a hermetic dielectric capping layer that conformally covers the MTJ pillar and the portion of the surface of the bottom electrode. The hermetic dielectric capping layer may be a protection layer formed at lower temperatures without adversely impacting the performance of the protected MTJ stack. Other embodiments may be described and/or claimed.

Inventors:
O'BRIEN KEVIN P (US)
CLENDENNING SCOTT B (US)
OGUZ KAAN (US)
DOCZY MARK L (US)
DOYLE BRIAN S (US)
RAHMAN TOFIZUR (US)
WIEGAND CHRISTOPHER J (US)
GOLONZKA OLEG (US)
GHANI TAHIR (US)
Application Number:
PCT/US2016/069222
Publication Date:
July 05, 2018
Filing Date:
December 29, 2016
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
INTEL CORP (US)
International Classes:
H01L43/02; H01L43/08; H01L43/10; H01L43/12
Foreign References:
US20150311433A12015-10-29
US20160293838A12016-10-06
US20150235844A12015-08-20
US20160332867A12016-11-17
US20120122312A12012-05-17
Attorney, Agent or Firm:
WANG, Yuke et al. (US)
Download PDF:
Claims:
Claims

What is claimed is:

1. A method for forming a semiconductor device, the method comprising: forming a bottom electrode;

forming a magnetic tunnel junction (MTJ) stack above the bottom electrode, wherein the MTJ stack includes a free layer and a reference layer, and wherein a portion of the bottom electrode adjacent to the MTJ stack is exposed after forming the MTJ stack;

forming a top electrode above the MTJ stack; and

forming a hermetic dielectric capping layer, wherein the hermetic dielectric capping layer conformally covers the top electrode, a side surface of the MTJ stack, and the exposed portion of the bottom electrode.

2. The method of claim 1 , further comprising:

forming another dielectric layer, wherein the another dielectric layer is formed conformally next to the hermetic dielectric capping layer.

3. The method of claim 1 , further comprising:

forming an opening of the hermetic dielectric capping layer to expose the top electrode; and

forming a via within the opening, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode.

4. The method of claim 1, wherein the forming the MTJ stack includes:

forming the MTJ stack above the bottom electrode; and

removing a part of the MTJ stack to expose the portion of the bottom electrode adjacent to the MTJ stack.

5. The method of any of claims 1 -4, wherein the forming the hermetic dielectric capping layer includes forming the hermetic dielectric capping layer in a temperature within a range from 15°C to 400 °C.

6. The method of any of claims 1 -4, wherein the hermetic dielectric capping layer includes a metal oxide, an aluminum nitride, or a boron nitride, and wherein the metal oxide includes an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a hafnium titanate, a zirconium oxide, a zirconium titanate, or a tantalum oxide.

7. The method of any of claims 1 -4, wherein the hermetic dielectric capping layer includes an aluminum oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes trimethyl aluminum (Α1Μβ3), triethyl aluminum (AlEt3), aluminum trichloride (AICI3), or aluminum isopropoxide [Al(OiPr)3], and the coreactant includes water, hydrogen peroxide, oxygen, ozone, methanol, ethanol, isopropanol, tertiary-butanol, formic acid, acetic acid, or carboxylic acid.

8. The method of any of claims 1 -4, wherein the hermetic dielectric capping layer includes an aluminum silicate film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes trimethyl aluminum (Α1Μβ3), and the coreactant includes tris(tert-butoxy)silanol or tris(tert- pentoxy)silanol.

9. The method of any of claims 1 -4, wherein the hermetic dielectric capping layer includes a titanium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes titanium chloride (T1CI4), titanium isopropoxide (Ti(OzPr)4), or tetrakis(amido)titanium, and the coreactant includes water, hydrogen peroxide, oxygen, ozone, methanol, ethanol, isopropanol, tertiary-butanol, formic acid, acetic acid, or carboxylic acid.

10. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a magnesium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes magnesium bis(cyclopentadienyl), and the coreactant includes water.

11. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a hafnium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes hafnium chloride, hafnium tert-butoxide, or tetrakis(ethylmethylamido)hafnium, and the coreactant includes formic acid, acetic acid, or water.

12. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a hafnium titanate film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes hafnium chloride and titanium isopropoxide, and the coreactant includes formic acid, acetic acid, or water. 13. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a zirconium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes zirconium tert- butoxide, or tetrakis(ethylmethylamido)zirconium, and the coreactant includes formic acid, acetic acid, or water.

14. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a zirconium titanate film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes zirconium chloride and titanium isopropoxide, and the coreactant includes formic acid, acetic acid, or water.

15. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a tantalum oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes tantalum chloride, tantalum ethoxide or pentakis(dimethylamido)tantalum, and the coreactant includes formic acid, acetic acid, or water.

16. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes an aluminum nitride film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes tris(dimethylamido)aluminum, and the coreactant includes hydrogen plasma, hydrazine, dimethylhydrazine, or tert-butylhydrazine. The method of any of claims 1-4, wherein the hermetic dielectric capping layer includes a boron nitride film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes boron chloride or triethylboron (BEt3), and the coreactant includes ammonia plasma, hydrazine, dimethylhydrazine, or tert-butylhydrazine.

18. A semiconductor device, comprising:

a bottom electrode;

a magnetic tunnel junction (MTJ) pillar above the bottom electrode, wherein the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack, and wherein a portion of a surface of the bottom electrode does not overlap with the MTJ pillar; and

a hermetic dielectric capping layer that conformally covers the MTJ pillar and the portion of the surface of the bottom electrode.

19. The semiconductor device of claim 18, further comprising:

another dielectric layer, wherein the another dielectric layer is disposed conformally next to the hermetic dielectric capping layer.

20. The semiconductor device of claim 18, further comprising:

a via, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode.

21. The semiconductor device of any of claims 18-20, wherein the hermetic dielectric capping layer includes a metal oxide, an aluminum nitride, or a boron nitride, and wherein the metal oxide includes an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a hafnium titanate, a zirconium oxide, a zirconium titanate, or a tantalum oxide.

An electrical system comprising:

a processor;

a display coupled to the processor; and

a memory device coupled to the processor, the memory device including a magnetic random access memory (MRAM) memory cell, and the R AIM memory cell including:

a bottom electrode;

a magnetic tunnel junction (MTJ) pillar above the bottom electrode, wherein the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack, and wherein a portion of a surface of the bottom electrode does not overlap with the MTJ pillar;

a hermetic dielectric capping layer above the MTJ pillar, wherein the hermetic dielectric capping layer conformally covers the MTJ pillar and the portion of the surface of the bottom electrode; and

a via, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode.

23. The electrical system of claim 22, wherein the hermetic dielectric capping layer includes a metal oxide, an aluminum nitride, or a boron nitride, and wherein the metal oxide includes an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a zirconium oxide, a zirconium titanate, a tantalum oxide, or a hafnium titanate.

24. The electrical system of any of claims 22-23, wherein the MRAM memory cell further includes another dielectric layer disposed conformally next to the hermetic dielectric capping layer.

25. The electrical system of any of claims 22-23, wherein the electrical system is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the memory device.

Description:
PROTECTION LAYERS FOR MAGNETIC TUNNEL JUNCTIONS

Field

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to memory.

Background

The memory system is an important component of modern computers and communication devices. Magnetic random access memory (MRAM) system may play a more and more important role in computers and communication devices. In general, a MRAM memory cell may include a magnetic tunnel junction (MTJ) pillar formed by a MTJ stack. A MRAM memory cell may be formed by various operations using a variety of chemical compounds after the formation of the MTJ stack. During the process of forming the MRAM memory cell, the MTJ stack may be covered by a protection layer to reduce potential damages or degradation that may be caused by the various operations. The protection layer may also increase the long-term reliability of the MRAM memory cell. A silicon nitride (SiN) layer may be deposited by plasma enhanced chemical vapor deposition (CVD) as a protection layer on a MTJ stack. However, the process of depositing a SiN layer by CVD may be a high temperature process that can cause degradation of the magnetic properties of the MTJ stack.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Figure 1 schematically illustrates a diagram of a random access memory array including multiple memory cells, where a memory cell includes a MRAM memory cell, in accordance with some embodiments.

Figures 2(a)-2(f) schematically illustrate a process for forming a protection layer for a MTJ stack in a MRAM memory cell, in accordance with some embodiments.

Figure 3 schematically illustrates another process for forming a protection layer for a MTJ stack in a MRAM memory cell, in accordance with some embodiments.

Figure 4 schematically illustrates an interposer implementing one or more embodiments of the disclosure, in accordance with some embodiments. Figure 5 schematically illustrates a computing device built in accordance with an embodiment of the disclosure, in accordance with some embodiments.

Detailed Description

In general, a MRAM memory cell may represent a logic 0 and a logic 1 by two states with different resistance values, which are switchable upon an application of an electric current or voltage. A MRAM memory cell may include a MTJ pillar formed by a MTJ stack, where the MTJ stack may include a free layer and a reference layer. In some embodiments, a reference layer may also be referred to as a pinned magnetic layer, or a pinned layer. The reference layer may keep its magnetic direction fixed, while the free layer may have its magnetic direction changed by means of either an applied magnetic field or a polarized current. When both the reference layer and the free layer have a same magnetic direction, the MRAM memory cell may have a low resistance value. If the reference layer and the free layer have different magnetic directions, the MRAM memory cell may have a high resistance value.

During the process of forming a MRAM memory cell, the MTJ stack may be covered by a protection layer to reduce potential damage or degradation that may be caused by various operations performed in forming the MRAM memory cell. A silicon nitride (SiN) layer may be deposited by plasma enhanced chemical vapor deposition (CVD) as a protection layer on the MTJ stack. However, SiN is a solid with a high- melting-point. Sometimes, SiN may be processed between 400 °C and 500 °C, or over 1000 °C to form a protection layer. Such a high temperature process may cause degradation of the magnetic properties of the MTJ stack covered by the protection layer including SiN.

In embodiments, a protection layer, e.g., a hermetic dielectric capping layer, may be formed to cover a MTJ stack in the process of forming a MRAM memory cell. The hermetic dielectric capping layer may be a protection layer formed at lower temperatures without adversely impacting the performance of the protected MTJ stack. For example, a hermetic dielectric capping layer may be formed between about room temperature, e.g. , 15 °C, to about 400 °C. Often a hermetic dielectric capping layer may be formed at a temperature below 200 °C.

Embodiments herein may present a semiconductor device, which includes a bottom electrode, and a MTJ pillar above the bottom electrode, where the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack. A portion of a surface of the bottom electrode does not overlap with the MTJ pillar. The device may further include a hermetic dielectric capping layer that conformally covers the MTJ pillar and the portion of the surface of the bottom electrode.

Embodiments herein may present an electrical system, which includes a processor, a display coupled to the processor, and a memory device coupled to the processor. In more detail, the memory device may include a MRAM memory cell, where the MRAM memory cell may include a bottom electrode, and a MTJ pillar above the bottom electrode. The MTJ pillar may include a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack. A portion of a surface of the bottom electrode does not overlap with the MTJ pillar. A hermetic dielectric capping layer may be above the MTJ pillar, conformally covering the MTJ pillar and the portion of the surface of the bottom electrode. The MRAM memory cell may further include a via, where the via is through the hermetic dielectric capping layer and in contact with the top electrode.

In embodiments, a method for forming a semiconductor device may include: forming a bottom electrode; forming a MTJ stack above the bottom electrode, wherein the MTJ stack includes a free layer and a reference layer, and wherein a portion of the bottom electrode adjacent to the MTJ stack is exposed after forming the MTJ stack; and forming a top electrode above the MTJ stack. Afterwards, the method may include forming a hermetic dielectric capping layer on the top electrode and/or MTJ stack. For example, the hermetic dielectric capping layer may conformally cover the top electrode, a side surface of the MTJ stack, and the exposed portion of the bottom electrode. As a result, the hermetic dielectric capping layer may cover the MTJ stack conformally and uniformly, protecting the MTJ stack from damages or degradation that may result from the various operations after the formation of the MTJ stack. The hermetic dielectric capping layer may also increase the long-term reliability of the MRAM memory cell.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The terms "over," "under," "between," "above," and "on" as used herein may refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.

The description may use the phrases "in an embodiment," or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

Where the disclosure recites "a" or "a first" element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.

As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, "computer-implemented method" may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.

Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si02) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV. In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si02), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Figure 1 schematically illustrates a diagram of a random access memory array 100 including multiple memory cells (e.g., a memory cell 102, a memory cell 104, a memory cell 106, and a memory cell 108), where a memory cell, e.g., the memory cell 102, includes a MRAM memory cell, e.g., a MRAM memory cell 110, in accordance with some embodiments. In embodiments, the multiple memory cells may be arranged in a number of rows and columns coupled by bit lines, e.g., bit line Bl and bit line B2, and word lines, e.g., word line Wl and word line W2.

A memory cell, e.g., the memory cell 102, may be coupled in series with other memory cells, e.g., the memory cell 106, of the same row, and may be coupled in parallel with the memory cells of other rows, e.g., the memory cell 104 and the memory cell 108. The memory array 100 may include any suitable number of one or more memory cells. Although the memory array 100 is shown in Figure 1 with two rows that each includes two memory cells coupled in series, other embodiments may include other numbers of rows and/or numbers of memory cells within a row. In some embodiments, the number of rows may be different from the number of columns in a memory array. Each row of the memory array may have a same number of memory cells. Additionally, or alternatively, different rows may have different numbers of memory cells.

In embodiments, multiple memory cells, such as the memory cell 102, the memory cell 104, the memory cell 106, and the memory cell 108, may have a similar configuration. For example, the memory cell 102 may include a selector 112 and the MRAM memory cell 110. A memory cell may be controlled through a selector coupled to a bit line and a word line to read from the memory cell, write to the memory cell, and/or perform other memory operations. For example, the selector 112 may have an electrode 101 coupled to the word line Wl, and the MRAM memory cell 110 may have an electrode 109 coupled to the bit line Bl. In addition, the selector 112 and the MRAM memory cell 110 may be coupled together by the electrode 107.

In embodiments, the selector 112 may switch between an "on" state and an "off state depending on the amount of current or voltage applied across the selector 112. The selector 112 may control the MRAM memory cell 110, which is switchable between two states with different resistance values upon an application of an electric current or voltage. When the word line Wl is active, the selector 112 may select the MRAM memory cell 110. A signal from the word line Wl may pass through the selector 112, further through the MRAM memory cell 110, and reaching the other electrode, which is coupled to the bit line Bl.

In embodiments, the MRAM memory cell 110 may be a traditional MRAM, a spin-transfer torque (STT)-MRAM, or others. The MRAM memory cell 110 may include a MTJ stack having a reference layer and a free layer. The MRAM memory cell 110 may be in a first state (e.g., to store a logic 0) when the reference layer and the free layer of the MTJ stack of the MRAM memory cell 110 have a same magnetic direction resulting in a low resistance value of the MTJ stack. The MRAM memory cell 110 may be in a second state (e.g., to store a logic 1) when the reference layer and the free layer of the MTJ stack of the MRAM memory cell 110 have a different magnetic direction resulting in a high resistance value of the MTJ stack. In embodiments, the resistance difference between the low resistance value and the high resistance value may be one or more orders of magnitude.

In various embodiments, the memory cells, e.g., the memory cell 102, the memory cell 104, the memory cell 106, and the memory cell 108, included in the memory array 100 may be formed in back-end-of-line (BEOL) processing. Accordingly, the memory array 100 may be formed in higher metal layers, e.g., metal layer three and/or metal layer four, of the integrated circuit above the active substrate region, and may not occupy the active substrate area that is occupied by conventional transistors or memory devices.

Figures 2(a)-2(f) schematically illustrate a process 200 for forming a protection layer, e.g., a hermetic dielectric capping layer 217, for a MTJ stack 213 in a MRAM memory cell 210, in accordance with some embodiments. In embodiments, the MRAM memory cell 210 may be an example of the MRAM memory cell 110 in Figure 1.

As shown in Figure 2(a), the MRAM memory cell 210 may include a bottom electrode 211, a MTJ stack 213, and a top electrode 215, formed above a substrate 201. The bottom electrode 211 may be above the substrate 201. The MTJ stack 213 may be above the bottom electrode 21 1, and the top electrode 215 may be above the MTJ stack 213.

In embodiments, the substrate 201 may be a bulk-silicon substrate, or another suitable substrate. The substrate 201 may include an inter-metal dielectric layer, active devices, or passive devices, not shown for clarity.

In embodiments, the bottom electrode 211 or the top electrode 215 may include a single layer conductive material or multi-layer stack including conductive and dielectric materials. The bottom electrode 21 1 or the top electrode 215 may include a conductive material, such as a metal or a metal alloy. For example, the bottom electrode 21 1 or the top electrode 215 may include copper, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, and/or a combination thereof. The bottom electrode 21 1 or the top electrode 215 may be formed by acceptable deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and/or a combination thereof.

In embodiments, the MTJ stack 213 may include various layers formed of different combinations of materials. For example, the MTJ stack 213 may include a reference layer and a free layer. In embodiments, the reference layer may include platinum manganese (PtMn) and the free layer may include cobalt iron boron (CoFeB). In addition, the MTJ stack 213 may include a tunnel barrier layer or a barrier layer, an anti-ferro-magnetic layer, or others.

As shown in Figure 2(b), a MTJ pillar 220 may be formed above the bottom electrode 221 , where the MTJ pillar 220 may include the MTJ stack 213 and the top electrode 215. The MTJ pillar 220 may be formed by removing a part of the MTJ stack 213 and the top electrode 215 to expose a portion 212 of the bottom electrode 211 adjacent to the MTJ stack 213, so that the portion 212 of a surface of the bottom electrode 21 1 does not overlap with the MTJ pillar 220. In some embodiments, the MTJ pillar 220 may be formed by depositing a hard mask over the top electrode 215, where the hard mask may include silicon oxynitride or silicon oxide, and then etching away portion of the MTJ stack 213 and the top electrode 215 that are exposed by the hard mask.

As shown in Figure 2(c), a protection layer, e.g., a hermetic dielectric capping layer 217, may be formed that conformally covers the MTJ pillar 220 and the portion 212 of the surface of the bottom electrode 21 1. For example, the hermetic dielectric capping layer 217 may follow the contour of the MTJ pillar 220, covering a top surface and the side surfaces of the MTJ pillar 220, and the portion 212 of the surface of the bottom electrode 211. Furthermore, the hermetic dielectric capping layer 217 may have a uniform thickness relative to the top surface and the side surfaces of the MTJ pillar 220, and the portion 212 of the surface of the bottom electrode 211. In some embodiments, the hermetic dielectric capping layer 217 may have a thickness in about 2 nm to about 10 nm, relative to the surface of the bottom electrode 211, or the top surface and the side surfaces of the MTJ pillar 220.

In embodiments, the hermetic dielectric capping layer 217 may include a metal oxide, an aluminum nitride, or a boron nitride. In more detail, the metal oxide may include an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a hafnium titanate, a zirconium oxide, a zirconium titanate, or a tantalum oxide. More details of forming the hermetic dielectric capping layer 217 may be provided in the description for Figure 3.

As shown in Figure 2(d), an optional dielectric layer, e.g., a layer 219, may be further formed conformally next to the hermetic dielectric capping layer 217. The layer 219 may include one of the materials described above for the hermetic dielectric capping layer 217, or a silicon nitride layer.

As shown in Figure 2(e), an opening 220 may be formed on the hermetic dielectric capping layer 217 to expose the top electrode 215. If there is an optional dielectric layer, e.g., the layer 219, the opening 220 may also be formed completely through the layer 219 to expose the top electrode 215.

As shown in Figure 2(f), a via 221 may be formed within the opening 220, wherein the via 221 may be formed through the hermetic dielectric capping layer 217 and in contact with the top electrode 215. If there is an optional dielectric layer, e.g., the layer 219, the via 221 may also be completely through the layer 219 to be in contact with the top electrode 215. In addition, an interconnect 223 may be formed in contact with the via 221. In embodiment, the interconnect 223 may be the electrode 109 in Figure 1 to be connected to a bit line or a word line. The via 221 and the interconnect 223 may include a conductive material, e.g., copper, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, and/or a combination thereof.

Figure 3 schematically illustrates another process 300 for forming a protection layer for a MTJ stack in a MRAM memory cell, in accordance with some embodiments. In embodiments, the process 300 may be applied to form the MRAM memory cell 210 with the hermetic dielectric capping layer 217, as shown in Figure 2.

At block 301, the process 300 may include forming a bottom electrode. For example, the process 300 may include forming the bottom electrode 211 over the substrate 201 as illustrated in Figure 2(a).

At block 303, the process 300 may include forming a MTJ stack above the bottom electrode, where the MTJ stack may include a free layer and a reference layer. In addition, a portion of the bottom electrode adjacent to the MTJ stack may be exposed after forming the MTJ stack. For example, the process 300 may include forming the MTJ stack 213 over the bottom electrode 211 as illustrated in Figure 2(a). In embodiments, the MTJ stack 213 may include a free layer and a reference layer, as described for the MTJ stack 213 in Figure 2(a). The portion 212 of the bottom electrode 21 1 adjacent to the MTJ stack 213 may be exposed, so that the portion 212 of a surface of the bottom electrode 21 1 does not overlap with the MTJ stack 213, as illustrated in Figure 2(b).

At block 305, the process 300 may include forming a top electrode above the MTJ stack. For example, the process 300 may include forming the top electrode 215 over the MTJ stack 213 as illustrated in Figure 2(b). In embodiments, the top electrode 215 and the MTJ stack 213 together form the MTJ pillar 220.

At block 307, the process 300 may include forming a hermetic dielectric capping layer, where the hermetic dielectric capping layer may conformally cover the top electrode, a side surface of the MTJ stack, and the exposed portion of the bottom electrode. For example, the process 300 may include forming the hermetic dielectric capping layer 217 conformally covering the top electrode 215, a side surface of the MTJ stack 213, and the exposed portion 212 of the bottom electrode 21 1, as illustrated in Figure 2(c).

In embodiments, the hermetic dielectric capping layer 217 may include a metal oxide, an aluminum nitride, or a boron nitride. In more detail, the metal oxide may include an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a hafnium titanate, a zirconium oxide, a zirconium titanate, or a tantalum oxide. The hermetic dielectric capping layer 217 may be formed in a temperature within a range from about 15 °C to about 400 °C, e.g., 200 °C.

In embodiments, the hermetic dielectric capping layer 217 may be formed by ALD, which may be considered as a subclass of CVD. ALD is a thin film deposition technique that is based on the sequential use of a gas phase chemical process. In embodiments, ALD reactions may use two chemicals, typically called a precursor and a coreactant. The precursor and the coreactant react with the surface of a material one at a time in a sequential manner. Through the repeated exposure to the precursor and the coreactant, a thin film may be deposited at the surface of the material.

In embodiments, the hermetic dielectric capping layer 217 may include an aluminum oxide film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include trimethyl aluminum (Α1Μβ 3 ), triethyl aluminum (AlEt 3 ), aluminum trichloride (AICI 3 ), or aluminum isopropoxide [Al(OiPr) 3 ], and the coreactant may include water, hydrogen peroxide, oxygen, ozone, methanol, ethanol, isopropanol, tertiary-butanol, formic acid, acetic acid, or carboxylic acid.

In embodiments, the hermetic dielectric capping layer 217 may include an aluminum silicate film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include trimethyl aluminum (Α1Μβ 3 ), and the coreactant may include tris(tert-butoxy)silanol or tris(tert-pentoxy)silanol.

In embodiments, the hermetic dielectric capping layer 217 may include a titanium oxide film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include titanium chloride (T1CI 4 ), titanium isopropoxide (Ti(OzPr) 4 ), or tetrakis(amido)titanium, and the coreactant may include water, hydrogen peroxide, oxygen, ozone, methanol, ethanol, isopropanol, tertiary-butanol, formic acid, acetic acid, or carboxylic acid.

In embodiments, the hermetic dielectric capping layer 217 may include a magnesium oxide film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include magnesium bis(cyclopentadienyl), and the coreactant may include water.

In embodiments, the hermetic dielectric capping layer 217 may include a hafnium oxide film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include hafnium chloride, hafnium tert-butoxide, or tetrakis(ethylmethylamido)hafnium, and the coreactant may include formic acid, acetic acid, or water.

In embodiments, the hermetic dielectric capping layer 217 may include a hafnium titanate film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include hafnium chloride and titanium isopropoxide, and the coreactant may include formic acid, acetic acid, or water.

In embodiments, the hermetic dielectric capping layer 217 may include a zirconium oxide film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include zirconium tert-butoxide, or tetrakis(ethylmethylamido)zirconium, and the coreactant may include formic acid, acetic acid, or water.

In embodiments, the hermetic dielectric capping layer 217 may include a zirconium titanate film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include zirconium chloride and titanium isopropoxide, and the coreactant may include formic acid, acetic acid, or water.

In embodiments, the hermetic dielectric capping layer 217 may include a tantalum oxide film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include tantalum chloride, tantalum ethoxide or pentakis(dimethylamido)tantalum, and the coreactant may include formic acid, acetic acid, or water.

In embodiments, the hermetic dielectric capping layer 217 may include an aluminum nitride film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include tris(dimethylamido)aluminum, and the coreactant may include hydrogen plasma, hydrazine, dimethylhydrazine, or tert-butylhydrazine.

In embodiments, the hermetic dielectric capping layer 217 may include a boron nitride film formed by a metal precursor and a coreactant using ALD. In more detail, the metal precursor may include boron chloride or triethylboron (BEt 3 ), and the coreactant may include ammonia plasma, hydrazine, dimethylhydrazine, or tert-butylhydrazine.

At block 309, the process 300 may include forming another dielectric layer, where the another dielectric layer may be formed conformally next to the hermetic dielectric capping layer. For example, the process 300 may include forming an optional dielectric layer, e.g., the layer 219, conformally next to the hermetic dielectric capping layer 217, as illustrated in Figure 2(d). In embodiments, the optional dielectric layer, e.g., the layer 219, may include one of the materials described above may for the hermetic dielectric capping layer 217, or a silicon nitride layer.

At block 311 , the process 300 may include forming an opening of the hermetic dielectric capping layer to expose the top electrode. For example, the process 300 may include forming the opening 220 on the hermetic dielectric capping layer 217 to expose the top electrode 215, as illustrated in Figure 2(e). The opening 220 may also be completely through the optional dielectric layer, e.g., the layer 219, to expose the top electrode 215.

At block 313, the process 300 may include forming a via within the opening, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode. For example, the process 300 may include forming the via 221 within the opening 220, wherein the via 220 is through the hermetic dielectric capping layer 217 and in contact with the top electrode 215, as illustrated in Figure 2(f).

Figure 4 illustrates an interposer 400 that includes one or more embodiments of the disclosure. The interposer 400 is an intervening substrate used to bridge a first substrate 402 to a second substrate 404. The first substrate 402 may be, for instance, an integrated circuit die, including the memory array 100 shown in Figure 1 or the MRAM memory cell 210 shown in Figures 2(a)-2(f). The second substrate 404 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 400 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 400 may couple an integrated circuit die to a ball grid array (BGA) 406 that can subsequently be coupled to the second substrate 404. In some embodiments, the first and second substrates 402/404 are attached to opposing sides of the interposer 400. In other embodiments, the first and second substrates 402/404 are attached to the same side of the interposer 400. And in further embodiments, three or more substrates are interconnected by way of the interposer 400.

The interposer 400 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 412. The interposer 400 may further include embedded devices 414, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 400.

In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 400.

Figure 5 illustrates a computing device 500 in accordance with one embodiment of the disclosure. The computing device 500 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices. The components in the computing device 500 include, but are not limited to, an integrated circuit die 502 and at least one communications logic unit 508. In some implementations the communications logic unit 508 is fabricated within the integrated circuit die 502 while in other implementations the communications logic unit 508 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 502. The integrated circuit die 502 may include a processor 504 as well as on-die memory 506, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), SRAM, MRAM, or spin-transfer torque memory (STT-MRAM). For example, the on- die memory 506 may include the memory array 100 shown in Figure 1, the MRAM memory cell 210 shown in Figure 2, or a MRAM memory cell formed according to the process 300 shown in Figure 3.

Computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 510 (e.g., dynamic random access memory (DRAM), non-volatile memory 512 (e.g., ROM or flash memory), a graphics processing unit 514 (GPU), a digital signal processor (DSP) 516, a crypto processor 542 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 520, at least one antenna 522 (in some implementations two or more antenna may be used), a display or a touchscreen display 524, a touchscreen display controller 526, a battery 530 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 528, a compass, a motion coprocessor or sensors 532 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 534, a camera 536, user input devices 538 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 540 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 500 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 500 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 500 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

The communications logic unit 508 enables wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 508 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communications logic units 508. For instance, a first communications logic unit 508 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 508 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 504 of the computing device 500 includes one or more devices, such as transistors. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communications logic unit 508 may also include one or more devices, such as transistors.

In further embodiments, another component housed within the computing device 500 may contain one or more devices, such as MRAM, or spin-transfer torque memory (STT-MRAM), that are formed in accordance with implementations of the current disclosure, e.g., the memory array 100 shown in Figure 1, the MRAM memory cell 210 shown in Figure 2, or a MRAM memory cell formed according to the process 300 shown in Figure 3.

In various embodiments, the computing device 500 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

Some non-limiting Examples are provided below.

Example 1 may include a method for forming a semiconductor device, the method comprising: forming a bottom electrode; forming a magnetic tunnel junction (MTJ) stack above the bottom electrode, wherein the MTJ stack includes a free layer and a reference layer, and wherein a portion of the bottom electrode adjacent to the MTJ stack is exposed after forming the MTJ stack; forming a top electrode above the MTJ stack; and forming a hermetic dielectric capping layer, wherein the hermetic dielectric capping layer conformally covers the top electrode, a side surface of the MTJ stack, and the exposed portion of the bottom electrode.

Example 2 may include the method of example 1 and/or some other examples herein, further comprising: forming another dielectric layer, wherein the another dielectric layer is formed conformally next to the hermetic dielectric capping layer.

Example 3 may include the method of example 1 and/or some other examples herein, further comprising: forming an opening of the hermetic dielectric capping layer to expose the top electrode; and forming a via within the opening, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode.

Example 4 may include the method of example 1 and/or some other examples herein, wherein the forming the MTJ stack includes: forming the MTJ stack above the bottom electrode; and removing a part of the MTJ stack to expose the portion of the bottom electrode adjacent to the MTJ stack.

Example 5 may include the method of any of examples 1 -4 and/or some other examples herein, wherein the forming the hermetic dielectric capping layer includes forming the hermetic dielectric capping layer in a temperature within a range from 15°C to 400 °C. Example 6 may include the method of any of examples 1 -4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a metal oxide, an aluminum nitride, or a boron nitride, and wherein the metal oxide includes an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a hafnium titanate, a zirconium oxide, a zirconium titanate, or a tantalum oxide.

Example 7 may include the method of any of examples 1 -4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes an aluminum oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes trimethyl aluminum (Α1Μβ 3 ), triethyl aluminum (ΑΙΕΪ 3 ), aluminum trichloride (AICI 3 ), or aluminum isopropoxide [Al(OiPr) 3 ], and the coreactant includes water, hydrogen peroxide, oxygen, ozone, methanol, ethanol, isopropanol, tertiary-butanol, formic acid, acetic acid, or carboxylic acid.

Example 8 may include the method of any of examples 1 -4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes an aluminum silicate film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes trimethyl aluminum (Α1Μβ 3 ), and the coreactant includes tris(tert-butoxy)silanol or tris(tert-pentoxy)silanol.

Example 9 may include the method of any of examples 1 -4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a titanium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes titanium chloride (T1CI 4 ), titanium isopropoxide (Ti(OzPr) 4 ), or tetrakis(amido)titanium, and the coreactant includes water, hydrogen peroxide, oxygen, ozone, methanol, ethanol, isopropanol, tertiary-butanol, formic acid, acetic acid, or carboxylic acid.

Example 10 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a magnesium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes magnesium bis(cyclopentadienyl), and the coreactant includes water.

Example 1 1 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a hafnium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes hafnium chloride, hafnium tert-butoxide, or tetrakis(ethylmethylamido)hafnium, and the coreactant includes formic acid, acetic acid, or water.

Example 12 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a hafnium titanate film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes hafnium chloride and titanium isopropoxide, and the coreactant includes formic acid, acetic acid, or water.

Example 13 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a zirconium oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes zirconium tert-butoxide, or tetrakis(ethylmethylamido)zirconium, and the coreactant includes formic acid, acetic acid, or water.

Example 14 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a zirconium titanate film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes zirconium chloride and titanium isopropoxide, and the coreactant includes formic acid, acetic acid, or water.

Example 15 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a tantalum oxide film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes tantalum chloride, tantalum ethoxide or pentakis(dimethylamido)tantalum, and the coreactant includes formic acid, acetic acid, or water.

Example 16 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes an aluminum nitride film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes tris(dimethylamido)aluminum, and the coreactant includes hydrogen plasma, hydrazine, dimethylhydrazine, or tert- butylhydrazine.

Example 17 may include the method of any of examples 1-4 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a boron nitride film formed by a metal precursor and a coreactant using atomic layer deposition (ALD), and wherein the metal precursor includes boron chloride or triethylboron (BEt 3 ), and the coreactant includes ammonia plasma, hydrazine, dimethylhydrazine, or tert- butylhydrazine.

Example 18 may include a semiconductor device, comprising: a bottom electrode; a magnetic tunnel junction (MTJ) pillar above the bottom electrode, wherein the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack, and wherein a portion of a surface of the bottom electrode does not overlap with the MTJ pillar; and a hermetic dielectric capping layer that conformally covers the MTJ pillar and the portion of the surface of the bottom electrode.

Example 19 may include the semiconductor device of example 18 and/or some other examples herein, further comprising: another dielectric layer, wherein the another dielectric layer is disposed conformally next to the hermetic dielectric capping layer.

Example 20 may include the semiconductor device of example 18 and/or some other examples herein, further comprising: a via, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode.

Example 21 may include the semiconductor device of any of examples 18-20 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a metal oxide, an aluminum nitride, or a boron nitride, and wherein the metal oxide includes an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a hafnium titanate, a zirconium oxide, a zirconium titanate, or a tantalum oxide.

Example 22 may include an electrical system comprising: a processor; a display coupled to the processor; and a memory device coupled to the processor, the memory device including a magnetic random access memory (MRAM) memory cell, and the MRAM memory cell including: a bottom electrode; a magnetic tunnel junction (MTJ) pillar above the bottom electrode, wherein the MTJ pillar includes a MTJ stack having a free layer and a reference layer, and a top electrode above the MTJ stack, and wherein a portion of a surface of the bottom electrode does not overlap with the MTJ pillar; a hermetic dielectric capping layer above the MTJ pillar, wherein the hermetic dielectric capping layer conformally covers the MTJ pillar and the portion of the surface of the bottom electrode; and a via, wherein the via is through the hermetic dielectric capping layer and in contact with the top electrode.

Example 23 may include the electrical system of example 22 and/or some other examples herein, wherein the hermetic dielectric capping layer includes a metal oxide, an aluminum nitride, or a boron nitride, and wherein the metal oxide includes an aluminum oxide, an aluminum silicate, a titanium oxide, a magnesium oxide, a hafnium oxide, a zirconium oxide, a zirconium titanate, a tantalum oxide, or a hafnium titanate.

Example 24 may include the electrical system of any of examples 22-23 and/or some other examples herein, wherein the MRAM memory cell further includes another dielectric layer disposed conformally next to the hermetic dielectric capping layer.

Example 25 may include the electrical system of any of examples 22-23 and/or some other examples herein, wherein the electrical system is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the memory device.

Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and" may be "and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.