Title:
PROVIDING CAPACITY GUARANTEES FOR HARDWARE TRANSACTIONAL MEMORY SYSTEMS USING FENCES
Document Type and Number:
WIPO Patent Application WO/2013/089980
Kind Code:
A3
Abstract:
A method is provided that includes determining a number of outstanding out-of-order instructions in an instruction stream. The method includes determining a number of available hardware resources for executing out-of-order instructions and inserting fencing instructions into the instruction stream if the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. A second method is provided for compiling source code that includes determining a speculative region. The second method includes generating machine-level instructions and inserting fencing instructions into the machine-level instructions in response to determining the speculative region. A processing device is provided that includes cache memory and a processing unit to execute processing device instructions in an instruction stream. The processing device includes an out-of-order speculation supervisor unit to determine hardware resource availability and generate an indication to insert fencing instructions in response to the availability. Computer readable storage media are also provided.
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Inventors:
POHLACK MARTIN T (DE)
HOHMUTH MICHAEL (DE)
DIESTELHORST STEPHAN (DE)
CHRISTIE DAVID (US)
YEN LUKE (US)
HOHMUTH MICHAEL (DE)
DIESTELHORST STEPHAN (DE)
CHRISTIE DAVID (US)
YEN LUKE (US)
Application Number:
PCT/US2012/065958
Publication Date:
March 20, 2014
Filing Date:
November 20, 2012
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC (CA)
POHLACK MARTIN T (DE)
HOHMUTH MICHAEL (DE)
DIESTELHORST STEPHAN (DE)
CHRISTIE DAVID (US)
YEN LUKE (US)
POHLACK MARTIN T (DE)
HOHMUTH MICHAEL (DE)
DIESTELHORST STEPHAN (DE)
CHRISTIE DAVID (US)
YEN LUKE (US)
International Classes:
G06F9/38; G06F9/30
Domestic Patent References:
WO2012040742A2 | 2012-03-29 |
Foreign References:
US7624255B1 | 2009-11-24 | |||
US6708269B1 | 2004-03-16 | |||
EP1973036A2 | 2008-09-24 |
Other References:
TSENG C-W: "COMPILER OPTIMIZATIONS FOR ELIMINATING BARRIER SYNCHRONIZATION", ASSOCIATION FOR COMPUTING MACHINERY, ACM PRESS, NEW YORK, NEW YORK, USA, vol. 30, no. 8, 1 August 1995 (1995-08-01), pages 144 - 155, XP000528325, ISSN: 0362-1340, DOI: 10.1145/209937.209952
Attorney, Agent or Firm:
SINCELL, Mark, W. (Morgan Amerson, P.C.,10333 Richmond, Suite 110, Houston TX, US)
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