An Electronic Device From A Lower Power Mode

Background

[0001 ] Electronic devices, such as computers, electronic appliances, gaming modules, personal digital assistants, and so forth, have various internal electronic components. When an electronic device is idle, it is desirable to place the electronic device into a lower power mode by powering off certain internal electronic

components to reduce power consumption. When activity resumes, the electronic device is awakened from its lower power mode.

Brief Description Of The Drawings

[0002] Some embodiments are described with respect to the following figures:

Fig. 1 is a block diagram of an example system incorporating some

embodiments;

Fig. 2 is a block diagram of another example system incorporating alternative embodiments; and

Fig. 3 is a flow diagram of a process of performing wakeup of an electronic device from a lower power mode in response to a wake message received over a network, according to some embodiments.

Detailed Description

[0003] After an electronic device (e.g., computer, electronic appliance, personal digital assistant, etc.) has been placed into a lower power mode {e.g., standby mode, hibernation mode, and so forth), certain activities can cause the electronic device to be awakened from the lower power mode. In the lower power mode, various electronic components of the electronic device are powered off. Increasing the number of electronic components of the electronic device that are powered off typically leads to increased power savings. Generally, a "lower power mode" of an electronic device refers to a mode of the electronic device in which certain

component(s) of the electronic device are powered off to achieve power savings as compared to a normal mode of operation. To ensure that the electronic device can be awakened from its lower power mode in response to certain activities, some of the electronic components of the electronic device remain powered during the lower power mode of the electronic device.

[0004] One of the activities that can cause the electronic device to be awakened from the lower power mode is a wake message received over a network to which the electronic device is connected. The network can be a wired network or a wireless network. In some examples, the wake message can be a wake-on-LAN (local area network) message— a wake-on-LAN message is also sometimes referred to as a magic packet. The LAN can be a wired LAN or a wireless LAN. The magic packet is a broadcast packet that contains a predefined payload. In some examples, the predefined payload includes a predefined value in combination with an address of the electronic device that is to be awakened by the magic packet. In other examples, a wake message can have other predefined formats. Instead of being a broadcast packet, the wake message can be a message targeted to a particular electronic device.

[0005] To be able to be awakened by a wake message received over a network, certain network interface components are powered even while the electronic device is in a lower power mode. One such component is a physical layer of a network interface controller. Moreover, another layer that typically remains powered is a link layer that is above the physical layer. Such link layer of an electronic device typically remains fully powered to be able to process a wake message received over a network from a link layer of a sending device.

[0006] Maintaining both the physical layer and the link layer fully powered while the electronic device is in the lower power mode can cause power consumption of the electronic device to rise above a target power consumption threshold. In some examples, the target power consumption threshold can be set by a government regulatory agency or by a standard. In specific examples, the power threshold can be 1 .2 watts— in other words, while the electronic device is in the lower power mode, it is desired that the electronic device consume less than or equal to 1 .2 watts of power to satisfy government regulation or a standard. [0007] Although reference is made to 1 .2 watts as a power consumption threshold in specific examples, it is noted that other power consumption thresholds can be set in other examples. Also, the power consumption threshold does not have to be set by government regulation or a standard— rather the power consumption threshold can be a target value set by the manufacturer or seller of an electronic device, or by some other entity.

[0008] In some implementations, the link layer is a media access control (MAC) layer, which provides addressing and channel access control mechanisms. The MAC layer provides an interface between the physical layer and a higher protocol layer of the electronic device. In some example implementations, the MAC layer is an interface between the physical layer and a logical link control (LLC) layer, which provides flow control for packets communicated over a network. According to the OSI (open system interconnection) model, the LLC layer and the MAC layer are considered sub-layers of a data link layer (or layer two). Although reference is made to the MAC layer in some implementations, it is noted that other types of link layers can be used in other implementations.

[0009] In accordance with some embodiments, to further conserve power while an electronic device is in a lower power mode, a link layer residing in an input/output (I/O) controller of an electronic device remains powered off while the electronic device is in the lower power mode. Even with the link layer in the I/O controller powered off, the electronic device remains enabled to respond to a wake message received over a network. The ability to respond to such wake message is provided by using wakeup logic that is implemented as a separate device from the I/O controller— the wakeup logic is able to detect that a network interface controller has received the wake message. Note that conventionally it is the I/O controller that detects that the network interface controller has received the wake message.

[0010] An example electronic device 100 is shown in Fig. 1 , which has a network interface controller 102 connected to a network 104 (wired network or wireless network). The network interface controller 102 can be implemented as a network interface chip, such as a PHY chip or other type of chip. A "PHY chip" refers to an integrated circuit chip that implements physical layer functionality. Alternatively, the network interface controller 102 can be part of another controller in the electronic device that also performs other functions.

[001 1 ] The network interface controller 102 includes a physical layer 106

(represented as "PHY" in Fig. 1 ), which provides the lowest level interface to physical transmission media implementing the network 104, where the physical transmission media can include electrical wires, optical fiber links, or wireless links. The electronic device 100 also includes a wakeup logic 108 that is separate from an input/output (I/O) controller 1 10. In some examples, the wakeup logic 108 can be a discrete logic device separate from the I/O controller 1 10. The I/O controller 1 10 includes a link layer 1 12 (among other components). Note that in implementations as depicted in Fig. 1 , the link layer 1 12 is provided in a part or device {e.g., I/O controller 1 10) that is separate from the network interface controller 102.

[0012] The link layer 1 12 receives a power voltage 1 14, where a "power voltage" refers to a voltage output by a power system of the electronic device 100. The power voltage 1 14 can also be used to power other logic 1 13 in the I/O controller 1 10. During normal operation, the link layer 1 12 in the I/O controller 1 10 cooperates with the physical layer 106 in the network interface controller 102 to perform data communications over the network 104. For example, if the link layer 1 12 is implemented as a MAC layer, then the MAC layer can communicate frames containing MAC addresses over the network 104, where the MAC addresses in each frame are used to switch the frame between network devices.

[0013] The link layer 1 12 and the physical layer 106 are part of a communication stack of protocol layers in the electronic device that operate according to respective protocols to allow the electronic device to communicate over the network 104. For example, another protocol layer in the communication stack can be an Internet Protocol (IP) layer for implementing IP communications over the network 104. Yet another protocol layer in the communication stack is a transport layer, such as a Transmission Control Protocol (TCP) layer or User Datagram Protocol (UDP) layer. [0014] During a lower power mode of the electronic device 100, the power voltage 1 14 to the link layer 1 12 is deactivated, such that the link layer 1 12 (and the other logic 1 13) is powered off. With the link layer 1 12 powered off, conventional electronic devices would not be able to be awakened in response to a wake message received over the network 104. However, in accordance with some implementations, the separate wakeup logic 108 is interposed between the network interface controller 102 and the I/O controller 1 10 to allow the wakeup logic 108 to receive a wake indication 1 16 from the network interface controller 102, in response to the physical layer 106 receiving a wake message over the network 104.

[0015] In response to the wake indication 1 16, the wakeup logic 108 asserts an indication 1 18 to the I/O controller 1 10, where the activated indication 1 18 is to cause the I/O controller 1 10 to perform tasks to awaken the electronic device 100 from the lower power mode. Awakening the electronic device 100 from the lower power mode causes activation of power to components of the electronic device 100 that were powered off in the lower power mode. For example, the power voltage 1 14 can be activated upon the electronic device 100 awakening from the lower power mode, which causes the link layer 1 12 (and the other logic 1 13 connected to the power voltage 1 14) to be powered up.

[0016] By allowing the link layer 1 12 to remain powered off during the lower power mode, additional power savings can be achieved while still enabling waking the electronic device 100 in response to a network wake message. In some implementations, by deactivating the link layer 1 12 and the other logic 1 13 in the I/O controller 1 10 connected to the power voltage 1 14, power consumption of the electronic device 100 during the lower power mode can be reduced below a target power consumption threshold, such as a target threshold set by a government regulatory agency, by a standard, or by some other entity. In some examples, this target power consumption threshold can be 1 .2 watts, although other example power consumption thresholds can be used in other implementations.

[0017] Fig. 2 shows the electronic device 100 according to alternative

implementations. In the arrangement of Fig. 2, the I/O controller 1 10 of the electronic device 100 of Fig. 1 is implemented with a southbridge controller 202. The southbridge controller 202 has a MAC layer 204 (which corresponds to the link layer 1 12 of Fig. 1 ) and a general purpose input/output (GPIO) interface 206. The GPIO interface 206 is configurable (or programmable) to cause the GPIO interface 206 to perform predefined tasks. In accordance with some implementations, one of the predefined tasks of the GPIO interface 206 is to respond to the activated indication 1 18 provided by the wakeup logic 108. The activated indication can be provided to a GPIO input pin that is input to the GPIO interface 206. Although reference is made to the GPIO interface 206 for receiving the activated indication 1 18 from the wakeup logic 108, it is noted that other implementations can include other circuitry in the southbridge controller 202 for responding to the activated indication 1 18 to allow for awakening of the electronic device 100 from a lower power mode in response to a network wake message.

[0018] In accordance with some implementations, the GPIO interface 206 is configured to provide a wake event in response to the activated indication 1 18.

Consequently, upon receipt of the activated indication 1 18 at the GPIO interface 206, the southbridge controller 202 recognizes that a wake event has occurred, and the southbridge controller 202 responds by performing tasks to awaken the electronic device 100.

[0019] As further shown in Fig. 2, a portion of the southbridge controller 202 including the MAC layer 204 is powered by V1 , while the GPIO interface 206 is powered by V2. V1 and V2 are power supply voltages provided by a power system 208 of the electronic device. The power system 208 can receive a battery input (from a battery) and/or an AC adapter input (from an AC adapter). Other power supply voltages can also be produced by the power system 208. Generally, the power system 208 represents the components of the electronic device 100 used to produce and/or deliver power to different parts of the electronic device 100. Such components of the power system 208 can include a power supply, power

regulator(s), power rails, and so forth. V1 , V2 and other power supply voltages can be provided by different ones of the components of the power system 100. [0020] During lower power mode, V1 can be off, while V2 remains on. During normal operating mode, both V1 and V2 are on.

[0021 ] The southbridge controller 202 includes other components 210 that can also be powered off during lower power mode. These other components 210 can be powered by V1 or alternatively, by other power supply voltages from the power system 208 that are off while the electronic device 100 is in a lower power mode. Examples of the other components 210 that can be included in the southbridge controller 202 include a mass storage controller, an interrupt controller, and an interface to a northbridge controller 212. The mass storage controller is used for managing access of mass storage media 214 {e.g., disk-based storage device(s) or integrated circuit storage device(s)). The interrupt controller of the southbridge controller 202 is used to receive and process interrupts from I/O devices. Although certain example components of the southbridge controller 202 are listed above, it is noted that the southbridge controller 202 can include other or alternative

components.

[0022] The northbridge controller 212 has an interface to a processor 214, a memory controller to manage access of memory 216, and other logic. In some examples, instead of being separate components, the northbridge controller 212 can be integrated into the processor 214. During lower power mode of the electronic device 200, the processor 214 and northbridge controller 212 can also be powered off.

[0023] In certain implementations, the northbridge controller 212 can be referred to as a memory controller hub or an integrated memory controller, and the

southbridge controller 202 can be referred to as an I/O controller hub.

[0024] As further depicted in Fig. 2, a sideband bus is provided between the network interface controller 102 and the wakeup logic 108 (Fig. 2 depicts a sideband bus segment 218 between the network interface controller 102 and the wakeup logic 108). In some examples, the sideband bus can be an SMBus (system management bus). In some examples, the sideband bus (including segments 218 and 219) is also connected between the network interface controller and the southbridge controller 202 (through the wakeup logic 108). As depicted in Fig. 2, the sideband bus segment 218 is between the network interface controller 102 and the wakeup logic 108, and the sideband bus segment 219 is between the wakeup logic 108 and the southbridge controller 202. The sideband bus segment 218 allows for provision of the wakeup indication 1 16 (Fig. 1 ) from the network interface controller 102 to the wakeup logic 108. It is noted that in certain implementations, the southbridge controller 202 has an interface to the sideband bus. However, during lower power mode, this interface of the southbridge controller 202 to the sideband bus is powered off, such that this interface to the sideband bus would not be able to properly respond to the wake indication from the network interface controller 102 that is provided over the sideband bus 218. Instead, the wakeup logic 108 is provided to allow for proper awakening of the electronic device 100 in response to a wake message on the network 104 while the MAC layer 204 and the interface to the sideband bus in the southbridge controller 202 remains powered off in the lower power mode. However, during normal operation (when the system is not in a lower power mode), then the sideband bus segments 218 and 219 are connected through buffers in the wakeup logic 108, such that the interface to the sideband bus in the southbridge controller 202 can interact over the sideband bus (218, 219) with the network interface controller 102.

[0025] By interposing the wakeup logic 108 between the network interface controller 102 and the southbridge controller 202, the sideband bus is isolated from the southbridge controller 202 while in the lower power state, in some examples.

[0026] As further depicted in Fig. 2, the network interface controller 102 also includes a magic packet detector 220. Upon receiving a packet over the network 104, the received packet is sent by the physical layer 106 to the magic packet detector 220 to allow the magic packet detector 220 to determine whether the received packet is a magic packet, and if so, whether the magic packet is targeted to the electronic device 100. If the magic packet is targeted to the electronic device 100, the magic packet detector 220 activates the wake indication (1 16 in Fig. 1 ) over the sideband bus 218. [0027] In alternative implementations, instead of providing the magic packet detector 220, an alternative wake message detector can be used in the network interface controller 102 to recognize other types of wake messages.

[0028] Fig. 3 is a flow diagram of a process according to some implementations for awakening the electronic device 100 from a lower power mode in response to a wake message. The physical layer 106 of the network interface controller 102 receives (at 302) a wake message over the network 104. As noted above, the wake message can be a magic packet that is sent by a remote node over the network 104, where the magic packet has predefined payload that is recognizable by the receiving network interface controller 102. In response to the wake message, the network interface controller 102 provides (at 304) a wake indication (1 16 in Fig. 1 ) to the wakeup logic 108, such as over the sideband bus 218 of Fig. 2. In response to the wake indication, the wakeup logic 108 activates (at 306) an indication (1 18 in Fig. 1 ) to the I/O controller 1 10. In response to the activated indication 1 18, the I/O controller 1 10 performs (at 308) tasks to awaken the electronic device 100 from the lower power mode.

[0029] In the foregoing description, numerous details are set forth to provide an understanding of the subject disclosed herein. However, implementations may be practiced without some or all of these details. Other implementations may include modifications and variations from the details discussed above. It is intended that the appended claims cover such modifications and variations.