BACKGROUND

[0001] Universal Serial Bus (USB) such as USB 2.0 is a legacy intellectual property

(IP) where the USB specification keeps evolving for enabling low cost platform integration and to support new features. In the legacy USB 2.0 suspend mode configuration, the USB device weak pull-up impedance (Rpu) has a specification range 900 W to 1575 W, and is terminated to 3.3V (maximum 3.6V) power supply rail. The IO (input-output) pins D+ or D- of the USB device are pulled up to 3.3V for High Speed (HS)/Full Speed (FS) or Low Speed (LS) capable configurations during suspend mode (e.g., where idle supply voltage=VIHZ). The host device coupled to the USB device has a pull-down impedance (Rpd) coupled to IO pins D+ and D- at the host device. These IO pins are required by the USB host specification to be held at 0V when a host port of the host device is not connected with any USB device through the IO pins D+ and D-.

[0002] During suspend mode, Rpu can have a range of 7.2 KW to 8.8 KW and is directly terminated to 5V VBUS (a USB specification supply rail). As such, the idle voltage of VIHZ has a range 3.16V to 4.07V when worst case Rpu and VBUS specification values are considered. To support USB Type-C specification, VBUS may be raised to 5.5V, and that high VBUS causes VIHZ to be as high as 4.26V. Such high VIHZ during suspend mode causes transistor reliability issues at the host device. For example, transistors being fabricated at more advanced process nodes such as 14 nm (nanometer) and beyond may break down at such high VIHZ voltages. Catering to USB legacy devices as well as new USB devices using advanced transistors on the host is challenging from reliability and power consumption perspective.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0005] Fig. 1 illustrates a legacy Universal Serial Bus (USB) 2.0 device in connected or suspend mode configuration with a host device.

[0006] Fig. 2 illustrates an apparatus to reduce idle voltage on D+ and D- pins at a host device which is USB 2.0 compliant, in accordance with some embodiments.

[0007] Fig. 3 illustrates a plot showing overlapping VIHZ voltage range for various

USB 2.0 compliant device operation.

[0008] Fig. 4 illustrates a timing diagram for host and device handshaking sequence, and times when shunt pull-down devices (or legs) are enabled to protect reliability of transistors of the host device, in accordance with some embodiments.

[0009] Fig. 5 illustrates an apparatus to differentiate pull-up configuration of the device to protect devices and lower power consumption at the host, in accordance with some embodiments.

[0010] Fig. 6 illustrates a squelch detector or amplifier used to enable or disable the shunt pull-down devices (or legs), in accordance with some embodiments.

[0011] Fig. 7 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with apparatus to differentiate pull-up configuration of the device to protect devices and lower power consumption at the host, according to some embodiments of the disclosure.

DETAILED DESCRIPTION

[0012] Some embodiments describe an apparatus and method to detect and differentiate Rpu design configuration of a device (e.g., USB 2.0 device) during Host-device connection/handshake event and enable shunt legs when reliability protection is required. However, the embodiments are not limited to USB compliant devices. Other devices operating at high supply voltages that are to be coupled to a host device are also contemplated by the various embodiments. The apparatus of the host device disables the shunt legs when the power supply to the Rup resistors on the device is 3.3V or less, in accordance with some embodiments.

[0013] In some embodiments, the apparatus comprises a signal detector (e.g., a squelch detector or amplifier) including a first input to receive a first data signal (e.g., D+), a second input to receive a second data signal (e.g., D-), a third input to receive a first reference, and a fourth input to receive a second reference. In some embodiments, the apparatus comprises a first multiplexer coupled to the signal detector, wherein the first multiplexer is to selectively provide the first reference from among a first plurality of references. In some embodiments, the apparatus comprises a second multiplexer coupled to the signal detector, wherein the second multiplexer is to selectively provide the second reference from among a second plurality of references. The two references may be differential references that allow the signal detector to detect a small difference between D+ and D- signals. For example, the signal detector can detect as low as 50 mV signal difference. In this example, the two references can be set in a range of 50 mV to 60 mV.

[0014] In some embodiments, the apparatus comprises a latch circuitry to latch an output of the signal detector, wherein the latch circuitry is to provide a latched version of the output. In some embodiments, the apparatus comprises a first device (e.g., an n-type device) to receive the latched version of the output; and a second device (e.g., another n-type device) to receive the latched version of the output. In some embodiments, the apparatus comprises a first series of devices (e.g., a shunt leg) coupled to the first input and the first device; and a second series of devices (e.g., another shunt leg) coupled to the second input and the second device. In various embodiments, to protect the reliability of transistors on the host device, the first and second devices are turned on when the first and second inputs are coupled to a device with a supply voltage greater than approximately 3.3V. In some embodiments, the first and second devices are turned off when the supply voltage less than approximately 4.25V. In various examples here, device is a Universal Serial Bus (USB) compliant device. However, the embodiments are not limited to USB compliant devices. Other devices operating at high power supplies (e.g., 3.3V and greater) are also applicable here. In some embodiments, the first and second series of devices include at least one diode-connected transistor and at least one device to be biased by an analog bias. In some embodiments, when the device is a USB compliant device, first or second controls to control the first and second multiplexers, respectively, are to select a reference between approximately 50 mV to 60 mV as the first or second references when a device is connected to the apparatus and when a reset operation is enabled.

[0015] There are many technical effects of various embodiments. For example, the apparatus and method of various embodiments allows high voltage devices such as USB2.0 to be connected to advanced integrated circuitry (e.g., 14 nm or beyond based integrated circuits). These advanced integrated circuitries at the host can safely use such devices while lowering power consumption (e.g., by at least 5 mW per USB port). As such, circuits fabricated on advanced technology nodes can continue to work with new and legacy devices. Other technical effects will be evident from the various embodiments and figures. [0016] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0017] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0018] The term“device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

[0019] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

[0020] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

[0021] The term“adjacent” here generally refers to a position of a thing being next to

(e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

[0022] The term "circuit" or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0023] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on." [0024] The term“scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term“scaling” generally also refers to downsizing layout and devices within the same technology node. The term“scaling” may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

[0025] The terms“substantially,”“close,”“approximately,”“ near,” and“about,” generally refer to being within +/- 10% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms“substantially equal,”“about equal” and“approximately equal” mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-10% of a predetermined target value.

[0026] Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0027] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0028] The terms“left,”“right,”“front,”“back,”“top,� �“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms“over,” “under,”“front side,”“back side,”“top,”“bottom,”“over,”“under,” and“on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device.

[0029] The term“between” may be employed in the context of the z-axis, x-axis or y- axis of a device. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

[0030] Here, the term“backend” generally refers to a section of a die which is opposite of a“frontend” and where an IC (integrated circuit) package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten-metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term“frontend” generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low-level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten-metal stack die example).

[0031] It is pointed out that those elements of the figures having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0032] Fig. 1 illustrates a system 100 comprising legacy Universal Serial Bus (USB)

2.0 device in connected or suspend mode configuration with a host device. System 100 comprises host device 101 (e.g. a computer device, laptop, smartphone, tablet, etc.), USB Device 102 (e.g., flash driver, camera, printer, etc.), and transmission line 103 (e.g., USB cable). Other components of system 100 are not shown for simplicity purposes. For example, the mechanical interface of the USB (plug and receptacle), transmitter and receivers at the device and host end, etc. are not shown. Switches SW1 and SW2 are used to enable various operation modes such as suspend mode or connection mode. These switches can be implemented as transistors such as pass-gates.

[0033] The devices on host 101 are usually fabricated on advanced process nodes

(e.g., 14 nm and beyond) for newer host devices. Conversely, the devices and power supplies a device 102 and vary over a wide spectrum because some devices are legacy devices operating on higher voltages while other devices are newer devices operating on lower voltages. USB 2.0 is a legacy IP (intellectual property) where the specification keeps evolving since year 2000 for enabling low cost platform integration and new features support. In the legacy USB2.0 suspend mode configuration, weak pull-up (Rpu spec range 900 - 1575ohm) of device 102 is terminated to Vdd_D=3.3V (wherein maximum Vdd_D is 3.6V) supply. The IO pin D+ or D- will get pulled up to 3.3V for High Speed (HS)/Full Speed (FS) or Low Speed (LS) capable device, respectively, during suspend mode (idle voltage=VIHZ). Note: Rpd is required by the USB2.0 host specification to hold the D+/D- to 0V when the host port of device 101 is not connected with any device.

[0034] According to one engineering change order (ECN)-resistor ECN-approved by

USB IF, USB2.0 device vendor can pull up the D+/D- wires during suspend mode by using Rpu of specification range 7.2 Kohm to 8.8 Kohm. These Rpus are directly terminated to Vdd_D of 5V, which is also referred to as VBUS of device 102. One reason for this ECN is to save manufacturing cost for platform voltage regulator (VD). This increase in VBUS and change in Rpu causes VIHZ to be in a range of 3.16V to 4.07V when considering the worst case pull-up Rpu and VBUS minimum and maximum specification. With another 5.5V VBUS ECN to support USB Type-C requirement, the VIHZ may reach as high as 4.26V at worst case condition.

[0035] Table 1 illustrates the VIHZ maximum level in accordance with the ECNs.

The maximum (max) VIHZ may violate reliability limits of transistors in host device 101. For example, transistors manufactured at 14nm FinFET (Fin Field Effect Transistor) process technology may not survive such high VIHZ. Note, current specification range for Rpd is 14.25 KOhm to 24.8 KOhm.

Table 1

[0036] Fig. 2 illustrates apparatus 200 to reduce idle voltage on D+ and D- pins at a host device which is USB 2.0 compliant, in accordance with some embodiments. To safe guard the devices on host 201 that are coupled to D+ and D- lines, in some embodiments, stack of devices 201a and 201b are coupled to D+ and D- lines. These stack of devices are referred to as shunt legs. In some embodiments, the stack of devices are in parallel to the pull-down resistors Rpd. In some embodiments, each stack of devices comprises p-type devices MP1 and MP2, and n-type devices MN1 and MN2. Here, transistors MP1 and MN1 are diode-connected devices (e.g., gate of the transistor is coupled to the drain of the transistor). In some embodiments, transistors MP2 and MN2 are biased to control the current flow though the shunt leg. In some embodiments, transistor MP2 is biased by pbias while transistor MN2 is biased by nbias. These analog bias signals can be generated by any known reference generator.

[0037] In some embodiments, shunt legs 201a and 201b are weak pull-down legs that behave as leakers. In some embodiments, stack of devices 201a and 201b are always-on. For example, stack of devices 201a and 201b are configured to be always powered on through BIOS (built-in operating system) setting. Here, always-on refers to a state of circuitry that has a path from a high voltage potential to ground (e.g., from D+/D- to ground).

[0038] The stack of devices 201a and 201b provide an additional leaker path on top of

Rpd resistor path to ground. As such, VIHZ is reduced during suspend mode to be less than 3.6V, which may be low enough to meet gate transistor reliability limits. Shunt legs 201a and 201b can be further upsized to be stronger when VBUS ECN is applied. VBUS ECN supports higher VBUS range from 5.25V to 5.5V as the maximum limit to meet USB Type-C requirement. VBUS ECN further increases the suspend leakage power consumption as shunt legs 201a and 201b become stronger and sink more current to ground. For example, host device 201 will bum additional leakage when the D+ and D- I/O pads are parked at 3.3V due to the always-on shunt legs 201a and 201b.

[0039] While the embodiment of Fig. 2 provides a solution to protect transistor reliability with USB 2.0 specification before the ECN, after the resistor ECN, and after the VBUS ECN, it may result in leakage power because of the always-on shunt legs. For example, shunt legs 201a and 201b start consuming noticeable power after voltages on D+ and D- are pulled up to greater than 2.5V. These shunt legs 201a and 201b become stronger when the voltages on D+/D- keeps rising. For instance, when the voltage on D+/D- is 3.3V, turning ON the weakest shunt leg would bum up to greater than 300pW across PVT (process, voltage, and temperature). This leakage number may be two to three times higher when the shunt legs are further upsized to meet the VBUS ECN specification requirements.

[0040] While the embodiments here describe the shunt legs 201a and 201b with a particular implementation having diode-connected transistors and other transistors that are biased, the shunt legs are not limited to that implementation. Any suitable implementation that provides a weak resistive path from D+ and D- to ground can be used as shunt legs 201a and 201b.

[0041] Fig. 3 illustrates plot 300 showing an overlapping VIHZ voltage range for various USB 2.0 compliant device operation. Here, arrow 301 illustrates the range of VIHZ when Rpu is coupled to Vdd_D of 3.3V. In this case, minimum VIHZ is 2.7V and maximum VIHZ is 3.47V. Arrow 302 illustrates the range of VIHZ when Rpu is coupled to Vdd_D of VBUS. In this case, minimum VIHZ is 2.92V and maximum VIHZ is 4.25V. Overlapping VIHZ is region 303, which is the region between the two Rpu designs. In some

embodiments, shunt legs 201a and 201b can be turned off during region 303 to reduce suspend power consumption while being turned on outside of the region 303, in accordance with some embodiments.

[0042] Fig. 4 illustrates timing diagram 400 for host and device handshaking sequence, and times when shunt pull-down devices (or legs) are enabled to protect reliability of transistors of the host device, in accordance with some embodiments. Timing diagram 400 shows an example of HS/FS capable device handshaking with a host port. For LS device, the D- pin is pulled up to VIHZ. With USB2.0 protocol, the host port needs to maintain both D+/D- at approx. 0V by weak Rpd when there is no device connected to the port.

[0043] Once a device is connected to the host port and detected and VBUS is ready, the Rpu from the device side pulls up the voltage on either D+ or D- to approximately 3.3V (VIHZ), depending on the device speed capability, to indicate that a device connection event occurred. After a certain period of time, the host controller issues a reset signal by pulling down both D+/D- to ground with a 45 ohm main driver. This is indicated by region 401.

Due to the Rpu being 1.5KW at 3.3V (or 8KW at 5V), a non-zero SE0 (Tiny J) is observed in region 401 where the voltage on D+ is slightly higher than the voltage level at D- during the reset period. With the variations of some parameters, Table 2 shows that the non-zero port reset amplitude (D+ - D- or vice versa) may vary from 75.2mV to 187.7mV with 1.5Kohm of Rpu at Vdd_D 3.3V configuration or 21.5mV to 37.6mV with 8Kohm of Rpu at Vdd_D 5V configuration. The timing diagram shows that by disabling the shunt legs 201a and 201b when Rpu is 1 1.5 KPhms at Vdd_D of 3.3V, and enabling the shunt legs when the device is connected and outside of reset region, suspend power can be saved. In some embodiments, when Rpu is 8 KOhms at Vdd_D of VBUS, shunt legs 201a and 201b can be enabled to protect devices at host 201. Table 2 tabulates port reset amplitude with different device Rpu design configurations.

Table 2

[0044] Fig. 5 illustrates apparatus 500 to differentiate pull-up configuration of the device to protect devices and lower power consumption at the host, in accordance with some embodiments. Here, shunt legs 201a and 201b are replaced with legs 501a and 501b, respectively, which are coupled to n-type MN3 and MN4 devices, respectively. Apparatus 500 further comprises signal detector and amplifier 502, latch 503, inverter 504, and multiplexers 505 and 506. In some embodiments, signal detector and amplifier comprises a squelch amplifier or detector.

[0045] The sensitivity of the signal detector and amplifier 502 depends on the reference voltages Ref-i- and Ref-. In some embodiments, reference voltages Ref-i- and Ref are differential voltages. In some embodiments, during suspend mode or when the voltages on D+ and D- lines are in the VIHZ overlap region 303, the reference voltages Ref-i- and Ref- can be adjusted to cause the signal detector and amplifier 502 to detect the fine difference between D+ and D- voltages indicated in region 401. For example, during the reset operation, discussed with reference to Fig. 4, Ref-i- and Ref- can be set to 50 mV to 60 mV setting to identify the condition in region 401 and to control the shut legs 501a and 501b accordingly. While the embodiments here discuss the signal detector and amplifier 502 as being a squelch detector or amplifier, the embodiments are not limited to such. For example, other amplifiers and/or comparators that are operable to detect a fine difference between D+ and D- as indicated by region 401, can also be used.

[0046] In some embodiments, squelch detector 502 is configured to trip in between

100 mV to 150 mV during normal operation (e.g., when not in suspend mode) and is able to operate at a high speed (e.g., 480 Mbps). By adjusting the reference voltages Ref-i- and Ref-, squelch detector 502 can trip as low as 50 mV and as high as 162.5 mV, for example. The “tiny J” amplitude in region 401 during host reset can be detected using squelch detector 502 to differentiate the device Rpu design configuration by using Ref-i- and Ref- at 50 mV-60 mV. Here,‘J’ refers to toggling of signals on the D+ and D- lines. In some embodiments, multiplexers 504 and 505 provide different reference voltages (Vrefl+/-, Vref2+/-, Vref3+/-, and Vref4+/-) for different operating modes of host 501 and device 102. While four references are shown as selectable references for each multiplexer, any number of references can be used so long as they include references for normal operation of squelch detector 502 and suspend mode operation of device 102. As such, Rup configuration of device 102 can be detected and“tiny J” (in region 401) is identified during host reset. Squelch detector 502 is used to detect the“tiny J” amplitude and decide when shunt enabling or disabling is desired. [0047] In some embodiments, references provided as input to multiplexers 505 and 5-

6 can be generated by a voltage divider such as a resistor ladder. Other means can also be used to generate the references. For example, the references can be generated by a bandgap reference to provide a base reference and then a voltage ladder to generate a plurality of references from the base reference.

[0048] In USB 2.0 protocol, host device 501 and device 102 begin a series of handshake transactions after detecting port reset for a predetermined time (e.g., greater than 2.5pS). The reset duration is long enough for host device 501 to detect the“tiny J” level in region 401 and to differentiate the device 102 Rpu configuration to determine whether to enable shunt legs 501a/b for electric overstress (EOS) and aging protection or to disable shunt legs 501a/b for suspend power saving. Shunt legs 501a/b are disabled when Shunt_enb is at logic 0 while shunt legs 501a/b are enabled when Shynt_enb is logic 1.

[0049] The HS operation that uses the Squelch Detector 502 to operate at 480 Mbps may start after the handshaking process of Fig. 4 is complete, which may take up to a millisecond range. As such, little or no significant performance impact is observed by multiplexing the references for detector 502. After port reset, Squelch detector 502 receives the normal reference voltages and operates in normal mode.

[0050] The output“out” trips as logic“1” when D+ minus D- (or vice versa) amplitude is greater than the differential Vref (“Ref+” -“Rref-”) or else“out” trips as logic “0”. In some embodiments, the Sel+[1:0] and Sel-[1:0] signals can be gated by configuration register bits and a port reset enabling signal. A latch 503 can be added at the output of Squelch Detector 502 to hold the device Rpu detection information after port reset de- asserted.

[0051] Table 3 shows the results of Squelch detector 502 with 50 mV reference voltage setting at two different device Rpu design configuration.

Table 3

[0052] A designer can use the latch output (Shunt_en) signal information to enable/disable shunt legs 501a/b. In some embodiments, shunt legs 501a/b are enabled by default as they consume low power (e.g., shunt legs 501a/b consume power when D+/D- is greater than 2.5 V). In some embodiments, combinational logic can be added to enable shunt legs 501a/b right after power-on and after device 102 is connected and port reset process is asserted. As such, host 501 has zero exposure to reliability risk from D+ and D- signals. In some embodiments, host 501 may hold both D+/D- to approximately 0V by its weak Rpd when device 101 is not connected to host device 501 via transmission line 103. In this case, shunt legs 501a/b may not burning any leakage power at D+/D- = 0V.

[0053] The apparatus of Fig. 5 can save power. For example, up to 3.7 mW is saved at worst case by taking 10 USB ports as reference point as showing in Table 4. In one example, the apparatus of Fig. 5 can save up to 5.2mW on today’s chipset that uses 14 USB2.0 ports.

Table 4

[0054] While the embodiments here describe the shunt legs 501a and 501b with a particular implementation having diode-connected transistors and other transistors that are biased, the shunt legs are not limited to that implementation. Any suitable implementation that provides a weak resistive path from D+ and D- to ground can be used as shunt legs 501a and 501b.

[0055] Fig. 6 illustrates a squelch detector or amplifier 600 (e.g., 502) used to enable or disable the shunt pull-down devices (or legs), in accordance with some embodiments. In some embodiments, sense amplifier latch 600 comprises n-type input transistors MN1 and MN2 to receive input signals on nodes D- and D+. In one embodiment, cross-coupled inverting stages formed from transistors MP2 and MN3 (inverter 1), and transistors MP4 and MN4 (inverter 2) are coupled to input n-type transistors MN1 and MN2 at their respective drain terminals. In some embodiments, p-type transistors MP1 and MP3 are coupled in parallel to MP2 and MP4 to enable or disable transistors MP4 and MP2 respectively on different phases of clock signal Clk. In some embodiments, outputs V0+ (out) and Vo- (out- ) are coupled to the drains of transistors MN3 and MN4 respectively. In some embodiments, sense amplifier latch 600 comprises a switchable current source in transistor MN5 which provides current to sense amplifier latch 600.

[0056] In some embodiments, sense amplifier latch 600 consumes far less power than any traditional amplifier or comparator because the current source MN5 is OFF during the low phase of clock signal Clk. In one such embodiment, outputs V0+ and Vo- are held logically high by transistors MP1 and MP3 which are ON during the low phase of clock signal Clk. The clock signal Clk can be generated by any suitable source (e.g., phase locked loop, sign oscillator, etc.). In some embodiments, sense amplifier latch 600 samples input signals D- and D+ during the high phase of clock signal Clk. In one such embodiment, transistor MN5 is ON and acts like a current source while transistors MP1 and MP3 are OFF.

[0057] In some embodiments, the sense (or sensing) amplifier based latch 600 has two operating phases— one operating phase is reset, and the other operating phase is evaluation. In some embodiments, during the reset operation phase, output differential nodes V0+ and Vo- are shorted to Vdd (or Vss in a complimentary structure). In some

embodiments, the back-to-back coupled inverters (MN3/MP2 and MN4/MP4) are forced to have equal input/output voltages. In some embodiments, during the evaluation operating phase, the differential pair charges the two output nodes V0+ and Vo- at different rates because the current flowing through the differential pair is a function of input signals Vin- and Vin+. In one such embodiment, the back-to-back coupled inverters (MN3/MP2 and MN4/MP4) see a voltage difference at their inputs/outputs and operate in a positive feedback. The positive feedback causes the voltage difference to be magnified. For example, the inputs/outputs of the back-to-back coupled inverters (MN3/MP2 and MN4/MP4) grow quickly to a solid logical‘G or logical Ό’ levels. Hence, a small voltage at the sensing amplifier inputs (D- and D+) are magnified to a logic signal. In some embodiments, a RS (reset-set) flip-flop follows sense amplifier latch 600 stage to form a fully functional unit.

[0058] In some embodiments, when MN5 is turned ON there is a current that passes through both sides of sense amplifier latch 600. If the input voltage to the gate of MN 1 is higher than input voltage to the gate of MN2 then the current through the left side of sense amplifier latch 600 is higher than the right side of sense amplifier latch 600. A higher current on the left side means that the voltage drop across MP2 is larger than the voltage drop across MP4, which means that voltage at V0+ is higher than voltage at Vo-. In this example, the top portion of sense amplifier latch 600 comprises two cross-coupled inverters, where the input of each gate is coupled to the output of the other gate. These two inverters may create a positive feedback that quickly forces V0+ to become Vdd and Vo- to become GND

(ground). Through a similar analysis it can be seen that if the input voltage to the gate of MN2 is higher than the input voltage to the gate of MN1, then V0+ is set to GND and Vo- is set to Vcc (power supply).

[0059] In some embodiments, transistors MN1 and MN2 are of the same size, transistors MN3 and MN4 are of the same size, transistors MP2 and MP4 are of the same size, and transistors MP1 and MP3 are of the same size. In some embodiments, capacitors Cl and C2 are metal capacitors. In some embodiments, capacitors Cl and C2 are transistor based capacitors. In some embodiments, capacitors Cl and C2 are hybrid capacitors (e.g., combination of metal and transistors-based capacitors). In some embodiments, capacitors are fabricated in the frontend of the die. In some embodiments, the capacitors are fabricated in the backend of the die. In some embodiments, resistors R1 and R2 are resistors offered by the process node. In some embodiments, resistors R1 and R2 are transistors operating in the linear region.

[0060] Fig. 7 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with apparatus to differentiate pull-up configuration of the device to protect devices and lower power consumption at the host, according to some embodiments of the disclosure. Fig. 7 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0001] In some embodiments, computing device 1600 includes first processor 1610 with apparatus to differentiate pull-up configuration of the device to protect devices and lower power consumption at the host, according to some embodiments discussed. Other blocks of the computing device 1600 may also include the apparatus to differentiate pull-up configuration of the device to protect devices and lower power consumption at the host, according to some embodiments. In some embodiments, the apparatus can be a separate block that connects with another of the blocks shown in Fig. 7.

[0002] The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0003] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0004] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0005] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0006] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0007] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0008] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0009] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0010] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0011] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0012] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0013] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0014] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0015] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0016] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0017] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0018] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0019] Following examples are provided to illustrate the various embodiments.

These examples can depend from one another in any suitable manner.

[0020] Example 1: An apparatus comprising: a signal detector including a first input to receive a first data signal, a second input to receive a second data signal, a third input to receive a first reference, and a fourth input to receive a second reference; a first multiplexer coupled to the signal detector, wherein the first multiplexer is to selectively provide the first reference from among a first plurality of references; and a second multiplexer coupled to the signal detector, wherein the second multiplexer is to selectively provide the second reference from among a second plurality of references.

[0021] Example 2: The apparatus of example 1 comprising a latch circuitry to latch an output of the signal detector, wherein the latch circuitry is to provide a latched version of the output.

[0022] Example 3: The apparatus of example 2 comprising a first device to receive the latched version of the output; and a second device to receive the latched version of the output.

[0023] Example 4: The apparatus of example 3 comprising a first series of devices coupled to the first input and the first device; and a second series of devices coupled to the second input and the second device.

[0024] Example 5: The apparatus of example 4, wherein the first and second devices comprise first and second n-type transistors, respectively.

[0025] Example 6: The apparatus of example 4, wherein the first and second devices are turned on when the first and second inputs are coupled to a device with a supply voltage greater than approximately 3.3V.

[0026] Example 7: The apparatus of example 6, wherein the first and second devices are turned off when the supply voltage less than approximately 4.25V. [0027] Example 8: The apparatus of example 7, wherein the device is a Universal

Serial Bus (USB) compliant device.

[0028] Example 9: The apparatus of example 4, wherein the first and second series of devices include at least one diode-connected transistor and at least one device to be biased by an analog bias.

[0029] Example 10: The apparatus according to any one of examples 1 to 9, wherein the signal detector comprises a squelch amplifier.

[0030] Example 11 : The apparatus according to any one of examples 1 to 9, wherein the first and second multiplexers are controllable by first and second controls, respectively, and wherein at least one of the first and second controls are to select a reference between approximately 50 mV to 60 mV as the first or second references.

[0031] Example 12: The apparatus of example 11, wherein the first or second controls are to select a reference between approximately 50 mV to 60 mV as the first or second references when a device is connected to the apparatus and when a reset operation is enabled.

[0032] Example 13: An apparatus comprising: a first input terminal coupled to a first terminal impedance; a second input terminal coupled to a second terminal impedance; a squelch amplifier including a first input to receive a first data signal from the first input terminal, a second input to receive a second data signal from the second input terminal, and an output; a first series of devices coupled to the first input terminal and a first device; and; a second series of devices coupled to the second input terminal and a second device, wherein the first and second devices are controlled by the output of the squelch amplifier according to voltage levels of the first and second data signals on the first and second input terminals, respectively.

[0033] Example 14: The apparatus of example 13, wherein the squelch amplifier comprises a third input to receive a first adjustable reference, and a fourth input to receive a second adjustable reference.

[0034] Example 15: The apparatus of example 14 comprising: a first multiplexer coupled to the squelch amplifier, wherein the first multiplexer is to selectively provide the first adjustable reference from among a first plurality of references; and a second multiplexer coupled to the squelch amplifier, wherein the second multiplexer is to selectively provide the second adjustable reference from among a second plurality of references.

[0035] Example 16: The apparatus of example 15, wherein the first and second multiplexers are controllable by first and second controls, respectively, and wherein at least one of the first and second controls are to select a reference between approximately 50 mV to 60 mV as the first or second adjustable references.

[0036] Example 17: The apparatus of example 13, wherein the first or second controls are to select a reference between approximately 50 mV to 60 mV as the first or second adjustable references when a device is connected to the apparatus and when a reset operation is enabled.

[0037] Example 18: The apparatus of example 13 comprising a latch circuitry coupled to the output of the squelch amplifier, wherein the latch circuitry is to provide a latched version of the output of the squelch amplifier to the first and second devices.

[0038] Example 19: A system comprising: a memory; a processor coupled to the memory, wherein the processor includes a Universal Serial Bus compliant circuitry which includes an apparatus according to any one of examples 1 to 12; and an antenna to allow the processor to communicate with another device.

[0039] Example 20: A system comprising: a memory; a processor coupled to the memory, wherein the processor includes a Universal Serial Bus compliant circuitry which includes an apparatus according to any one of examples 13 to 18; and an antenna to allow the processor to communicate with another device.

[0040] Example 21 : An apparatus comprising: a first input terminal coupled to a first terminal impedance; a second input terminal coupled to a second terminal impedance; a squelch amplifier including a first input to receive a first data signal from the first input terminal, a second input to receive a second data signal from the second input terminal, and an output; a first series of devices coupled to the first input terminal and a first device; and; a second series of devices coupled to the second input terminal and a second device, wherein the first and second devices are controlled by the output of the squelch amplifier according to pull-up configuration of a device coupled to the first and second input terminals, respectively.

[0041] Example 22: The apparatus of example 21, wherein the squelch amplifier comprises a third input to receive a first adjustable reference, and a fourth input to receive a second adjustable reference.

[0042] Example 23: The apparatus of example 21 comprising: a first multiplexer coupled to the squelch amplifier, wherein the first multiplexer is to selectively provide the first adjustable reference from among a first plurality of references; and a second multiplexer coupled to the squelch amplifier, wherein the second multiplexer is to selectively provide the second adjustable reference from among a second plurality of references. [0043] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.