[0001] This relates generally to electronic systems, and more particularly to a pulse-shaping amplifier system.

BACKGROUND

[0002] Amplifiers are implemented in a large variety of electronic circuit applications to provide amplified versions of signals. As one example, amplifiers can be implemented to boost voltages in certain communications standards, such as peripheral sensor interface (PSI) standards (e.g., PSI5). In a synchronous configuration of PSI communication, a transceiver can generate a voltage pulse to trigger peripheral sensors, after which the peripheral sensors can transmit data. The voltage pulse can be generated by the transceiver based on an amplifier to shape the voltage pulse to be compliant to certain timing parameters, such that the data transmission is not corrupted, but also to substantially mitigate radio frequency interference (RFI). As a result, the communication from the peripheral sensors can be provided at the speed that may be required by the standard without being potentially corrupted by RFI.

SUMMARY

[0003] In described examples, an amplifier system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The amplifier system also includes an amplifier stage that receives at least one power voltage and is configured to amplify the reference voltage pulse and to provide pulse-shaping of the amplified reference voltage pulse based on a change of amplitude of the at least one power voltage resulting from an amplitude of the reference voltage pulse.

[0004] Another example includes a method for generating a shaped output voltage pulse. The method includes providing an input pulse signal to an input stage to generate a reference voltage pulse based on the input pulse signal. The method also includes providing a first power voltage to an amplifier stage to amplify the reference voltage pulse. The amplifier system includes a first transistor device and a second transistor device interconnected by an output node on which an amplified reference voltage pulse is provided. The method also includes providing a second power voltage to the amplifier stage, the second power voltage having an amplitude that changes in response to a change of resistance associated with a respective one of the first and second transistor devices based on the amplitude of the reference voltage pulse to provide pulse-shaping of the amplified reference voltage pulse on which the shaped output voltage pulse is based.

[0005] Another example includes an amplifier system. The system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The system also includes an amplifier stage. The amplifier stage includes a

Class AB amplifier comprising a first transistor device and a second transistor device being interconnected via an output node on which an amplified reference voltage pulse corresponding to the reference voltage pulse is provided. The first and second transistor devices can be arranged between a first power voltage and a second power voltage, respectively. The second power voltage can have an amplitude that changes in response to a change of resistance associated with the second transistor device based on the amplitude of the reference voltage pulse to provide pulse-shaping of the amplified reference voltage pulse.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 illustrates an example of an amplifier system.

[0007] FIG. 2 illustrates an example of a timing diagram.

[0008] FIG. 3 illustrates an example of a circuit diagram of an amplifier system.

[0009] FIG. 4 illustrates another example of a timing diagram.

[0010] FIG. 5 illustrates an example of a peripheral sensor interface system.

[0011] FIG. 6 illustrates an example of a method for generating a shaped output voltage pulse.

DETAILED DESCRIPTION OF EXAMPLE EMB ODEVIENT S

[0012] This description relates generally to electronic systems, and more particularly to a pulse-shaping amplifier system. The amplifier system can be implemented in a variety of applications to generate a shaped output voltage pulse in response to an input pulse signal. For example, the amplifier system can be implemented in a transceiver in a peripheral sensor interface (PSI) system (e.g., PSI5). The amplifier system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. For example, the input stage can include a pair of switches that are alternately activated via the input pulse signal to charge a capacitor via a reference voltage and to discharge the capacitor to generate the reference voltage pulse. The amplifier system also includes an amplifier stage that can generate an amplified version of the reference voltage pulse, and can provide pulse-shaping of the amplified reference voltage pulse based on an amplitude of the reference voltage pulse. [0013] For example, the amplifier system can include a Class AB amplifier that includes a pair of transistor devices being interconnected via an output node on which the amplified reference voltage pulse corresponding to the reference voltage pulse is provided. As described herein, the term "transistor device" refers to an arrangement of one or more transistors configured to function as a single transistor. The pair of transistor devices can be arranged between a first power voltage and a second power voltage, respectively. For example, the first power voltage can be provided via a charge pump or a boost power converter, and the second power voltage can be provided from a low-dropout (LDO) power supply. The second power voltage can have an amplitude that changes in response to a change of resistance associated with the second transistor device of the pair of transistor devices based on the amplitude of the reference voltage pulse increasing to provide pulse-shaping of the amplified reference voltage pulse. Therefore, the overshoot voltage of the LDO power supply can provide a more gradual increase of the amplified reference voltage pulse for an initial short time duration to substantially mitigate RFI in the generated shaped output voltage pulse.

[0014] FIG. 1 illustrates an example of an amplifier system 10. The amplifier system 10 can be implemented in a variety of different implementations to generate a shaped output voltage pulse, demonstrated in the example of FIG. 1 as VSHP. For example, as described in greater detail herein, the amplifier system 10 can be implemented in a peripheral sensor interface (PSI) system to generate the shaped output voltage pulse VSUP in a manner to comply with timing requirements of a communication standard while substantially mitigate radio frequency interference (RFI).

[0015] The amplifier system 10 includes an input stage 12 that is configured to receive an input pulse signal PLS, such as provided as a low-voltage digital signal to initiate the shaped output voltage pulse VSUP, and to generate a reference voltage pulse VRPLS that can be a low-voltage reference pulse that corresponds to the input pulse signal PLS. For example, the reference voltage pulse VRPLS can be a pulsed voltage signal having a pulse-width that is approximately the same as the pulse signal PLS, and thus can be generated based on the pulse signal PLS. For example, the input stage 12 can include a pair of switches that are alternately activated via the input pulse signal PLS to charge a capacitor via a reference voltage (e.g., based on a current source) and to discharge the capacitor (e.g., based on a current source) to generate the reference voltage pulse VRPLS. [0016] The amplifier system 10 also includes an amplifier stage 14 that is configured to amplify the reference voltage pulse VRPLS to generate an amplified reference voltage pulse VAMP. Also, the amplifier stage 14 is configured to provide pulse-shaping of the amplified reference voltage pulse VAMP. As described herein, the term "pulse-shaping" refers to controlling the slew-rate of the amplified reference voltage pulse VAMP, and thus controlling at least one of an increase and a decrease of the amplitude of the amplified reference voltage pulse VAMP. For example, the pulse-shaping can be provided at an increase in amplitude of the amplified reference voltage pulse VAMP during a first portion of the increase of the amplitude relative to a second portion of the increase of the amplitude. Therefore, the amplifier stage 14 can be configured to provide a first increase in amplitude of the amplified reference voltage pulse VAMP from a first amplitude to a second amplitude during a first time duration, and to provide a second increase in amplitude of the amplified reference voltage pulse VAMP from the second amplitude to a third amplitude during a second time duration subsequent to the first time duration. The second increase in amplitude of the amplified reference voltage pulse VAMP can be greater than the first increase in amplitude to substantially mitigate RFI associated with the generation of the amplified reference voltage pulse VAMP.

[0017] In the example of FIG. 1, the amplifier stage 14 includes a first power voltage VPSH and a second power voltage VPSL. For example, the first power voltage VPSH can be generated via a boost power converter or via a charge pump, and the second power voltage VPSL can be generated via a low-dropout (LDO) power supply. For example, the amplifier stage 14 can include a Class AB amplifier that includes a pair of transistor devices that interconnect the power voltages VPSH and VPSL. Thus, in response to an increase in amplitude of the reference voltage pulse VRPLS, and thus a change in resistance of the pair of transistor devices, the amplitude of the second power voltage VPSL can increase (e.g., overshoot) to decrease the slew-rate of the amplified reference voltage pulse VAMP, and thus to shape the pulse of the amplified reference voltage pulse VAMP. As a result, the amplified reference voltage pulse VAMP can have a lower slew-rate for a brief duration of time before the slew-rate of the amplitude of the amplified reference voltage pulse VAMP increases.

[0018] The amplifier system 10 further includes an output stage 16 that is configured to provide the shaped output voltage pulse VSHP based on the amplified reference voltage pulse VAMP. For example, the output stage 16 includes a back-to-back transistor device pair through which the amplified reference voltage pulse VAMP can be provided. The back-to-back transistor device pair can be controlled, such as by an adaptive gate bias system that is configured to set a bias (e.g., provide a gate voltage) of the back-to-back transistor device pair based on an amplitude of the amplified reference voltage pulse VAMP. Thus, the back-to-back transistor device pair can be configured to provide the shaped output voltage pulse VSHP at a high current amplitude. The output stage 16 is demonstrated in the example of FIG. 1 in the amplifier system 10, but it is optional, such that the amplified reference voltage pulse VAMP could instead be provided directly from the amplifier system 10 as the shaped output voltage pulse VSHP.

[0019] FIG. 2 illustrates an example of a timing diagram 50. The timing diagram 50 demonstrates the shaped output voltage pulse VSHP plotted over time. The shaped output voltage pulse VSHP can be generated via the amplifier system 10 in the example of FIG. 1. Therefore, reference is to be made to the example of FIG. 1 in the following description of the example of FIG. 2. In the context of the timing diagram 50, the shaped output voltage pulse VSHP is demonstrated linearly, but the shaped output voltage pulse VSHP is depicted ideally, such that portions of the actual shaped output voltage pulse VSHP can be non-linear.

[0020] The timing diagram 50 can correspond to the shaped output voltage pulse VSHP, as shaped via the amplifier stage 14. Beginning at a time Tl, the shaped output voltage pulse VSHP can increase from a first amplitude VI to a second amplitude V2 at a time T2. Thus, the time Tl to the time T2 can define a first duration of time. Beginning at the time T2, the shaped output voltage pulse VSHP can increase from the second amplitude V2 to a third amplitude V3 at a time T3. Thus, the time T2 to the time T3 can define a second duration of time subsequent to the first duration of time. For example, the third amplitude V3 can correspond to an amplitude that is sufficient for operation of another circuit, such as peripheral sensors in a PSI communication standard (e.g., PSI5). During the first duration of time, the increase of the amplitude of the shaped output voltage pulse VSHP is less than the increase of the amplitude of the shaped output voltage pulse VSHP during the second duration of time. In the example of FIG. 2, the slew-rate of the shaped output voltage pulse VSHP in the first duration of time is less than the slew-rate of the shaped output voltage pulse VSHP in the second duration of time. Therefore, the shaped output voltage pulse VSHP can be pulse-shaped to substantially mitigate RFI by providing a lesser slew-rate in the first duration of time, while complying with communication timing requirements by providing a greater slew-rate in the second duration of time.

[0021] For example, the time Tl can correspond to a time just subsequent to a rising-edge of the pulse signal PLS, such that the reference voltage pulse VRPLS increases to subsequently increase the amplitude of the amplified reference voltage pulse VAMP. Therefore, beginning at the time Tl, the amplitude of the reference voltage pulse VRPLS can increase to effect a change in the resistance of one of the transistor devices associated with the amplifier stage 14, such that the amplitude of the second power voltage VPSL can provide an overshoot. Thus, the overshoot can cause a decrease in the slew-rate of the amplified reference voltage pulse VAMP during the first time duration. At the time T2, the overshoot can settle (e.g., decrease), thus causing the slew-rate to increase during the second time duration. As a result, the amplified reference voltage pulse VAMP can have a lower slew-rate during the first time duration before the slew-rate of the amplitude of the amplified reference voltage pulse VAMP increases during the second time duration.

[0022] Beginning at a time T4, the shaped output voltage pulse VSHP decreases from the third amplitude V3 to the first amplitude VI at a time T5. For example, the time T4 can correspond to a time just subsequent to a falling-edge of the pulse signal PLS, such that the reference voltage pulse VRPLS decreases to subsequently decrease the amplitude of the amplified reference voltage pulse VAMP. Therefore, beginning at the time T4, the shaped output voltage pulse VSFIP decreases (e.g., based on the discharge of a capacitor in the input stage 12). Therefore, the shaped output voltage pulse VSFIP can have a pulse-width that is approximately the same as the input pulse signal PLS.

[0023] FIG. 3 illustrates an example of a circuit diagram of an amplifier system 100. The amplifier system 100 can correspond to the amplifier system 10 in the example of FIG. 1. Therefore, the amplifier system 100 can be implemented in a variety of different implementations to generate a shaped output voltage pulse, demonstrated in the example of FIG. 3 as VSHP. For example, the amplifier system 100 can be implemented in a peripheral sensor interface (PSI) system to generate the shaped output voltage pulse VSHP in a manner to comply with timing requirements of a communication standard while substantially mitigate radio frequency interference (RFI).

[0024] The amplifier system 100 includes an input stage 102 that is configured to receive an input pulse signal PLS, such as provided as a digital signal to initiate the shaped output voltage pulse VSHP, and to generate a reference voltage pulse VRPLS at a node 104 that corresponds to the input pulse signal PLS. In the example of FIG. 3, the input stage 102 includes a first current source 106 configured to generate a current II and a second current source 108 configured to generate a second current 12. The first current source 106 is arranged between a reference voltage VREF and a first switch SW1 that is coupled to the node 104 to provide the current II to the node 104 in response to the first switch SW1 being closed. Similarly, the second current source 108 is arranged between a second switch SW2 that is coupled to the node 104 and a low voltage rail (e.g., ground) to provide the current 12 from the node 104 in response to the second switch SW2 being closed. In the example of FIG. 3, the first and second switches SW1 and SW2 are alternately activated by the input pulse signal PLS. Also, in the example of FIG. 3, the input stage 102 includes an input capacitor CI that is arranged between the node 104 and the low voltage rail.

[0025] FIG. 4 illustrates another example of a timing diagram 150. The timing diagram 150 demonstrates the input pulse signal PLS, the reference voltage pulse VRPLS, a power supply voltage VLDO, and the shaped output pulse signal VSHP plotted as a function of time. At a time TA (e.g., corresponding to the time Tl in the example of FIG. 2), the input pulse signal PLS transitions from a logic-low state to a logic-high state, and thus has a rising-edge. In response, the first switch SW1 closes and the second switch SW2 opens. As a result, the current II charges the capacitor CI to more slowly increase the amplitude of the reference voltage pulse VRPLS until the reference voltage pulse VRPLS achieves an amplitude of approximately the amplitude of the reference voltage VREF.

[0026] Referring again to the example of FIG. 3, the amplifier system 100 also includes an amplifier stage 110. The amplifier stage 110 includes a high voltage amplifier 112, which includes a power supply voltage VPS and is referenced to the low voltage rail (e.g., ground). The amplifier stage 110 also includes an N-type field effect transistor (FET) device Nl and a P-type FET device PI (hereinafter, "FETs"). The N-FET Nl and the P-FET PI are arranged as a Class AB amplifier between the power supply voltage VPS, via a diode Dl, and a power supply voltage VLDO. For example, the power supply voltage VPS can be provided via a boost power converter or via a charge pump, and the second power voltage VLDO can be generated via an LDO power supply. The Class AB amplifier arrangement of the N-FET Nl and the P-FET PI is configured to generate and pulse-shape an amplified reference voltage pulse VAMP at a node 114 based on the reference pulse voltage VRPLS. For example, the high voltage amplifier 112 is configured to generate a first control voltage VC1 and a second control voltage VC2 that are level-shifted relative to each other based on the reference voltage pulse VRPLS, thus operating the N-FET Nl and the P-FET PI in a push-pull manner to generate the amplified reference voltage pulse VAMP.

[0027] As described herein, the power voltage VLDO can provide an overshoot (e.g., an approximate 200 mV increase, such as from 500 mV to 700 mV). As the amplitude of the reference voltage pulse VRPLS begins to increase, the P-FET PI is still more strongly activated relative to the N-FET Nl . Therefore, the amplified reference voltage pulse VAMP increases from a first amplitude (e.g., the amplitude VI in the example of FIG. 2) to a second amplitude (e.g., the amplitude V2) with the slope of the VLDO overshoot during the first time duration between the times Tl and T2 in the example of FIG. 2 (e.g., approximately 3 μ8). Thus, the inclusion of the overshoot of the power voltage VLDO with the amplified reference voltage pulse VAMP ensures a slower ramp rate to mitigate RFI without sacrificing timing. As the slew-rate of the amplified reference voltage pulse VAMP continues to increase, the N-FET Nl activates more strongly than P-FET PI, and the amplitude of the amplified reference voltage pulse VAMP increases (e.g., the amplitude V2 in the example of FIG. 2) to a third amplitude (e.g., the amplitude V3 in the example of FIG. 2, which can be approximately 4 V greater than the amplitude VI) during a second time duration (e.g., from the time T2 to the time T3 in the example of FIG. 2

[0028] The amplifier system 100 further includes an output stage 116 that is configured to provide the shaped output voltage pulse VSUP based on the amplified reference voltage pulse VAMP. In the example of FIG. 3, the output stage 116 includes an adaptive gate bias system 118, demonstrated as "AGB" 118. The adaptive gate bias system 118 is arranged across the N-FET Nl to adaptively generate a voltage VAGB based on the amplitude of the amplified reference voltage pulse VAMP. The output stage 116 also includes an N-FET N2 and an N-FET N3 arranged as a back-to-back transistor device pair through which the amplified reference voltage pulse VAMP is provided as the shaped output voltage pulse VSUP. In the example of FIG. 3, the N-FETs N2 and N3 are controlled by the voltage VAGB. Thus, the back-to-back transistor device pair of the N-FETs N2 and N3 can provide the shaped output voltage pulse VSHP at a high current amplitude.

[0029] Referring again to the example of the timing diagram 150 of the example of FIG. 4, in response to the increase in amplitude of the reference voltage pulse VRPLS, the shaped output voltage pulse VSHP begins to increase at a time just subsequent to the time Tl . Also, the resistance (RDS ON) of the P-FET PI changes in response to the increase in the control voltage VC2 results in a brief overshoot of the power supply voltage VLDO at the time just subsequent to the time Tl . As a result, the slew-rate of the amplitude of the amplified reference voltage pulse VAMP decreases momentarily, demonstrated in an exploded view 152 during a brief time duration indicated at 154 corresponding to the time of the overshoot of the power supply voltage VLDO. After the overshoot of the power supply voltage VLDO settles (e.g., within approximately 3 μβ), the slew-rate of the amplitude of the amplified reference voltage pulse VAMP increases, demonstrated at 156 in the exploded view 152. Accordingly, the amplitude of the shaped output voltage pulse VSFIP levels-off (e.g., at an amplitude that is approximately 4 V greater than the voltage VI in the example of FIG. 2) at a time just subsequent to the time of level-off of the reference voltage pulse VRPLS, until a time TB (e.g., corresponding to the time T4 in the example of FIG. 2).

[0030] At the time TB, the input pulse signal PLS transitions from the logic-high state to the logic-low state, and thus has a falling-edge. In response, the first switch SW1 opens and the second switch SW2 closes. As a result, the current 12 discharges the capacitor CI to slowly decrease the amplitude of the reference voltage pulse VRPLS until the reference voltage pulse VRPLS achieves an amplitude of approximately the voltage VI, which could be approximately zero volts. As a result, at a time just subsequent to the time TB the shaped output voltage pulse VSHP likewise decreases (e.g., to the amplitude of the power supply voltage VLDO).

[0031] Accordingly, the lower slew-rate of the amplified reference voltage pulse VAMP, and thus the shaped output voltage pulse VSHP, during the first time duration at 154 (e.g., during the overshoot) can result in substantially mitigated RFI. Also, the more rapid slew-rate of the amplified reference voltage pulse VAMP, and thus the shaped output voltage pulse VSHP, during the second time duration at 156 (e.g., after the overshoot) can maintain a more rapid increase (e.g., within approximately 3 μβ) of the amplified reference voltage pulse VAMP, and thus the shaped output voltage pulse VSHP, to comply with communication standards (e.g., PSI5). Also, the topology of the amplifier system 100, as described herein, can be configured to be scalable for any amplitude of the shaped output voltage pulse VSHP based on any delay and/or rise and fall times of the input pulse signal PLS. Furthermore, implementing the overshoot of the power supply voltage VLDO generated via an LDO power supply can allow for an external capacitance of the LDO power supply that is on the order of hundreds of nF, instead of in the tens of μ¥, which can reduce the physical space of the electronics on an associated board.

[0032] FIG. 5 illustrates an example of a peripheral sensor interface system 200. The peripheral sensor interface system 200 can correspond to any of a variety of systems for controlling peripheral sensors 202, such as in an automotive system. In the example of FIG. 5, the peripheral sensor interface system 200 includes a plurality N of sensors 202, where N is a positive integer, that may be configured to transmit data in response to a shaped voltage pulse VECU in a time-division multiplexed sequence.

[0033] The peripheral sensor interface system 200 also includes a transceiver 204 that is configured to generate the shaped output voltage pulse VECU in response to a synchronization signal SYNC. For example, the synchronization signal SYNC can be provided as a pulsed signal, similar to the input pulse signal PLS in the examples of FIGS. 1, 3, and 4. In the example of FIG. 5, the transceiver 204 includes an amplifier system 206, and the transceiver 204 is configured to receive a first power supply voltage VPS from a power supply 208 and a second power supply voltage VLDO from an LDO power supply 210. Each of the power supply 208 and the LDO power supply 210 are configured to receive a battery voltage VBAT, such as from an automobile battery. The amplifier system 206 can be configured substantially similarly to the amplifier system 10 in the example of FIG. 1 or the amplifier system 100 in the example of FIG. 3.

[0034] For example, the amplifier system 206 can include an input stage that is configured to receive the synchronization signal SYNC to initiate the shaped output voltage pulse VECU. The amplifier system 206 can also include an amplifier stage that is configured to amplify a reference voltage pulse that is generated based on the synchronization signal SYNC to generate an amplified reference voltage pulse. Also, the amplifier stage of the amplifier system 206 can be configured to provide pulse-shaping of the amplified reference voltage pulse to generate the shaped output voltage pulse VECU. Therefore, the amplifier stage can be configured to provide a first increase in amplitude of the shaped output voltage pulse VECU from a first amplitude to a second amplitude during a first time duration, and to provide a second increase in amplitude of the shaped output voltage pulse VECU from the second amplitude to a third amplitude during a second time duration subsequent to the first time duration. Accordingly, the shaped output voltage pulse VECU can be generated in a manner that allows the peripheral sensors 202 to operate in a time-division multiplexed manner, and thus to adhere to a communication standard (e.g., PSI5), while substantially mitigating RFI associated with the generation of the shaped output voltage pulse VECU, and thus substantially mitigating corruption of the data transmitted by the peripheral sensors 202.

[0035] In view of the structural and functional features described hereinabove, a method in accordance with various aspects of example embodiments is described with reference to FIG. 6. For simplicity, the method of FIG. 6 is shown and described as executing serially, but example embodiments are not limited to the illustrated order, as some aspects could (in accordance with example embodiments) occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, some illustrated features may be optional to implement a method in accordance with an aspect of example embodiments.

[0036] FIG. 6 illustrates an example of a method 250 for generating a shaped output voltage pulse (e.g., the shaped output voltage pulse VSUP). At 252, an input pulse signal (e.g., the input pulse signal PLS) is provided to an input stage (e.g., the input stage 12) to generate a reference voltage pulse (e.g., the reference voltage pulse VRPLS) based on the input pulse signal. At 254, a first power voltage (e.g., the power voltage VPSH) is provided to an amplifier stage (e.g., the amplifier stage 14) to amplify the reference voltage pulse. The amplifier system can include a first transistor device (e.g., the N-FET Nl) and a second transistor device (e.g., the P-FET PI) interconnected by an output node (e.g., the node 114) on which an amplified reference voltage pulse (e.g., the amplified reference voltage pulse VAMP) is provided. At 256, a second power voltage (e.g., the power voltage VPSL) is provided to the amplifier stage. The second power voltage can have an amplitude that changes in response to a change of resistance associated with a respective one of the first and second transistor devices based on an increase in the amplitude of the reference voltage pulse to provide pulse-shaping of the amplified reference voltage pulse on which the shaped output voltage pulse is based.

[0037] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.