Title:
PULSE WIDTH MODULATION RECEIVER CIRCUITRY
Document Type and Number:
WIPO Patent Application WO/2014/051739
Kind Code:
A3
Abstract:
Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.
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Inventors:
YANG WEI-LIEN (US)
Application Number:
PCT/US2013/045512
Publication Date:
September 18, 2014
Filing Date:
June 12, 2013
Export Citation:
Assignee:
INTEL CORP (US)
International Classes:
H03K19/0175; H04L25/02
Foreign References:
| US20080025431A1 | 2008-01-31 | |||
| US6218869B1 | 2001-04-17 | |||
| US20090257541A1 | 2009-10-15 | |||
| US20080159444A1 | 2008-07-03 | |||
| US8068559B1 | 2011-11-29 |
Attorney, Agent or Firm:
MALLIE, Michael, J. et al. (1279 Oakmead ParkwaySunnyvale, CA, US)
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