BACKGROUND OF THE INVENTION

1. Field of the Invention

[0001] The present invention relates to pulse-width modulation (PWM) schemes based on space vector modulation (SVM) for three-phase rectifier converters.

2. Description of the Related Art

[0002] When reduction of size and weight of a converter is desired, the electrical isolation should be performed at high-frequency. Typically, single-stage power conversion can be realized with a direct matrix-type power factor correction (PFC) rectifier that directly converts the mains-frequency AC voltage into a high-frequency AC voltage which is supplied to a high- frequency isolation transformer and whose secondary voltage is then rectified to the desired DC output voltage.

[0003] Fig. 1 shows a three-phase, single-stage, isolated, high-frequency, PWM matrix rectifier. The circuit shown in Fig. 1 can be used either with known PWM schemes discussed in this section or with the novel PWM schemes according to the preferred embodiments of the present invention discussed in the Detailed Description of Preferred Embodiments section below.

[0004] Fig. 1 shows an isolated matrix rectifier. In the description of Fig. 1, "line side," "grid side," and "primary side" refer to the portion of the circuit on the left-hand side of the transformer 7 ^" _r that is connected to the line voltages v _a , Vb, v _c for each of the phases A, B, C, and "load side" and "secondary side" refer to the portion of the circuit on the right-hand side of the transformer 7 ^" _r that is connected to the output voltage V ₀ , i.e., the load. On the line side, the three-phase AC current is combined into a single-phase AC current, and on the load side, the single-phase AC current is rectified by diodes to D ₄ to provide a DC current.

[0005] The isolated matrix rectifier of Fig. 1 includes a filter inductor /. and a filter capacitor Cf that define a line-side filter that reduces the total harmonic distortion (THD), bi-directional switches Si to S ₆ arranged in a bridge as a 3-phase-to-l-phase matrix converter, a transformer 7,· that provides high-voltage isolation between the line-side circuit and the load-side circuit, four diodes to D ₄ arranged in a bridge to provide output rectification, an output inductor L ₀ and an output capacitor C ₀ that define a filter for the output voltage.

[0006] Bi-directional switches are used in this isolated matrix rectifier to open or close the current path in either direction. As shown in Fig. 1, the bi-directional switch includes two metal- oxide-semiconductor field-effect transistors (MOSFETs) connected in series. Because of the antiparallel diode of the MOSFETs, the MOSFET can only turn off the current in one direction. With two MOSFETs connected source-to-source or drain-to-drain, bi-directional switching can be achieved. If insulated gate bipolar transistors (IGBTs) are used, the two IGBTs can be connected in parallel or series to define the bi-directional switch.

[0007] A known three-phase, single-stage, isolated high-frequency PWM rectifier as shown in Fig. 1 is disclosed in Vlatkovic et al., "A Zero-Voltage Switched, Three-phase Isolated PWM Buck Rectifier," I EEE Trans. Power Electron., Vol. 10, No. 2, March 1995, pp. 148-157. The PWM rectifier shown in Fig. 1 is capable of power factor correction (unity power factor), low harmonic current distortion, and realizing zero-voltage switching (ZVS) for all power

semiconductor devices. The capacitors C ₂ i and C in Fig. 1 are parasitic capacitors that can be used in ZVS. The known converter of Vlatkovic et al. uses two full-bridge phase-shifted (FB-PS) converter sub-topologies, phases A and B define "converter x" (which can also be referred to as bridge x) and phases A and C define "converter y" (which can also be referred to as bridge y). Converters x and y operate alternatively within the switching cycle. Each converter has a series inductor that reduces the effective duty ratio and extended commutation time, resulting in larger current ripple and larger output inductor. The aforementioned duty cycle loss limits the converter operation at higher switching frequency, which results in decreased conversion efficiency and power density. When a large leakage inductance is required for extending ZVS at light load, the known PWM scheme of Vlatkovic et al. produces a larger THD compared to the PWM scheme of the preferred embodiments of the present invention.

SUMMARY OF THE INVENTION

[0008] To overcome the problems described above, preferred embodiments of the present invention provide PWM schemes in which duty losses are significantly reduced (which prevents the reduction of the effective duty cycle), efficiency is improved during light load, the peak output inductor current ripple is significantly reduced, and the total THD in the line-side current is significantly reduced.

[0009] A preferred embodiment of the present invention provides a method of operating a matrix rectifier. The matrix rectifier includes input phases A, B, and C, each of the input phases A, B, and C includes two bi-directional switches connected in series; a transformer connected to the input phases A, B, and C; a rectifier bridge connected to the transformer; a bridge x defined by phases A and B; and a bridge y defined by phases A and C. The method of operating the matrix converter includes operating the bridges x a nd y as independent full-bridge phase- shifted converters in each 60° interval between two successive zero-voltage crossings of the input phases A, B, and C. I n a first 30° sector of each 60° interval, the bridges x and y are operated in a first vector sequence in every switching period where each vector represents a switch state of the bi-directional switches; and the first vector sequence is divided into a sequence of / _x+; / _y+; / ₀ , / _x -, / _y - I a, where / _x+ and / _x - represent switching states of vector / _x for bridge x when i _P > 0 and i _P < 0, respectively, and where / _y+ and / _y - represent switching states of vector /y for bridge y when i _P > 0 and i _P < 0, respectively.

[0010] A dwell time for each vector in the first vector sequence preferably is TJ2, T _y /2, To/2, T 2, Ty/2, and TQ/2, respectively, where T _x , T _y , and T ₀ are dwell times for / _x , / _y , and / ₀ , respectively. Preferably, in a second 30° sector of each 60° interval, the bridges x and y are operated in a second vector sequence in every switching period, and the second vector sequence is divided into a sequence of / _y+; I _K+i / ₀ , / _y - / _x - /o- A dwell time for each vector in the second vector sequence preferably is T _y /2, T l, T ₀ /2, T _y /2, T 2, and T ₀ /2, respectively. Unity power factor and output-voltage regulation preferably are simultaneously achieved.

[0011] A preferred embodiment of the present invention provides a matrix rectifier including input phases A, B, and C, each of the input phases A, B, and C includes two bidirectional switches connected in series; a transformer connected to the input phases A, B, and C; a rectifier bridge connected to the transformer; a bridge x defined by the phases A and B; a bridge y defined by the phases A and C; and a controller that operates the bridges x and y as independent full-bridge phase-shifted converters in each 60° interval between two successive zero-voltage crossings of the input phases A, B, and C. In a first 30° sector of each 60° interval, the controller operates the bridges x and y in a first vector sequence in every switching period where each vector represents a switch state of the bi-directional switches, and the first vector sequence is divided into a sequence of I _K+i / _y+; I _0i / _x -, / _y - la, where / _x+ and / _x - represent switching states of vector / _x for the bridge x when i _P > 0 and i _P < 0, respectively, and where / _y+ and / _y - represent switching states of vector / _y for the bridge y when i _P > 0 and i _P < 0, respectively.

[0012] A dwell time for each vector in the first vector sequence preferably is TJ2, T _y /2, To/2, T 2, Ty/2, and TQ/2, respectively, where T _x , T _y , and T ₀ are dwell times for / _x , / _y , and / ₀ , respectively. Preferably, in a second 30° sector of each 60° interval, the controller operates the bridges x and y in a second vector sequence in every switching period, and the second vector sequence is divided into a sequence of / _y+; I _K+i I ₀ , / _y - / _x - /o- The dwell time for each vector in the second vector sequence is Ty/2, T /2, Τ ₀ /2, T _y /2, T /2, and T ₀ /2, respectively. Unity power factor and output-voltage regulation preferably are simultaneously achieved.

[0013] The above and other features, elements, characteristics, steps, and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Fig. 1 shows an isolated matrix rectifier.

[0015] Figs. 2A and 2B show current space vector representations.

[0016] Fig. 2C shows the envelope of the transformer primary voltage.

[0017] Fig. 3 shows the synthesis of reference current / _re f by I _lt I ₂ , and, / ₀ .

[0018] Figs. 4A and 4B show various circuit waveforms.

[0019] Figs. 5A and 5B show a comparison of duty cycle losses.

[0020] Figs. 6A and 6B show envelopes of the output-inductor current ripple.

[0021] Figs. 7A and 7B are close up views of the maximum current ripple of the current envelope of Figs. 6A and 6B. [0022] Figs. 8A and 8B show simulations of a PWM scheme of a preferred embodiment of the present invention and a known PWM scheme.

[0023] Fig. 8C shows simulated line-side phase voltage and current of the matrix rectifier of Fig. 1.

[0024] Figs. 9A and 9B show inductor output current and transformer primary voltage.

[0025] Fig. 10 shows the total harmonic distortion at 15% load.

[0026] Fig. 11 shows PWM waveforms of the matrix rectifier of Fig. 1.

[0027] Fig. 12 shows bridges x and y of the matrix rectifier of Fig. 1.

[0028] Figs. 13-21 show different operational modes of the matrix rectifier of Fig. 1.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0029] The methods of the preferred embodiments of the present invention can be used with the matrix rectifier shown in Fig. 1. Within any 60° interval, the matrix rectifier can be considered, as shown in Fig. 12, as two full-bridge phase-shifted (FB-PS) converter sub- topologies, in which phases (sometimes referred to as legs) A and B define "bridge x" and phases A and C define "bridge y," which operate alternatively within one switching cycle.

Bridges x and y act as two independent FB-PS converters. During one switching cycle of the three-phase matrix rectifier, there are two sub-switching cycles for each bridge x and y, respectively, and each bridge x or y completes one operating cycle in the same manner as a FB- PS converter. Therefore, steady-state operation and ZVS analysis of the three-phase converter is done in the same way as the FB-PS converter.

[0030] By rearranging the operating sequence of bridges x and y, a different PWM scheme can be generated. This different PWM scheme according to the preferred embodiments of the present invention combines the operation of bridge x and bridge y to resemble the operation of one FB-PS converter. During one switching cycle of the three-phase matrix rectifier, bridges x and y work together to complete one operating cycle in a similar way as a FB-PS converter. The operation of the basic soft-switching FB-PS converter is known. Therefore, only the operation modes during the switch transitions in the three-phase matrix rectifier will be described. The SVM technique and PWM scheme can be used to simultaneously achieve unity power factor and output-voltage regulation. 1) Principle of operation

[0031] Within any 60° interval between two successive zero crossings of the three-phase voltage input, there are two line voltages that do not change sign, i.e., do not change from positive to negative and do not change from negative to positive. For example, in Fig. 11, in the interval of -30° < Θ < 30°, the line voltages v _AB = v _A — v _B and v _AC = v _A — v _c are positive, and the line voltage V _A B, V _A C both attain their maximum in this interval. Because the switching frequency of the matrix rectifier is much higher than the line frequency, the two line voltages AB, V _ac can be considered as slowly varying DC voltages. Therefore, the three-phase matrix rectifier can be redrawn as one full-bridge converter with two bridges, bridge x and bridge y, as shown in Fig. 12. I n Fig. 1, the combination of phases A and B define bridge x, and the combination of phases A and C define bridge y. Fig. 11 shows the principal waveforms within the interval -30° < Θ < 30°. With an excessively increased switching period in which the switching frequency is reduced to a very low value, the details of the PWM can be observed as shown in Fig. 11.

[0032] I n sector 1(a), in which -30° < Θ < 0° and v _AB > v _AC , the switches S ₁₁ S ₂ i S ₁₆ , S ₂ 6 of bridge x are turned on with an on-time T _x , creating a positive voltage pulse v _P = v _AB and a current pulse flowing from phase A into phase B with magnitude of l _P . Then switches S _U S ₂₁ and S ₁₂ , S ₂₂ of bridge y turn on with an on-time T _y , creating a positive voltage pulse v _P = v _AC and a current pulse flowing from phase A into phase C with magnitude of l _P .

[0033] To keep the transformer flux balanced, a negative voltage pulse of the same duration is generated next by turning on switches S ₁₄ S ₂₄ and S ₁₃ S ₂₃ of bridge x and switches S ₁₄ S ₂₄ and S ₁₅ S ₂₅ of bridge y. The line-side current remains the same regardless of the alternating transformer current. In sector 1(b), in which Θ satisfies 0° < ϋ≤ 30° and v _AC > v _AB , the sequence to turn on bridges x and y is reversed to achieve ZVS operation of the switches S ₁₄ , $24, 5 _ΐ 3, ¾, S ₁₅ , and S ₂₅ , as discussed below.

[0034] Assuming that the matrix rectifier's output current is constant during one switching cycle, the relationship between the primary current i _P (t) and the output-inductor current i _L (t) is given by: [0035] The phase currents can be synthesized by current pulses of constant magnitude. If the input phase currents are given by

the duty cycles— and—, of the input current pulses generated by bridges x and y, respectively, within the chosen 60° interval are

(3)

where l _m is the peak of the fundamental-frequency component in i _a and m _a =— is the

ip

modulation index.

2) Switching States and Space Vectors of PWM Scheme

[0036] The matrix rectifier in Fig. 1 is equivalent to a traditional current-source rectifier (CSR), except that all the switches are bidirectional. An SVM technique and PWM scheme can be used to simultaneously achieve unity power factor at the input and output-voltage regulation.

[0037] As explained in U.S. Application No. 62/069,815, "SPACE VECTOR MODULATION FOR MATRIX CONVERTER AND CURRENT SOURCE CONVERTER," filed on October 28, 2014, the entire contents of which are hereby incorporated herein by reference, and in PCT Application No. PCT/US2015/057887, "SPACE VECTOR MODULATION FOR MATRIX CONVERTER AND CURRENT SOURCE CONVERTER," filed on October 28, 2015, the entire contents of which are hereby incorporated herein by reference, the SVM technique is based on the representation of the required instantaneous input current vector in the complex plane /(t) = / _m (t)e- ^/wt . The input current space vector of the converter is defined as: [0038] As shown in the Figs. 2A and 2B, the active switching states can be represented by active vectors /i to / ₆ , and zero switching states can be represented by zero space

vectors / ₇ , / ₈ , and / ₉ .

[0039] For each active vector, there are two possible switching states depending on the direction of the primary current i _P as shown in Figs. 2A and 2B.

[0040] Based on different switching states, the six active vectors can be obtained by equation (2):

where n = 1, 2, 6 for sectors I, II, ..., VI, respectively.

[0041] The reference vector l _re f rotates in space at an angular velocity that is the same as the grid voltage vector to obtain a sinusoidal input current shape. Unity power factor can be achieved by aligning the reference vector / _re /with the grid voltage vector. The reference vector / _re / can be approximated by two adjacent active vectors / _x , / _y and a zero vector / ₀ as shown in Fig. 3. /χ is generated by bridge x, and / _y is generated by bridge y. For example, when the reference vector / _re /is in sector I as shown in Fig. 3, it can be synthesized by / _x = /i, / _y = / ₂ and

Dwell Time Calculation

[0042] Below, the analysis is done in sector I which includes the vectors /i and / ₂ . If the output-inductor current l _L \s assumed to be constant, the ampere-second balancing equation is given by:

where T _lt T ₂ , and T ₀ are the dwell times for the vectors I _lt / ₂ , and / ₀ , respectively. The dwell time for I _lt I ₂ , and / ₀ can be calculated usin the following equations:

T ₀ = T _S - T _X - T _y

where m _a is the modulation index, given by the following equation: (8)

0 < m _a < 1

where l _m is the peak of the fundamental-frequency component in phase A current / ^' „.

4) SVM Switching Sequence

[0043] To use the transformer isolation, the primary voltage v _P of transformer T _r in Fig. 1 must alternate with a high frequency between positive and negative to maintain volt-sec balance. The vector sequence in every switching period can be divided into the sequence of I _K+i /y ₊ , Ιο, Ιχ- y-, lo, where / _x+ and / _x - represent the switching states of vector / _x when i _P > 0 and i _P < 0, respectively, and / _y+ and / _y - represent switching states of vector / _y when i _P > 0 and i _P < 0, respectively. Then the dwell time for each vector will be TJ2, T _v /2, To/2, T 2, T _v /2, and To/2, respectively. As shown in Figs. 2A and 2B, the two space-vector representations are different when the primary current i _P changes direction. During each switching period T _s , the switching states are selected alternatively from these two space vector diagrams to generate alternating primary voltage v _P and to maintain the same phase current as the line side.

[0044] Each sector is divided into two sections a and b. For Θ E j— oj, the reference vector / _re f is located in sector 1(a), and for Θ E [o,^], the reference vector / _re f is located in sector 1(b). The vector sequence discussed above is for sector 1(a) only. In sector 1(b), the sequence of two active vectors is reversed to achieve ZVS during the transition from one active vector to another active vector. Then, the vector sequence in sector 1(b) becomes / _y+; I _K+i / ₀ , / _y -, / _x - /o with the dwell time of each vector T _y /2, T _x /2, T ₀ /2, T _y /2, T _x /2, and T ₀ /2, respectively.

5) Steady-State Operation

[0045] The analysis below is based on the assumptions that the forward voltage drop across the diodes and the MOSFETs is zero, that the rectifier diode capacitances are zero, and that the output voltage Vo is constant.

[0046] The complete operation of the three-phase converter during one switching period T _s is illustrated in Figs. 4A and 4B. The circuit waveforms shown in Figs. 4A and 4B include the primary voltage v _P the primary current / , the rectified secondary voltage V _d , the output- inductor current i _L , and the corresponding switch gate signals in sectors 1(a) and 1(b). I n sector 1(a) for Θ E [— oj, the voltage v _AB is greater than the voltage v _AC , and in sector 1(b) for

Θ E [0' ~ ] _/ the voltage v _AC is greater than the voltage v _AB . As shown in Figs. 4A and 4B, the duty loss (during the interval AD) caused by the leakage inductance can be observed when the primary current i _P change directions. The duty loss can cause distortion on the line-side current because the effective dwell time will be less than the calculated value.

[0047] The transition time from the zero vectors to the active vectors is finite depending on the value of the leakage inductance /.¾ as shown in Fig. 5A and 5B during the interval AD. During this interval, the primary current i _P changes from one direction to another direction, and there is no energy transfer from the line side to the load side. Therefore, the effective duty cycle which is the duty cycle of the transformer secondary-side rectifier voltage Vd is less than the duty cycle of the primary voltage v _P .

[0048] I n sector I as shown in Fig. 11, the voltage v _A is always higher than voltages v _B and v _c . Switches S ₁₄ and S ₂₁ can be kept on all the time because the body diodes of switches S ₁₄ and S ₂₁ are forward biased. During the interval -30° < Θ < 0°, the voltage v _B is the lower than the voltages v _A and v _c , the body diodes of switches S ₁₃ and S ₂₆ of bridge x are forward biased, and the switches S ₁₃ and S ₂₆ can be kept on during the entire interval as shown in Fig. 4A.

Constraints need to be applied to switches S ₁₅ and S ₂₂ of bridge y to prevent short circuit between the line voltages v _B and v I n the left leg of bridges x and y as shown in Fig. 12, switch S ₁₅ of bridge y should be complimentary to switch S ₂₃ of bridge x to prevent short circuit between the line voltages v _B and v _c because the switch S ₂₅ is forward biased because the voltage vc is higher than the voltage v _B . For the same reason, in the right leg of both bridges x and y, switch S ₂₂ of bridge y should be complimentary to switch S ₁₆ of bridge x because switch S ₁₂ is forward biased.

[0049] During the interval 0° < Θ < 30°, voltage v _c is lower than the voltages v _A and v _B , the body diodes of switches S ₁₅ and S ₂₂ of bridge y are forward biased, and the switches S ₁₅ and S ₂₂ can be kept on during the entire interval as shown in Fig. 4B. Constraints need to be applied to switches S ₁₃ and S ₂₆ of bridge x for the same reason as constraints need to be applied to switches S ₁₅ and S ₂₂ in the interval -30° < Θ < 0° discussed above. Switch S ₁₃ of bridge x should be complimentary to switch S ₂₅ of bridge y, and switch S ₂₆ of bridge x should be complimentary to switch S ₁₂ of bridge y to prevent short circuit between the line voltages v _B and v _c . The six switches S ₂ i, S ₁₄ S ₁₃ S ₂ 6, S ₁₅ S ₂₂ discussed above function as synchronous rectifiers to bypass their body diodes because they are forward biased. The remaining six switches S _U S ₂₄ S ₂₃ S ₁₆ S ₂ 5, S ₁₂ operate in a similar manner as FB-PS converter to achieve ZVS.

[0050] If the average phase currents (/ ^' „, ¾, i _c ) are sinusoidal and in phase with the phase voltages, the input phase voltages are given by

[0051] At steady state, the output voltage V ₀ is the function of three phase input voltage (v _a ,v _b ,v _c ) and modulation index m _a . According to the principle of voltage-second balance,

V ₀ T _S = n [(v _a - v _b )T _x + (v _a - v _c )T _y ] (10) [0052] By substituting equations (7) and (9) into equation (10), provides:

V ₀ = nm _a V _m . (11)

[0053] During the interval AD of the duty loss, the primary current i _P is increasing in a linear fashion from negative to positive or decreasing in a linear fashion from positive to negative. The total changes l _dx is determined by the load current l ₀ . It is assumed that the output current ripple is small compared to the load current l ₀ , which is a realistic assumption at full load when the loss of duty cycle is at its most.

/, dx 2nL (12) where l ₀ is load current and n is transformer ratio. The total duty loss can be derived from the following equation :

*°-. ⁼ SfS ⁽¹³ » where v _P (Q) is the voltage across the leakage inductance /.¾ during interval AD of duty loss. The voltage v _P (Q) is one of the three line-to-line voltages that has the highest magnitude depending on the angle Θ as shown in Fig. 2C.

[0054] The maximum duty loss is obtained when v _P (Q) is a minimum at Θ = 0 so that: ^^totaljnax ^~ _3(/ , ^ _s (14) where V _m is the peak value of line-side phase voltage. Substituting equation (11) into equation (14), the maximum total duty loss is given by the following equation:

_ 4m _a n ² L _lk

total max ^~ _RTs ^■ > \->—>l where R =— is the load resistance.

Io

[0055] The duty cycle loss can be reduced by using a smaller value of the leakage inductance /. _¾ , but at the price of a reduced load range to achieve ZVS. In the PWM scheme of the preferred embodiments of the present invention, the zero voltage transition happens twice in every cycle. Compared with the known PWM scheme of Vlatkovic et al., the duty cycle loss in the preferred embodiments is only approximately half of the duty loss of Vlatkovic et al.

because the zero voltage transitions happened four times in Vlatkovic et al. In other words, if both designs have the same duty cycle loss, the PWM scheme of the preferred embodiments of the present invention achieve ZVS with a wider load range because of the larger value of the leakage inductance /. _¾ . The PWM scheme of U.S. Application No. 62/069,815 and PCT

Application No. PCT/US2015/057887 is suitable for unidirectional switches such as IGBTs. The anti-parallel diode of the IGBT is not by-passed when the IGBT is conducting current because the current can only flow in one direction. The PWM scheme of Vlatkovic is suitable for bidirectional switches such as MOSFETs. The anti-parallel diode of the MOSFET is by-passed when the MOSFET is conducting current.

[0056] To minimize the effect of the duty cycle loss on the line-side current THD, the duty cycle of the primary switches can be compensated to maintain the effective duty cycle being consistent with the calculated dwell time (equation (3)) for I _lt / ₂ , and / ₀ . As shown in Fig. 5A, the duty cycle loss happens during the dwell time of the vector / _x . Therefore, the actual dwell time for the switching state associated with the vector / _x can be recalculated as:

T _X = T ₁ = m _a T _s sin ( - ø) + T _s AD _total (16) 6) Output-inductor current ripple

[0057] At steady state, the output-inductor current ripple varies with the phase angle Θ as shown in Figs. 6A and 6B. At Θ =— - or Θ = - , the current ripple of the PWM scheme of the

6 6

preferred embodiments reaches a maximum and can be derived from the following equation:

[0058] At Θ = 0, the current ripple is a minimum and can be derived from the following equation:

A (18)

[0059] As shown in Figs. 6A and 6B, the maximum envelope of the current ripple (i.e., at Θ =— - and 0 = -) in the PWM scheme of the preferred embodiments is lower than that of

6 6

the known PWM scheme of Vlatkovic et al., while the minimum envelope of the current ripple (i.e., at Θ = 0) in the PWM scheme of the preferred embodiments is higher than that of the known PWM of Vlatkovic et al. For the PWM of Vlatkovic et al., the dwell time of / ₀ is evenly divided and inserted between / _x and / _y as shown Fig. 5B. At Θ = 0, the two pulses for vector / _y disappear, and the remaining two pulses are not evenly distributed, resulting in a larger current ripple as shown in Fig. 7B. By properly adjusting the dwell time of / ₀ between / _x and / _y , it is possible to improve the current ripple of the known PWM scheme of Vlatkovic et al.

7) ZVS Operation Analysis

[0060] The ZVS operation of the switches in Fig. 1 is analyzed with reference to SVM. The analysis is for sector 1(a), and the same analysis can be applied to sector 1(b) and the other five sectors. In sector I (a), the active vectors involved in the ZVS operation are I _x+ = /i and I _y+ = I ₂ .

[0061] Fig. 13 shows mode 0 with freewheeling primary current i _P during time t ₀ ^~ = 0. As shown in Fig. 13, in mode 0, the primary current i _P is freewheeling or circulating through switches S _n , S21, S _i4 and S ₂ 4. Mode 0 corresponds to time t in Fig. 21. The primary voltage v _P , which includes the voltage Vi and the voltage across the leak inductance /. _¾ , is clamped to zero. Because there is no current flowing through the three phases A, B, C, the current vector is / ₀ in mode 0.

[0062] Fig. 14 shows mode 1 with vector transition from I ₀ to Ii (I _x+ ) during time t = [to, ti]. Mode 1 starts when switch S ₂₄ is turned off as shown in Fig. 13. Then energy stored in the leakage inductance L _tk starts transferring to the output capacitance of switches S ₂₄ , S ₁₆ , S ₁₂ and S ₂₂ because of the resonance between them. The primary current i _P also starts resonating down to zero. At time t _lt when the voltage across the switch S ₁₆ reaches zero, the diode D ₁₆ starts conducting as shown in Fig. 16. To achieve ZVS of switch S ₁₆ , the energy stored in leak inductance /./^ charges the total equivalent capacitance of capacitors C ₂₄ , C ₁₆ , C ₂₂ , and C ₁₂ . The parasitic capacitance of transformer Tr is also considered as part of the total equivalent capacitance. This resonance can be analyzed using the simplified circuit shown in Fig. 15.

Because the input voltages between the phases A, B, C are constant during this resonant process, the phases A, B, C can be considered as short circuited. I n the simplified circuit of Fig. 15, capacitors C ₁₂ and C ₂₂ are in series and in parallel with capacitors C ₂₄ and C ₁₆ . The equivalent capacitance C _eq can be calculated by:

where C ₀ is the output capacitance of each switch and C _T R is the parasitic capacitance of the transformer Tr. The calculation of the equivalent capacitance is based on the assumption that the output capacitance C _EQ is constant at different voltages to simplify the analysis. More complex models can be used to derive a more accurate equivalent capacitance. The energy stored in the leakage inductance /.¾ charges the output capacitance C _EQ from 0 V to voltage v _AB . During mode 1, the primary voltage i^is clamped to zero because the primary current \ _P with respect to the load side is smaller than output-inductor current i _b and the current difference between the primary current i _P and the output-inductor current i _L freewheels through the bridge rectifier that includes diodes Dl, D2, D3, D4. Because the energy in the capacitance C _eq is proportional to the square of the input line voltage, the worst case for achieving ZVS will occur when the voltage v _AB is at its highest value, the energy E _c needed to charge the capacitance C _EQ at the peak of the voltage v _AB is

E _c = - ₂ (V3V _m ) ² C ₍ eq (20) [0063] Therefore, the minimum energy stored in the leakage inductance /. _¾ should be equal to energy E _c . This analysis is exactly the same as for a FS-PS converter. At the end of mode 1, the voltage across the leakage inductance /. _¾ is the voltage v _AB . The voltages across switches

S ₂ 4, S _1& S ₂₂ , and S ₁₂ are v _AB , 0, ^ v _AB , and _AC ^~ v _AB ), respectively.

[0064] Fig. 16 shows mode 2 with linear current ramping during t = [ti, t ₃ ]. During mode 2, the voltage v _AB appears across the leakage inductance /. _¾ because the primary voltage still clamped to zero and because the current difference between the reflected current of the primary current i _P and the output-inductor current i _L freewheels through the bridge rectifier. As a result, the primary current i _P ramps up linearly from negative to positive. At time t = t ₂ , before the primary current i _P crosses zero, the switch S ₁₆ is turned on at zero voltage. Mode 2 ends when the primary current i _P reaches the output-inductor current i _L and, as a result, the line voltage v _AB appears across the primary side of the transformer Tr and the vector transition from Io to /i is completed.

[0065] Fig. 17 shows mode 3 with energy transfer from the primary side to the secondary side with the current vector (I _x+ ) during time t = [t ₃ , t ₅ ]. During mode 3, energy is transferred from the primary side to the secondary side as the line voltage v _AB appears across the primary side of the transformer Tr. Because AC current enters into phase A and returns through phase B, the current vector is I _\ . The switch S ₁₂ is turned on at time t ₄ to prepare the vector transition from /i to / ₂ in mode 4. Because the voltage across switch S ₁₂ is not zero when it is turned on, turn-on losses occur. The turn-on losses depend on the switching voltage. As calculated in

1 3

mode 1, the voltage across switch S ₁₂ is (v _AC — v _AB ) and varies from 0 to - V _m during one 30° interval. Because switch S ₁₂ is operated without ZVS only during one 30° interval and because the switching voltage is low, the resulting switching losses are very low. Mode 3 ends when switch S ₁₆ is turned off at time t ₅ .

[0066] Fig. 18 shows mode 4 with the current-vector transition from Ii (I _x+ ) to I ₂ (I _y+ ) during t = [ts, t ₆ ]. The body diode of switch S ₂₂ is initially off with reversed voltage of (v _c — v _B ) before the current-vector transition. At time t ₅ , switch S ₁₆ is turned off, and primary current i _P begins to charge/discharge capacitors C ₂₄ , C _J6 and C ₂ 2. Then the total equivalent capacitance C _eq is the sum of the three capacitors C ₂₄ , C _J6 and C ₂₂ and the parasitic capacitance C _T R of the transformer Tr, as shown by:

C _eq = 3C ₀ + C _TR (21) where C ₀ is the output capacitance of each switch.

[0067] At time t ₆ , the voltage across capacitor C ₂₂ is discharged to zero, and, as shown in Fig. 19, diode D ₂₂ starts conducting. At the end of mode 4, the vector transition from / i to / ₂ is completed, and the line voltage v _AC appears across the primary side of the transformer Tr. During the current-vector transition, the leakage inductance /.¾ is in series with the reflected output-filter inductor L ₀ , which is the equivalent inductance as seen from the primary side and the capacitors C ₂₄ , C^ and C ₂₂ are charged/discharged by the combined energy stored in both the leakage inductance L _tk and output-filter inductor L ₀ which is significantly larger than the energy required to charged/discharge the capacitors C ₂₄ , C _J6 and C ₂₂ . Therefore, ZVS can be easily achieved. To achieve ZVS in this current-vector transition, the phase voltage v _c should be higher than the phase voltage v _B , which is satisfied in sector 1(a) only. In sector 1(b), phase the voltage v _B is higher than the phase voltage v _c . To achieve ZVS in sector 1(b), the switch sequence of the two active vectors is reversed.

[0068] Fig. 19 shows mode 5 with energy transfer from the primary side to the secondary side using current vector I ₂ (I _y+ ) during t = [t ₆ , t ₈ ] . During Mode 5, energy is transferred from the primary side to secondary side as line voltage v _AC appears across the primary side of the transformer Tr. Because AC current enters through phase A and returns through phase C, the current vector is / ₂ . Switch S ₂₂ is turned on at zero voltage at time t ₇ . Mode 5 ends when switch S ₁₂ is turned off.

[0069] Fig. 20 shows mode 6 with the current-vector transition from I ₂ (I _y+ ) to I ₀ during time t = [t& t ₉ ] . After switch S ₁₂ is turned off, the primary current i _P starts charging capacitors C ₁₂ and C ₁₆ and discharging capacitor C ₂₄ . At time t _g , the voltage across capacitor C ₂₄ reduces to zero and the diode D ₂₄ starts conducting as shown in Fig. 21. At the end of mode 6, the current- vector transition from / ₂ to / ₀ is completed, and the primary voltage v _P is clamped to zero. The total equivalent capacitance C _eq to be charged to achieve ZVS is same as that in Mode 4, and the combined energy stored in both /.¾ and L ₀ is used to charge/discharge capacitance. The ZVS can be easily achieved.

[0070] Fig. 21 shows mode 7 with the current vector being I ₀ and with freewheeling primary current during time t = [t ₉ , tn]. During mode 7, the primary voltage v _P is clamped to zero. The primary current i _P freewheels through switches S _llt S ₂ i, S ₁₆ and diode D ₂ 4 (or switch S24). Switch S ₂ 4 can be turned on at zero voltage after diode D ₂₄ starts conducting. Because there is no current flowing through the three phases A, B, C, the current vector is / ₀ . The mode 7 ends when switch S _n is turned off, which completes half the operation cycle. The second half of the operation cycle is similar to the first half.

[0071] I n summary, in Mode 1, bridge x is operating, and ZVS operation is similar to the leading leg operation of a FB-PS converter in which the energy stored in leakage inductance L _tk is used to achieve ZVS. I n Mode 6, bridge y is operating, and ZVS operation is similar to lagging leg operation of a FB-PS converter in which the total energy stored in leakage inductance /.¾ and the output-filter induct L ₀ is used to achieve ZVS. The current-vector transition described in mode 4 involves both bridges x and y, which does not exist in conventional FB-PS converters. However, ZVS of this transition is similar to that of mode 6 in which the total energy stored in leakage inductance /.¾ and the output-filter inductor L ₀ is used to achieve ZVS.

8) Simulations

[0072] Figs. 8A and 8B are simulations comparing the PWM scheme of the preferred embodiments of the present invention with the known PWM scheme of Vlatkovic et al. The simulation model is setup at a rated power of 10 kW and m _a = 0.8 under the following conditions:

(1) V _ab , _rms = 208 V,

(2) fundamental frequency f _m = 60 Hz,

(3) output voltage V ₀ = 400 V,

(4) input line inductor L _f = 30 μΗ,

(5) comm utation capacitor Cf = 5 μΡ,

(6) output inductor L ₀ = 450 μΗ ,

(7) load resistance R ₀ = 16 Ω, (8) turns ratio n = 2,

(9) leakage inductance L _!k = 3.5 μΗ,

(10) switching frequency f _S w = 100 kHz.

[0073] Figs. 8A and 8B show a set of simulated waveforms for the three-phase matrix rectifier of Fig. 1, where v _P , v _s , Vd are the primary side, the secondary side, and the output rectifier voltages; / , i _L are the primary and output-inductor currents; and i _a , ib, are the average (fundamental) phase currents of phase current i _A , i _B , i _c , respectively. Fig. 8C shows simulated line-side phase voltage and current.

[0074] When a large leakage inductance is required for extending ZVS at light load, the known PWM scheme of Vlatkovic et al. produces a larger THD compared to the PWM scheme of the preferred embodiments of the present invention. Based on the simulated waveforms in Fig. 8A, with the PWM scheme of the preferred embodiments, the inductor current ripple Ai _L (around Θ «— - in Fig. 3) is reduced by 26% compared to the known PWM scheme of

6

Vlatkovic et al. Based on the simulation results, the THD of the PWM scheme of the present preferred embodiment of the present invention is about 3.8%, for example. The simulation results are verified by the experimental results in Figs. 9A and 9B that show the transformer primary voltage Vi and inductor output current at Θ = 0 and at 0 < 0 < - or 0 > Θ >— . Fig.

6 6

10 shows the THD is less than about 3% at about 15% load, for example.

[0075] The line-current THD is within about 5%, and a unity power factor is achieved with the PWM scheme according to the preferred embodiments of the present invention. However, a small current distortion in the current waveform is observed. As shown in Fig. 8C, there is a sudden jump in current waveform (Δί _α = 4 A). This current distortion is due to:

(1) Duty loss caused by the leakage inductance /.¾ that reduces the effective duty cycle. As shown in Fig. 8A, waveforms of phase currents i _A and _e are not perfect square waves because the slope of the edge is determined by the leakage inductance /.¾. If a large leakage inductance is required to extend ZVS at light load, then the THD of line current might exceed the standard THD required by industry. (2) The output inductor current ripple introduces errors in the dwell time calculation, which is based on the assumption that inductor current is constant in one switching cycle.

(3) The switching sequence is reversed in the transition from sector 1(a) to sector 1(b) in each sector, which causes a small sudden jump in current between the two phases. As shown in Fig. 11, the gap between two adjacent current pulses in phase currents i _B and \ _c is suddenly changes due to the sequence change between sectors 1(a) and 1(b).

[0076] The SVM technique and PWM scheme of the preferred embodiments of the present invention are preferably implemented using a controller. In the preferred embodiments of the present invention, to calculate the dwell times of the PWM scheme, the controller measures transformer primary current i _p (or inductor current i _L ), line voltages u _a , u^, u _c , and output voltage u ₀ . The controller can be any suitable controller, including, for example, a PI controller, a PID controller, etc. The controller can be implemented in an IC device or a microprocessor that is programmed to provide the functions discussed above. Any suitable controller can be used.

[0077] It should be understood that the foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.