QUADRATURE HYBRID WITH MULTI-LAYER STRUCTURE

TECHNICAL FIELD

The disclosure relates to microwave circuit, and more particularly, to a quadrature hybrid with a multi-layer structure.

BACKGROUND

Recently, electronic devices are evolving towards miniaturization, lower cost and higher performance. In order to meet this requirement, passive components, which occupy the largest area in circuit design, need to be improved. In the traditional Surface Mounted Technology (SMT), most of passive components used in electronic devices, such as capacitors and inductors, are discrete components that take up a large real estate of a Printed Circuit Board (PCB).

Meanwhile, their performances and reliabilities are not good due to large parasitic inductances caused by long interconnections between components and solder joints.

The System-On-Package (SOP) concept where components are integrated as part of a package housing an electronic device is an attractive option to build wireless communication modules. This concept provides a potential for higher integration, leading to a more compact module size that is critical for portable applications. In addition, SOP components have reduced cost since they eliminate the need for discrete components and have shortened assembly time. Also, their performances are superior to those of on-chip components.

Recent progresses in commercial communications have created a need for RF components having more compact sizes. Lumped elements can provide circuit miniaturization at low frequency while having spurious-free responses at high frequency. Therefore, it is of particular interest to implement quadrature hybrids with lumped elements. The Low Temperature Co-fired Ceramic (LTCC) technique is a technique for integrating passive components. However, for SOP applications, the LTCC technique has two major disadvantages: it has a high fabrication cost and it is incapable of dealing with high density interconnections. On the other hand, the low cost organic substrate technique has been well developed, whereby high-density interconnections are possible. Further, in the past decade, embedded passive technique has been proposed and become an attractive IP130297

technology with benefits of lower parasitic parameter, better performance, compactness and higher reliability. The embedded passive technique based on organic substrate has been widely studied because of its advanced

characteristics. It provides a cost-effective alternative to discrete passive

components and LTCC devices.

Quadrature hybrid, also known as branch-line coupler, is an elemental component in various microwave circuits, such as balanced amplifiers, balanced mixers, phase shifters and beam-forming networks for array antennas. Conventional distributed-element quadrature hybrids, such as branch-line or Lange couplers, typically occupy large areas in Microwave Integrated Circuits (MICs) and it's impossible to implement a conventional quadrature hybrid with a planar structure having limited circuit area, especially at low frequency. Semi-lumped and lumped element quadrature hybrids are constructed from lumped π or T network and/or lumped distributed networks equivalent to a transmission line section with an appropriate characteristic impedance and electrical length.

J.Yamasaki, I. Ohta, T. Kawai and Y. Kokubo, "Design of broadband semi-lumped and lumped element quadrature hybrids," 2005 IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, pp. 1247-1250, Jun., 2005 discloses semi-lumped and lumped element quadrature hybrids. However, in this solution, lumped elements (e.g.

capacitors and inductors) are located on the surface of a PCB, which is not desirable for size reduction. In addition, semi-lumped elements (e.g., microstrip lines) also occupy a large area, especially at low frequency. Moreover,

performances of the lumped elements on the PCB surface are vulnerable to environmental conditions, such as temperature, humidity and electromagnetic interferences.

J. Hou and Y. Wang, "A compact quadrature hybrid based on high-pass and low-pass lumped elements," IEEE Microw. Wireless Compon. Lett, vol. 17, no.8, pp. 595-597, Aug., 2007 discloses a compact quadrature hybrid. However, it cannot be used at low frequency (e.g., lower than 200MHz) due to limited capacitance and inductance. The performances of its components are also vulnerable to environmental conditions (e.g., temperature, humidity). IP130297

Y.J. Lee and J. Y. Park, "Fully embedded lumped LC-quadrature hybrid coupler into organic packaging substrate for power sampling," Microw. Optical Technology Letters, vol. 51 , no.3, pp. 845-848, Mar., 2009 discloses a lumped LC-quadrature hybrid. However, it cannot be used at low frequency (e.g., lower than 200MHz) either due to limited capacitance and inductance. Moreover, the Q value of its planar inductor is very low, which results in a high insertion loss of passive components.

Therefore, there is a need for an improved quadrature hybrid capable of overcoming at least some of the above problems in the prior art.

SUMMARY

It is an object of the disclosure to provide a quadrature hybrid that has a reduced size, high capacitance, inductance and Q values and is less vulnerable to environmental conditions.

According to the disclosure, a quadrature hybrid is provided. The quadrature hybrid has a first, second, third and fourth ports and comprises: a substrate having a plurality of dielectric layers; a first, second, third and fourth capacitors, each capacitor having a first predetermined number of layers each being arranged on one of the plurality of dielectric layers; and a first, second, third and fourth inductors, each inductor having a second predetermined number of layers each being arranged on one of the plurality of dielectric layers. The first, second, third and fourth inductors are placed at four corners of a rectangular region on the substrate, respectively. A first terminal lead of the first inductor, a second terminal lead of the fourth inductor and a first terminal lead of the first capacitor are connected to the first port of the quadrature hybrid. A first terminal lead of the second inductor, a second terminal lead of the first inductor and a first terminal lead of the second capacitor are connected to the second port of the quadrature hybrid. A first terminal lead of the third inductor, a second terminal lead of the second inductor and a first terminal lead of the third capacitor are connected to the third port of the quadrature hybrid. A first terminal lead of the fourth inductor, a second terminal lead of the third inductor and a first terminal lead of the fourth capacitor are connected to the fourth port of the quadrature hybrid. A second terminal lead of each of the first, second, third and fourth capacitors is connected to a common ground. IP130297

In an embodiment, the first and second terminal leads of each inductor are arranged in orthogonal directions. In an embodiment, the first and second terminal leads of each of the first and third capacitors are arranged in a first direction and the first and second terminal leads of each of the second and fourth capacitors are arranged in a second direction orthogonal to the first direction. In an embodiment, projections of the first, second, third and fourth capacitors on a surface of the substrate are squares having a same size. The first and second terminal leads of each capacitor extend from a pair of opposite sides of the square on which the capacitor is projected, respectively. In an embodiment, projections of the first and third inductors on a surface of the substrate are squares each having a first size. The first and second terminal leads of each of the first and third inductors extend from neighboring sides of the square on which it is projected, respectively. Projections of the second and fourth inductors on the surface of the substrate are squares each having a second size. The first and second terminal leads of each of the second and fourth inductors extend from neighboring sides of the square on which the inductor is projected, respectively.

In an embodiment, each capacitor is a vertically-interdigital-capacitor.

In an embodiment, each inductor is a spiral inductor.

In an embodiment, each layer of the substrate is made of Low Temperature Co-fired Ceramic (LTCC) material.

With the embodiments of the disclosure, each capacitor or inductor in the quadrature hybrid has a multi-layer structure, which allows the quadrature hybrid to have a reduced size when compared with the traditional quadrature hybrid having planar capacitors and inductors or microstrip lines. The multi-layered capacitors and inductors also provide higher capacitance, inductance and Q values. In addition, since the capacitors and inductors are buried into the IP130297

multi-layered substrate, the performance of the quadrature hybrid is less vulnerable to environmental conditions, such as temperature, humidity and electromagnetic interferences. BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages will be more apparent from the following description of embodiments with reference to the figures, in which:

Fig. 1 shows an equivalent circuit of a quadrature hybrid and its circuit simulation;

Fig. 2 shows odd-mode and even-mode equivalent half circuits of the quadrature hybrid shown in Fig. 1 ;

Fig. 3 is a top view of a quadrature hybrid according to an

embodiment of the disclosure;

Fig. 4 is a top view of the multi-layered capacitor used in the

quadrature hybrid shown in Fig. 3;

Fig. 5 is a three dimensional view of the multi-layered capacitor shown in Fig. 4;

Fig. 6 is a top view of the multi-layered inductor used in the

quadrature hybrid shown in Fig. 3;

Fig. 7 is a three dimensional view of the multi-layered inductor

shown in Fig. 6;

Fig. 8 shows electromagnetic simulation results of the multi-layered capacitor shown in Figs. 4 and 5;

Fig. 9 shows electromagnetic simulation results of the multi-layered inductor shown in Figs. 6 and 7; and

Fig. 10 shows electromagnetic simulation results of the quadrature hybrid shown in Fig. 3. DETAILED DESCRIPTION

The embodiments of the disclosure will be detailed below with reference to the drawings. It should be noted that the following embodiments are illustrative only, rather than limiting the scope of the disclosure. Fig. 1 (a) shows an equivalent circuit of a quadrature hybrid to be used in the disclosure. As shown in the left graph of Fig. 1 (a), the quadrature hybrid has four IP130297

ports (P=1 , 2, 3 and 4) and includes four capacitors (CAP) and four inductors (IND). Each of the capacitors has a capacitance of C. Two of the inductors each have an inductance of L1 and the other two of the inductors each have an inductance of L2. In an example, L1 =52 nH, L2=38 nH and C=68 pf, such that the response of the quadrature hybrid meets the requirement for working at 130 MHz.

Fig. 1 (b) shows the simulation results (S-parameters) of the circuit shown in Fig. 1 (a). In this simulation, it is assumed that Port 1 is the input port and, accordingly, Port 2, Port 3 and Port 4 are the direct, coupled and isolated ports, respectively. It can be seen from Fig. 1 (b) that, at the working frequency of 130 MHz, the

S-parameters S(2, 1 ) between Port 2 and Port 1 and S(3, 1 ) between Port 3 and Port 1 are approximately -3dB; and the S-parameters S(1 , 1 ) (i.e., input port reflection coefficient) and S(4, 1 ) between Port 4 and Port 1 are both lower than -40dB. It can be appreciated by those skilled in the art that each of Port 2, Port 3 and Port 4 can alternatively serve as the input port and the roles of the other ports can vary accordingly.

The equivalent circuit of the quadrature hybrid is symmetric and the odd-even analysis is applicable. Fig. 2 shows odd-mode (a) and even-mode (b) equivalent half circuits of the quadrature hybrid shown in Fig. 1 . Each of the odd and even mode half circuits consists of a ττ-network. The cascaded connections of the half circuits can be analyzed using a known transmission matrix method. The values of L1 , L2 and C can be derived according to the following formulas:

l = -¾- (1 )

2π/

C =—^— (3)

2πβ ₀

where / denotes the working frequency of the quadrature hybrid and Z ₀ denotes the port characteristic impedance (i.e., 50Ω).

Fig. 3 is a top view of a quadrature hybrid 300 according to an embodiment of the disclosure. The quadrature hybrid 300 corresponds to the equivalent circuit shown in Fig. 1 (a). IP130297

As shown in Fig. 3, the quadrature hybrid 300 has a first port 301 , a second port 302, a third port 303 and a fourth port 304. The quadrature hybrid 300 includes a substrate 310 having a plurality of dielectric layers (not shown in Fig. 3 and will be described later). The quadrature hybrid 300 further includes a first capacitor 311 , a second capacitor 312, a third capacitor 313 and a fourth capacitor 314. Each of the capacitors has a number of layers each being arranged on one of the plurality of dielectric layers (not shown in Fig. 3 and will be described later). The

quadrature hybrid 300 further includes a first inductor 321 , a second inductor 322, a third inductor 323 and a fourth inductor 324. Each of the inductors has a number of layers each being arranged on one of the plurality of dielectric layers (not shown in Fig. 3 and will be described later).

The first, second, third and fourth inductors 321 -324 are placed at four corners of a rectangular region on the substrate 310, respectively. In this way, the magnetic cancelling effect among these inductors can be reduced.

A first terminal lead of the first inductor 321 , a second terminal lead of the fourth inductor 324 and a first terminal lead of the first capacitor 311 is connected to the first port 301 of the quadrature hybrid 300.

A first terminal lead of the second inductor 322, a second terminal lead of the first inductor 321 and a first terminal lead of the second capacitor 312 is connected to the second port 302 of the quadrature hybrid 300. A first terminal lead of the third inductor 323, a second terminal lead of the second inductor 322 and a first terminal lead of the third capacitor 313 are connected to the third port 303 of the quadrature hybrid 300.

A first terminal lead of the fourth inductor 324, a second terminal lead of the third inductor 323 and a first terminal lead of the fourth capacitor 314 are connected to the fourth port 304 of the quadrature hybrid 300.

A second terminal lead of each of the first, second, third and fourth capacitors 311 -314 is connected to a common ground 305, such that the effect of

electromagnetic interference can be reduced. IP130297

In an embodiment, as shown in Fig. 3, the first and second terminal leads of each of the inductors 321 -324 are arranged in orthogonal directions. In this way, the size of the entire quadrature hybrid can be further reduced. In an embodiment, as shown in Fig. 3, the first and second terminal leads of each of the first and third capacitors 311 and 313 are arranged in a first direction and the first and second terminal leads of each of the second and fourth capacitors 312 and 314 are arranged in a second direction orthogonal to the first direction. Such orthogonal and symmetric arrangement of the capacitors allows reduced coupling effects among the capacitors when compared with a structure where the capacitors are arranged in line. In this way, the coupling interference can be reduced.

In an embodiment, projections of the first, second, third and fourth capacitors 311 -314 on a surface of the substrate 310 are squares having a same size. The first and second terminal leads of each capacitor 311 -314 extend from a pair of opposite sides of the square on which the capacitor is projected, respectively, as shown in Fig. 3. When the projections of the capacitors 311 -314 on the surface of the substrate 310 are identical squares, the structure of the quadrature hybrid 300 can be more compact and design parameters of the capacitors can be

determined more easily.

In an embodiment, projections of the first and third inductors 321 and 323 on a surface of the substrate 310 are squares each having a first size. The first and second terminal leads of each of the first and third inductors 321 and 323 extend from neighboring sides of the square on which it is projected, respectively.

Projections of the second and fourth inductors 322 and 324 on the surface of the substrate 310 are squares each having a second size. The first and second terminal leads of each of the second and fourth inductors 322 and 324 extend from neighboring sides of the square on which the inductor is projected, respectively. When the projections of the inductors 321 and 323 on the surface of the substrate 310 are identical squares and the projections of the inductors 322 and 324 on the surface of the substrate 310 are identical squares, the structure of the quadrature hybrid 300 can be more compact and design parameters of the inductors can be determined more easily. IP130297

In the following, the structures of the capacitors and inductors in the quadrature hybrid shown in Fig. 3 will be described in detailed.

Fig. 4 is a top view of a capacitor (e.g., the capacitor 311 ) used in the quadrature hybrid 300 shown in Fig. 3. The other capacitors 312-314 may have the same structure as that of the capacitor 311 .

As an example, the capacitor can be a Vertically-lnterdigital-Capacitor (VIC). As shown in Fig. 4, the projection of the capacitor 311 on the surface of the substrate is a square having a width of W _c , which is a design parameter to be determined and will be described later. The capacitor 311 has a first terminal lead 401 and a second terminal lead 402. The first terminal lead 401 and the second terminal lead 402 extend from a pair of opposite sides of the square, respectively. Fig. 5 is a three dimensional view of the capacitor shown in Fig. 4. In the example shown in Fig. 5, the substrate includes ten dielectric layers 501 -510 made of e.g., Low Temperature Co-fired Ceramic (LTCC) material. It can be appreciated by those skilled in the art that the substrate can also be a multilayered PCB or Liquid Crystal Polymer (LCP). The capacitor 311 (which is a VIC in this example) has eight layers 521 -528. Eight layers of the VIC 311 are arranged on eight dielectric layers 501 -508, respectively. The first, third, fifth and seventh layers 521 , 523, 525 and 527 are connected to the first terminal lead 401 through a via 511 . The second, fourth, sixth and eighth layers 522, 524, 526 and 528 are connected to the second terminal lead 402 through another via 512. It can be appreciated by those skilled in the art that the substrate and/or the capacitor may include more or less layers.

Fig. 6 is a top view of an inductor (e.g., the inductor 321 ) used in the quadrature hybrid 300 shown in Fig. 3. The other inductors 322-324 may have the same structure as that of the inductor 321 .

As an example, the inductor 321 can be a spiral inductor. As shown in Fig. 6, the projection of the inductor 321 on the surface of the substrate is a square having a width of W _L , which is a design parameter to be determined and will be described later. The inductor 321 has a first terminal lead 601 and a second terminal lead 602. The first terminal lead 601 and the second terminal lead 602 are arranged in IP130297

orthogonal directions. In particular, the first terminal lead 601 and the second terminal lead 602 extend from neighboring sides of the square.

Fig. 7 is a three dimensional view of the inductor shown in Fig. 6. In the example shown in Fig. 7, the substrate includes ten dielectric layers 701 -710 made of e.g., LTCC material. It can be appreciated by those skilled in the art that the substrate can also be a multilayered PCB or Liquid Crystal Polymer (LCP). The inductor 321 (which is a spiral inductor in this example) has seven layers (6.75 turns). The line width of the inductor can be e.g., 0.2 mm, so as to increase its Q value which has a significant influence on the in-band insertion loss of a passive component. Seven layers of the spiral inductor 321 are arranged on seven dielectric layers 701 -707, respectively. The first terminal lead 601 is connected to the first layer. The first layer is connected to the second layer through a via, the second layer is connected to the third layer through a via, and so on. The second terminal lead 602 is connected to the seventh layer through a via. It can be appreciated by those skilled in the art that the substrate and/or the inductor may include more or less layers.

Next, a circuit design process for determining the parameters as mentioned above will be discussed. In the following, it is assumed that the projections of the capacitors 311 -314 on the surface of the substrate 310 are identical squares each having a width of W _c , the projections of the inductors 322 and 324 on the surface of the substrate 310 are identical squares each having a width of W _L i and the projections of the inductors 321 and 323 on the surface of the substrate 310 are identical squares each having a width of W _L 2. In other words, the four capacitors 311 -314 are identical, each having a capacitance value of C; the inductors 322 and 324 are identical, each having an inductance value of L1 ; and the inductors 321 and 323 are identical, each having an inductance value of L2. In the following simulation, a Ferro-A6 material with a dielectric constant of 5.9 and a loss tangent of 0.002 is used for the LTCC substrate. Each LTCC layer has a post-fired thickness of 0.1 mm. AWR MWO and AXIEM solver are used as circuit and electromagnetic simulators, respectively. IP130297

At step S1 , the values of L1 , L2 and C are determined based on the equivalent circuit shown in Fig. 1 (a). As noted above, with the MWO simulator, these values can be determined as: L1 =52 nH, L2=38 nH and C=68 pf. At step S2, electromagnetic models are established for the VICs and spiral inductors using the AXIEM simulator to determine the parameters W _c , W _L i and W|_2, such that their performances can match those of their equivalent elements.

At step S3, the entire quadrature hybrid is simulated and optimized in the AXIEM simulator. However, the electromagnetic simulation results of the quadrature hybrid may not match those of its equivalent circuit due to parasitic effects and mutual coupling of passive elements.

At step S4, the electromagnetic simulation results of the VICs and spiral inductors are considered in the MWO simulator and the values of L1 , L2 and C are adjusted such that the overall performance can meet the requirements for the quadrature hybrid. Then, a set of new values for L1 , L2 and C can be obtained: L1 '=43.9 nH, L2'=35.22 nH and C'=48.8 pf. At step S5, the electromagnetic models of the VICs and spiral inductors are combined in the AXIEM simulator to determine the final values for the parameters Wc, W _L i and W _L2 .

In order to provide the capacitance value of C'=48.8 pf at 130 MHz, W _c =4.25 mm is determined and its Q value is 195.4 (absolute value) at 130 MHz, as shown in Fig. 8. It can be seen that the multi-layered structure of the VIC provides higher capacitance and Q values than the traditional planar capacitors.

In order to provide the inductance values of L1 '=43.9 nH and L2'=35.2 nH at 130 MHz, it can be determined that W _L i=1 .4 mm and W _L 2 = .25mm and their Q values are 54.28 and 49.57 (absolute value) at 130 MHz, respectively, as shown in Fig. 9 (a) (for L1 ') and Fig. 9 (b) (for L2'). The multi-layered structure of the spiral inductor provides higher inductance and Q values than the traditional inductors. IP130297

Fig. 10 shows electromagnetic simulation results of the quadrature hybrid 300 shown in Fig. 3. In Fig. 10, the horizontal axis represents frequency, the vertical axis on the left represents S-parameter in dBs and the vertical axis on the right represents phase balance in degrees. Again, it is assumed that the first, second, third and fourth ports are input, direct, coupled and isolated ports, respectively. The S-parameters S(1 , 1 ), S(2, 1 ), S (3, 1 ) and S (4, 1 ) are better than -25 dB, -2.8 dB, -3.9 dB and -25 dB at 130 MHz, respectively. The phase balance between the coupled and direct ports is 89.9° at 130 MHz. Moreover, a 24 dB suppression for the second harmonic and a 36 dB suppression for the third harmonic are obtained.

The overall dimension of the quadrature hybrid according to the disclosure can be only 11 x 11 x 1 (width x length x height) mm for working at 130 MHz. A size reduction of approximately 95% can be achieved when compared with the traditional quadrature hybrid based on microstrip lines. The multi-layered capacitors and inductors provide higher capacitance, inductance and Q values. In addition, since the capacitors and inductors are buried into the multi-layered substrate, the performance of the quadrature hybrid is less vulnerable to environmental conditions, such as temperature, humidity and electromagnetic interferences. Finally, the quadrature hybrid according to the disclosure also exhibits an excellent harmonics suppression performance.

The disclosure has been described above with reference to embodiments thereof. It should be understood that various modifications, alternations and additions can be made by those skilled in the art without departing from the spirits and scope of the disclosure. Therefore, the scope of the disclosure is not limited to the above particular embodiments but only defined by the claims as attached.