Field of the invention

The present invention relates to a quadrature oscillator circuit and method. In particular, but not exclusively, it relates to a LC voltage controlled oscillator circuit and method.

Background of the invention

LC oscillators are well known and used in a large spectrum of applications, such as ultra-wideband communication systems, for generating periodic signals including quadrature outputs.

To generate such quadrature outputs, a quadrature clock signal is required in order to achieve image rejection when mixing. The I and Q outputs of the quadrature clock must be accurately matched in phase and amplitude as any error in this quadrature relationship will limit the image rejection and contribute to errors in the output data.

Many techniques have been developed to achieve I and Q outputs matched in phase and amplitude. One such technique is known as cross coupling. Two identical voltage controlled oscillators (VCOs) are utilised and cross coupled with each other such that the outputs are locked into a 90° phase shift to achieve the quadrature output, for example, as disclosed by A. Rofougran et al. in "A 900 MHz CMOS LC-oscillator with quadrature outputs" in IEEE Int. Solid State Circuits Conf. (ISSCC) Dig. Tech. Papers, pages 392-393, 1996.

This concept has been further developed and illustrated in Chao-Shiun Wang et al in "A Low Phase Noise Wide Tuning Range CMOS Quadrature VCO using Cascode Technology" in Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004, 4-5 Aug. 2004 pages 138-141. The core and connectivity of this known VCO is illustrated in Figure 1. The quadrature oscillator circuit comprises two substantially identical VCO circuits 10Oa and 100b. Each VCO circuit 100a, 100b comprises a current source 101 , the output of which is connected to source of a pair of pFETs 103a and 103b, respectively. The gate of each of the pair of pFETs 103a and 103b is connected to the drain of the other. The drains of the pFETs 103a and 103b are connected across an LC circuit (known as an LC tank), which includes an inductor 105a and a variable capacitor 105b for tuning the LC circuit. It is noted that the LC circuit may include other components not shown in Figure 1 , for example additional capacitors or switching devices. The drains of a first pair of nFETs 107a, 107b are also connected to the LC circuit comprising the inductor 105a and variable capacitor 105b. The source of each nFET 107a, 107b is connected to the respective drains of a second pair of nFETs 109a, 109b. The gate of each of the second pair of nFETs 109a, 109b is connected to the drain of the other of the first pair of nFETs 107a, 107b. The outputs of the tunable LC circuits provide the I components and Q components which are cross-coupled to the gate of the first pair of nFETs 107a, 107b of the other VCO circuit. The current source 101 sets the amplitude of the signal swing of the VCO circuits 100a, 100b and may be variable.

Although this arrangement provides some stability to the amplitude and phase of the quadrature outputs, small differences in the physical implementation result in offsets and mismatch between individual VCO components: varactors, inductors, capacitors and switching devices. This, in addition to differences in bias current mirroring, will contribute to differences in the I and Q amplitude.

Alternative methods of improving I and Q matching involve increasing the device sizes to reduce mismatch errors. However, this has a detrimental impact on chip area and, more importantly, on operating frequency. The parasitic capacitive loading effect of the devices can represent a significant proportion of the total capacitance within the LC oscillator.

Another method of achieving quadrature outputs without the issue of mismatch between LC cores is to design the VCO to operate at twice the desired frequency. Quadrature signals can then be generated using divide-by-two counters. However, using this approach for high frequency systems, such as Ultra-wideband, can be extremely problematic, particularly in a CMOS process.

Summary of the invention

The invention seeks to provide improved amplitude control in quadrature oscillators such that the same differential amplitude is maintained by the oscillators, reducing the sensitivity to device mismatch effects. This improved performance is crucial for communication systems which rely on accurate matching between the I and Q channels.

This is achieved, according to an aspect of the present invention, by a quadrature oscillator circuit comprising first and second oscillator stages, each of said first and second oscillator stages having a controllable amplitude, an output of each of said first and second oscillator stages being fed back via an automatic amplitude control circuit to control the amplitude of the output of each oscillator stage.

As a result improved I and Q amplitude matching is achieved, and sensitivity to device mismatch is reduced. Further, the size of the VCO core devices for matching purposes is reduced, lowering overall chip area whilst increasing maximum VCO operating frequency. Furthermore, the yield is improved due to reduced sensitivity to mismatch in small geometry processes, for example 130nm or 90nm CMOS processes.

The automatic amplitude control circuit (AAC) may be adapted to control the amplitude of the output of each oscillator stage such that the amplitude of the output of each oscillator stage is substantially equal. The AAC loop maintains an optimum signal swing at the output, thereby further improving the variation in amplitude.

In an embodiment the automatic amplitude control circuit comprises first and second automatic amplitude control circuits, each of the first and second automatic amplitude control circuits being connected to respective outputs of the first and second oscillator stages. The differential I and Q output amplitudes of the first and second oscillator stages are forced to be substantially equal through the use of two separate automatic amplitude control (AAC) loops. The amplitude control loops adjust the current in the VCO cores to achieve the required output amplitude. By this method, and careful layout matching of the AAC input devices and references, very good amplitude matching is achieved.

To improve regulation of the amplitude of the quadrature outputs to an optimum level, the automatic amplitude control circuit may comprise a common circuit connected to respective outputs of the first and second oscillator stages.

In an embodiment the first and second automatic amplitude control circuits have a common amplitude control reference to reduce the impact of any difference between the automatic amplitude control circuits, thus providing an improved amplitude matching of the quadrature output.

According to a further aspect of the invention, there is provided a method of providing matched amplitudes in the I and Q channels of a quadrature oscillator circuit comprising first and second oscillator stages, each of said first and second oscillator stages having a controllable amplitude. The method comprises the steps of feeding back an output of each of said first and second oscillator stages via an automatic amplitude control circuit to control the amplitude of each oscillator stage.

Brief description of the drawings

For a more complete understanding of the present invention, and to show how the invention may be carried into effect, reference is now made to the following description taken in conjunction with the accompanying drawings, in which

Figure 1 is an example of known quadrature LC VCOs;

Figure 2 is a simplified schematic block diagram of a quadrature oscillator according to an embodiment of the present invention; Figure 3 is a simplified schematic block diagram of a quadrature oscillator according to another embodiment of the present invention; and

Figure 4 is a simplified schematic block diagram of a quadrature oscillator according to yet another embodiment of the present invention.

Detailed description of the embodiments

As shown in Figure 2, the quadrature oscillator circuit 300 according to a first embodiment comprises first and second oscillator (VCO) stages 301 , 303. The first and second oscillator stages 301 , 303 may comprise substantially identical cascaded cross- coupled oscillator circuits having variable amplitude control, similar to those shown in Figure 1. It is noted, however, that the invention is not limited to such oscillator circuits, and is intended to embrace other types of oscillator circuits. The first oscillator stage 301 comprises a first input terminal 305, a second input terminal 307, a first output terminal 309, a second output terminal 31 1 and an amplitude control terminal 313. The second oscillator stage 303 comprises first and second input terminals 315, 317, first and second output terminals 321 , 323 and an amplitude control terminal 327.

The first and second output terminals 309, 31 1 of the first oscillator stage 301 are connected to the respective first and second input terminals 315, 317 of the second oscillator stage 303. The first and second output terminals 309, 311 are also connected to respective input terminals of a first automatic amplitude control (AAC) circuit 319.

First and second output terminals 321 , 323 of the second oscillator stage 303 are connected to respective input terminals of a second automatic amplitude control (AAC) circuit 325. The output at the first output terminal 321 of the second oscillator stage 303 is fed back to the second input terminal 307 of the first oscillator stage 301. The output at the second output terminal 323 of the second oscillator stage 303 is fed back to the first input terminal 305 of the first oscillator stage 301 such that the outputs of the second oscillator stage 303 are inverted when fed back to the first oscillator stage 301 , thereby cross-coupling the VCO circuits 301 , 303. The first and second AAC circuits 319, 325 are controlled by an amplitude control reference A _ref . The amplitude control reference A _ref is preferably common to both the first and second AAC circuits 319, 325. The amplitude control reference A _ref may be a voltage reference created on-chip or off- chip, and will be set to a level proportional to the required output amplitude. This reference may be fixed or variable according to system requirements.

The output of the first AAC circuit 319 is connected to the amplitude control terminal 313 of the first oscillator stage 301 and the output of the second AAC circuit 325 is connected to the amplitude control terminal 327 of the second oscillator stage 303. It is noted that the respective outputs of the first and second AAC circuits 319, 325 may be a current signal or a voltage signal.

The first oscillator stage 301 provides the l+ component and its complement I- on its output terminals 309, 31 1 , while the second oscillator stage 303 provides the Q+ component and its complement Q- on its output terminals 321 , 323. The first and second AAC circuits 319, 327 control the amplitude of the first and second oscillator stages 301 , 303.

The use of this approach overcomes the dominant sources of mismatch in the oscillator stages 301 , 303 and many of the differences between the first and second AAC circuits 319, 325 will be corrected by the action of the feedback loops themselves. Care must still be taken with the design and layout to reduce the effect of the remaining mismatch sources, in particular the AAC input devices and the reference voltage A _ref . As the same reference voltage A _ref is preferably used for both loops, mismatch is negligible, and effectively cancelled. The input devices can be well matched by layout and by increasing the size of the devices. It is noted that increasing these devices has less impact on VCO operation than attempting to overcome I and Q mismatch by resizing the core devices themselves.

Another embodiment is shown in Figure 3. The quadrature oscillator circuit 400 is similar to that of the first embodiment in that it comprises first and second oscillator stages 401 , 403. As before, the first and second oscillator stages 401 , 403 may comprise substantially identical cascaded cross-coupled oscillator circuits having variable amplitude control, similar to those shown in Figure 1. It is noted, however, that this embodiment of the invention is not limited to such oscillator circuits, and is intended to embrace other types of oscillator circuits. The outputs of the first oscillator stage 401 are connected to respective input terminals of the second oscillator stage 403. The outputs of the second oscillator stage 403 are fed back to the input terminals of the first oscillator stage 401 such that the outputs of the second oscillator stage 403 are inverted when fed back to the input terminals of the first oscillator stage 401.

The quadrature oscillator circuit 400 of this embodiment comprises an automatic amplitude control (AAC) circuit 419 having its inputs connected to the outputs of the first and second oscillator stages 401 , 403. The output of the AAC circuit 419 is connected to the amplitude control terminals 413, 427 of the first and second oscillator stages 401 , 403, and is controlled using a common reference voltage A _ref . In this way the amplitude of each oscillator stage is corrected by a common AAC loop. The primary function of this loop is to regulate the amplitude to the optimum level, rather than overcome I and Q amplitude mismatch. While there may still be small differences between I and Q, the signals will be centred around the optimum level.

Yet another embodiment is shown in Figure 4. As described with reference to the embodiments above the quadrature oscillator circuit 500 comprises first and second oscillator stages 501 , 503. The first and second oscillator stages 501 , 503 may comprise substantially identical cascaded cross-coupled oscillator circuits having variable amplitude control, similar to those shown in Figure 1. It is noted, however, that this embodiment of the invention is not limited to such oscillator circuits, and is intended to embrace other types of oscillator circuits. The first and second oscillator stages are interconnected as described above with reference to Figures 2 and 3. The first and second output terminals 509, 511 of the first oscillator stage 501 are connected to respective input terminals of first and third automatic amplitude control (AAC) circuits 519, 529. The first and second output terminals 521 , 523 of the second oscillator stage 503 are connected to respective input terminals of a second and the third AAC circuits 525, 529. The first, second and the third AAC circuits 519, 525, 529 are preferably controlled by a common reference voltage A _ref . The outputs of the first and third AAC circuits 519, 529 are connected to the amplitude control terminal 513 of the first oscillator stage 501. The outputs of the second and third AAC circuits 525, 529 are connected to the amplitude control terminal 527 of the second oscillator stage 503. The amplitude of each oscillator stage, i.e. VCO circuit, is then controlled by a pair of AAC circuits. The benefit of this approach is that it lessens the required contribution of the separate I and Q correction loops and reduces possible impact of differences between the I and Q AAC input stages. However this approach requires greater complexity and care must be taken to avoid stability issues due to multiple loops.

The various embodiments of the invention described above provide an improved amplitude control in quadrature oscillators such that the same differential amplitude is maintained by the oscillators, reducing the sensitivity to device mismatch effects.

Although embodiments of the present invention have been illustrated in the accompanying drawings and described in the foregoing description, it will be understood that the invention is not limited to the embodiments disclosed but is capable of numerous modifications without departing from the scope of the invention as set out in the following claims.