RADIATION DETECTOR AND METHOD OF MANUFACTURE THEREOF

Technical Field

The invention concerns a radiation detector for position-resolved detection of radiation as well as a method of manufacturing such detector. Background Art

Radiation detectors are mainly used for the detection of electromagnetic radiation e.g. in the X-ray band, or electrons with energies e.g. between IkeV and 400keV. For some applications, a position-resolved detec tion of the radiation is required, e.g. in medical appli cations such as X-ray measurements or computed tomography (CT) scans for e.g. mammography or angiography, or e.g. in electron microscopes for applications like cryogenic electron microscopy (Cryo-EM), scanning electron micros copy (SEM), transmission electron microscopy (TEM) or scanning transmission electron microscopy (STEM)

A well-known class of detectors are semicon ductor detectors which either directly or indirectly con- vert incident radiation, i.e. incident photons or elec trons, to an electrical charge proportional to the ab sorbed energy. A semiconductor radiation detector can be built up from detector modules. Each module is composed of one or several semiconductor sensor tiles and one or multiple readout application specific integrated circuits (ASICs). The photons or electrons are thus converted to electrical charge in the semiconductor sensor tile. The electrical charge is then evaluated e.g. in terms of a position-resolved image of the incident radiation. In case of photon or electron counting detector, the evalua- tion of the electrical charge, completed at the ASIC, in cludes counting the number of charge pulses above a cer tain threshold within a time frame.

"Position-resolved" means that the detector determines the amount of radiation, e.g. a number of pho tons, a number of electrons, or deposited energy, per lo cation in space. For that purpose, space of sensitive material is usually discretized in pixels represented by areas of electrically conducting material defined on the sensor tile surface. In another embodiment, pixel may refer to a corresponding area defined by an electrically conducting diffusion layer on the sensor layer with a metal contact on top (with the diffusion layer e.g. being part of PIN diode structure formed inside e.g. a sensor layer of silicon). The bottom surface of the sensor tile includes a periodic array of pixels. A distance between neighbor pixels is defined as "pitch". The detector spatial resolution depends on the size and spacing of the pixels. The smaller the pixel in which incident photons or electrons are detected, the smaller can usually the pixel pitch be. The higher the number of pixels per sen sor tile area, the better the spatial resolution.

Each pixel is electrically connected to an input contact of a readout ASIC, e.g. by means of solder bumps. The top side of the ASIC includes an array of in put contacts. The pitch of the input contacts in the ASIC is defined as the distance between adjacent input con tacts. Usually the pitch of the input contacts is uniform across the ASIC. In case the input contacts do not co - pletely cover the ASIC, such pitch uniformity may be bro ken between neighboring input contacts lying at the edge of adjacent ASICs.

The pitch between two regular input contacts may preferably be between 20 um and 500 urn. In conven- tional semiconductor radiation detectors, the electrical connection between pixels and input contacts is direct, i.e. the sensor pixel pitch and ASIC input contact pitch are identical and the input contacts and the correspond ing pixels are located directly opposite to each other.

Multiple detector modules can be assembled side by side such that radiation in an area larger than the area of a single detector module is registered. In the region where adjacent modules are joined, a gap oc curs, where no radiation will be detected.

Further, the quality of the space-resolved detection also depends on further factors. In state of the art semiconductor detectors, the charge created by the incident radiation is converted to a voltage in an ASIC with a charge sensitive amplifier. The amplitude of the resulting voltage signal as well as its underlying noise level are strongly influenced by the capacitance at the input of the amplifier. Optimal performance of a sem iconductor detector is achieved, when the noise is as low as possible, and the signal as large as possible. As the signal-to-noise ratio determines basic detector performance parameters like e.g. the response of the detector to low energy radiation, it is important to have a uniform and high signal-to-noise ratio of the voltage signal over the full detector. In order to ensure a high and uniform signal-to-noise ratio, it is necessary to reduce the capacitance at the input of the charge sensitive am- plifier, and to achieve a uniform capacitance distribu tion over the full detector. Further noise sources from ambient noise sources need to be reduced as well, as they further decrease the signal-to-noise ratio.

Generally it is desired to have a radiation detector that covers an area without or at least reduced insensitive gaps and without or at least reduced devia tions on the pixel pitch between detector modules, sensor tiles or in the region between two ASICs. This is particularly important for imaging applications, e.g. for medi- cal applications or for electron imaging applications.

Conventional radiation detectors exhibit gaps between de- tector modules and/or a different pitch between neighbor ing pixels corresponding to neighboring input contacts in adjacent ASICs. Radiation or photons which hit the gap between two detector modules or sensor tiles are actually not incident on a pixel and hence not detected. This leads to the loss of a fraction of the incoming radia tion. Furthermore, the input contacts periodicity distor tion between neighboring ASICs lead to local variations of the detector spatial resolution when x-rays or elec- trons hit the region between two ASICs. It is hence an object of the invention to provide a radiation detector with high resolution covering a large area without or at least minimized gaps and without or at least reduced pixel pitch variation in the junction between ASICs, sen- sor tiles and/or detector modules. The invention may have particular impact in x-ray or electron imaging applica tions .

Disclosure of the Invention

The object is achieved by a radiation detec tor for position-resolved detection of radiation which comprises the following elements:

- at least one sensor tile with sensor mate- rial sensitive to the radiation, defining a horizontal plane: The sensor tile may have a rectangular or in particular quadratic shape in the horizontal plane with a side length of e.g. 2 cm or 4 cm or 6 cm or 8 cm. The radiation is X-ray radiation with typical energies between 2 keV and 200 keV, or electron radiation with energies between 2 keV and 400 keV. X-radiation for medical applications typically has an energy in the range of 5 to 100 keV or up to 200 keV. Suitable semiconductor sensor materials are silicon, gallium arsenide, cadmium tellu- ride or cadmium zinc telluride. The sensor material is preferably adapted to convert incident radiation or an incident photon to electrical charge, which can then be measured .

- a set of pixels of electrically conducting material in contact with the sensor material: A pixel is defined as a surface area in the horizontal plane, typi cally made of metal. Any electrical charge induced in the pixel, and in particular originating from a converted photon or electron, contributes to a measurement value of the pixel. Hence, the detector spatial resolution, i.e. the number of pixels or measurement values per unit area, depends on the pixel pitch. Preferably the pixels are rectangular and in particular quadratic with a side length typically between 20 and 1000 ym, ideally between 30 and 450 ym. The set of pixels may be a grid-like ar- rangement, e.g. a rectangular grid, ideally covering a large fraction of the sensitive material of the sensor tile, e.g. at least 90%, 95% or 99%.

- at least one ASIC with input contacts in electrical connection with the pixels, wherein at least one input contact is horizontally offset relative to a corresponding pixel: Each input contact is preferably connected with exactly one corresponding pixel, meaning that a number of pixels of the set is preferably equal to a number of input contacts. Preferably one or multiple ASICs correspond to, i.e. evaluate all signals of one sensor tile. The one or more ASICs are preferably config ured to evaluate an electrical signal collected on the pixels in contact with the ASICs input contacts. In particular evaluating may comprise at least one or more of determining an amount of electrical charge per pixel and time, counting a number of incident photons or electrons above a given signal threshold converted to electrical charge per pixel and time, and further processing such as calibration. Preferably, the at least one ASIC assigned per sensor tile is arranged in a plane parallel to the horizontal plane defined by the sensor tile, and preferably is arranged in a stack together with the sensor tile and possibly other components such as the redistribution layer introduced below. Preferably, the input contacts of the ASIC face the pixels even though other components may be arranged in between. For a simple attribution of input contacts to pixels, it would be desirable to have each input contact "directly below", i.e. without any horizon tal offset to the corresponding pixel. This, however, may not be possible because of a different size of the sensor tile compared to the size of the ASIC/s or because of space under the sensor tile and horizontally besides the input contacts that is required for other elements such as input/output (I/O) pads for reading out the ASIC/s, setting parameters of the ASIC/s or providing power or reference voltages to the ASIC/s. - a redistribution layer between the at least one sensor tile and the at least one ASIC, the redistri bution layer comprising conductor tracks electrically connecting the pixels with a contact array located in a plane parallel to the sensor surface, preferably with a pitch identical to the pitch of the input contacts of the ASIC: In other words, the redistribution layer facili tates an electrical and preferably also mechanical connection between the sensor tile and the ASIC. In view of each input contact preferably being connected with ex- actly one corresponding pixel, the redistribution layer provides one conductor track per pair of pixel / input contact. Such conductor track preferably has only one or more horizontal portions, and one or more vertical portions referred to as vias. Preferably the conductor tracks connect the pixels through under bump metallization (UBM) contacts and solder bumps to the input con tacts of the at least one ASIC.

In the radiation detector according to the invention, at least one of the conductor tracks crosses at least one crossed pixel different from the corresponding pixel. This means that such conductor track crosses at least one pixel, the "crossed pixel", which may and should detect different signals from photons or electrons than the corresponding pixel. Preferably, the crossing conductor track connects to the corresponding input con tact horizontally offset from the corresponding pixel, and thereby crosses one or more different crossed pixels. Preferably, a crossed pixel is a neighbor pixel to the corresponding pixel.

The crossing as implemented in conventional detectors leads to the problem of capacitive coupling be- tween signals of different pixels, i.e. photons and electrical charge detected by the corresponding pixel affect the signal of the crossed pixel, also called crosstalk between pixels. This deteriorates signal quality. In par ticular, the crossing leads to so-called parasitic capac- itances between the corresponding pixel and the at least one crossed pixel. Furthermore, as this parasitic capacitance depends on the location and geometry of the crossed pixel, not every pixel will see the same input capaci tance at the ASIC amplifier, leading to a non-uniform signal-to-noise ratio.

In the radiation detector according to the invention, this problem is avoided or at least minimized in the following way: The at least one crossed pixel has a void of the electrically conducting material corre- sponding to at least a portion of the projection of the crossing conductor track. Projection means an area on the crossed pixel where the conductor track is projected vertically, i.e. orthogonal to a surface of the pixel in the horizontal plane, onto the crossed pixel. While the pixel is of electrically conducting material, it preferably does not have any electrically conducting material within at least a portion of the projection. This means that the pixel, which otherwise may be rectangular or quadratic, may have a hole corresponding to at least a portion of the projection.

Such pixel design avoids or at least mini mizes the parasitic capacitance between a crossed pixel and the pixel corresponding to a certain input contact of the ASIC or to a certain conductor track, respectively.

In addition, a more uniform input capacitance distribu tion is reached at the ASIC input contacts. This can be understood when considering the simplified example of a parallel-plate capacitor whose capacitance C is given as C = eA/d with the permittivity e of material between the plates, the plate area A, and the plate distance d. It follows that the larger the plate area A, the larger is the capacitance C, which in the present case is an undesired parasitic capacitance. Hence avoiding plate areas A opposite to each other as in a parallel-plate capacitor, as is done according to the present invention with the void in the at least one crossed pixel, minimizes a para- sitic capacitance.

Preferably, each pixel of the tile is a crossed pixel and has a void from a crossing conductor track. Such design reflects a highly compacted arrange ment of input contacts on the ASIC. In general, designing pixels according to the present invention enables in par ticular to make the redistribution layer thinner, e.g. with a thickness of between 0.1 and 10 pm, which is equivalent to making the plate distance d in the above formula smaller, without enlarging parasitic capacitances and deterioration measurement quality.

At the same time, the pixel design according to the invention allows to vary the ASIC size and/or shape independent of a size and/or shape of the sensor tile. This yields various possibilities for designing the radiation detector. In particular, it facilitates a re duction of gaps, in particular gap width, between tiles, while keeping the pixel pitch constant. In this way, less radiation or photons passes through the detector unde tected, and the effective resolution will not be dis- torted in regions between adjacent ASICs or adjacent sen sor tiles. Horizontal offset between a pixel and the corresponding input contact on the ASIC preferably refers to a location of the input contact on the one hand, and to a location of a termination point of the conductor track within an area of the corresponding pixel on the other hand. Given the size of a pixel, the termination point may lie in different regions of the pixel as desired. Hence, designing the termination point in the area of a pixel, e.g. per pixel, may in addition serve to re- duce crosstalk. In one embodiment, at least two pixels of the set of pixels have different termination points within the respective pixels. Preferably, at least one, and preferably all of the termination points are located at the edges of the corresponding pixel areas. In case the corresponding conductor track is led right to the neighboring gap, crosstalk can be minimized in this way, too. Preferably, a combination of the aforementioned two embodiments is applied. Termination points are preferably only arranged at edges of the pixels, however, at differ- ent edges. For example, termination points may be on a right hand edge of pixels of a first subset while termi nation points may be on a left hand edge of pixels of a second subset

Further advantageous features according to the invention are as follows:

The at least one sensor tile preferably has a larger surface area in the horizontal plane than the at least one ASIC. Further, the at least one sensor tile protrudes over at least one edge of the at least one ASIC assigned, in its projection on the at least one ASIC.

More preferably, the at least one sensor tile has a larger surface area in the horizontal plane than the at least one ASIC assigned. In particular, a horizontal ex tension of the set of pixels is larger than an extension of the array of input contacts.

This means that there is some space in the ASIC, below the sensor tile and besides the ASIC input contacts array which may be used for different elements, e.g. for input/output (I/O) pads of the ASIC. Thus neighboring tiles can be arranged closer together, hence avoiding undesired gaps between sensor tiles. In an em- bodiment, each sensor tile has a surface area of at least 2 cm x 2 cm.

In a preferred embodiment, the radiation detector comprises a set of sensor tiles and/or modules arranged adjacent to each other in the horizontal plane, wherein the tiles and/or modules are separated by gaps.

An overall surface of the gaps in the horizontal plane is preferably smaller than 10%, in particular smaller than 5% or 1%, of an overall surface of the tiles and/or mod ules . In a preferred embodiment, for collecting the charge generated inside the semiconductor sensor tile an electric field (bias voltage) is applied across the semiconductor sensor tile. To create the electric field a high-voltage (HV) preferably is applied on the side of sensor tile that faces the incident radiation. The HV is typically applied to a metal electrode on the sensor tile e.g. via a wire bond to the metal electrode or via a wire bond connected to a conductive tape on the electrode or using conductive tape for connecting directly to the electrode or to the semiconductor.

Further, an area of the void preferably amounts to at least 80%, in particular at least 90%, of an area of the projections, which area defines the por tion of the projection. While the void may be differently shaped and in particular larger or smaller than the projections, it is advantageous that the void occupies at least said portion of the projections in order to minimize parasitic capacitances.

A / the void/s are preferably delimited by continuous edges of electrically conducting material.

This means that the void in particular is a hole through the pixel, and not only a recess in the pixel. In an embodiment, the void covers the whole area of the projec tion but not the edge of the pixel which is left as a continuous electrical connection. Such pixel design makes sure that all parts of a pixel are on the same potential, in particular in the case where a projection would otherwise cut a crossed pixel into two or more parts.

Parasitic capacitances may alternatively or additionally be minimized or avoided in other ways ac- cording to the above formula, namely by changing the permittivity e of material between the plates, i.e. between the conductor track and the crossed pixel, and or by changing the plate distance d, i.e. the distance between the conductor track and the crossed pixel which is in particular similar to the thickness of the redistribution layer. According to this idea, it is advantageous that the redistribution layer has a thickness of at least 1 pm, in particular at least 5 pm. Moreover it is advan tageous that the redistribution layer comprises a low-k material, meaning a material, particularly a dielectric, with a relative permittivity of e _r < 3.9. Preferable ex amples for the low-k material are e.g. porous Si02, F- doped Si02, Polyamide.

In a further embodiment, the radiation detec- tor comprises a substrate for holding and contacting the at least one ASIC. The substrate may comprise an electric insulator substrate and an external conductive via through the insulator substrate, e.g. one external con ductive via per ASIC. In particular an I/O pad of the at least one ASIC is electrically connected to the external conductive via, in particular by printed micro wire or by tab bonding or by wire bonding. Hence the substrate preferably acts as a holder and in particular facilitates mounting more than one ASIC and at least one module on one radiation detector. In yet another embodiment, the radiation de tector further comprises a shield between the redistribu tion layer and the at least one ASIC. The shield preferably is arranged on the redistribution layer and prefera- bly faces at least one of an I/O pad of the ASIC or a conductive via of an electric insulator substrate holding the ASIC. The shield is preferably electrically conduct ing and connected to ground. The shield serves to avoid or at least minimize the crosstalk between digital or an- alog signals routed inside, to or from the I/O pads of the ASIC and the conductor tracks in the redistribution layer or the pixels. It is advantageous that a projection of the shield covers at least 50%, in particular at least 80%, of a surface area of the ASIC that is not covered by input contacts.

According to another aspect of the invention, a method of manufacturing a radiation detector is pro vided. It comprises the steps of

- providing at least one sensor tile compris- ing a sensor material sensitive to the radiation,

- forming a set of pixels of electrically conducting material in contact with the sensor material, in particular by applying photolithography and metallization, - depositing a dielectric coating layer, in particular contributing to a redistribution layer,

- etching a via hole per pixel into the dielectric coating layer,

- forming conductor tracks by filling the via holes with an electrically conducting material defining redistribution tracks on the dielectric coating layer, in particular by applying photolithography and metalliza tion,

- defining contacts of the conductor tracks, in particular by UBM, and depositing another dielectric coating layer on the redistribution tracks, in particular the other dielectric coating layer also contributing to the redistribution layer, and

- electrically connecting the contacts of the conductor tracks to input contacts of at least one ASIC. The at least one input contact is horizontally offset relative to a corresponding pixel. At least one of the conductor tracks crosses at least one crossed pixel different from the corresponding pixel. And at least one crossed pixel has a void of the electrically conducting material corresponding to at least a portion of projections of the conductor tracks.

Further it is advantageous that the method comprises at least one of the following steps:

- arranging a set of tiles adjacent to each other in a horizontal plane, wherein the tiles are sepa rated by gaps, wherein an overall surface of the gaps in the horizontal plane is smaller than 10%, in particular smaller than 5% or 1%, of an overall surface of the tiles, - providing a substrate for holding and con tacting the at least one ASIC, in particular wherein the substrate comprises a electric insulator substrate and an external conductive via through the insulator substrate per ASIC, - mounting the at least one tile and the at least one ASIC to the substrate,

- electrically connecting an I/O pad of the at least one ASIC to the external conductive via, in par ticular by printed micro wire or by tab bonding or by wire bonding.

The described embodiments and features similarly pertain to the radiation detector and to the method. Synergetic effects may arise from different com binations of the embodiments and features although they might not be described in detail. Brief Description of the Drawings

The invention will be better understood and objects other than those set forth above will become ap- parent when consideration is given to the following de tailed description thereof. Such description makes refer ence to the annexed drawings, wherein:

Fig. 1 shows a pixelated sensor tile (on the left) and an ASIC containing an array of input contacts (on the right) of a radiation detector according to the state of the art;

Fig. 2 shows a cross-section through a radiation detector module with a pixelated sensor and a pixelated ASIC as in Fig. 1; Figs. 3a and 3b show detector modules of a radiation detector; Fig 3a shows detector modules com posed by a sensor tile per ASIC, whereas in Fig. 3b, several ASICs are connected to one sensor tile;

Fig. 4 shows an exploded view of a radiation detector according to the state of the art;

Fig. 5 shows a cross-section through a radia tion detector with redistribution layer according to the state of the art;

Fig. 6 shows a perspective view on the redis- tribution layer of a radiation detector according to the state of the art;

Fig. 7 shows a top view on the redistribution layer of Fig. 6;

Fig. 8 shows a top view on representative six pixels of a radiation detector according to an embodiment of the invention;

Fig. 9 shows a cross-section through a tile and a redistribution layer of a radiation detector ac cording to an embodiment of the invention;

Fig. 10 shows a cross-section similar to Fig. 9 but with a greater thickness of the redistribution layer according to an embodiment of the invention; is

Fig. 11 shows a cross section of a the assem bly of an ASIC within a substrate according to an embodi ment of the invention;

Fig. 12 shows a cross-section of a radiation detector with a substrate according to the embodiment of Fig. 11;

Figs. 13 to 16 show photolithography masks (Figs. 13a to 16a) and cross-sections of a radiation detector (Figs. 13b to 16b) as used and obtained in a method of manufacturing a radiation detector according to an embodiment of the invention;

Figs. 17 and 18 show photolithography masks for redistribution tracks and vias in an outer part and an inner part of a tile of a radiation detector according to an embodiment of the invention.

Modes for Carrying Out the Invention

For a better understanding of the problem as well as its solution according to the invention, first features of state-of-the-art radiation detectors are described by means of Figs. 1 to 7.

Fig. 1 shows a pixelated sensor (on the left) and an ASIC containing an array of input contacts (on the right) of a radiation detector according to the state of the art. At least one pixelated sensor tile 1 or an array of sensor tiles and at least one ASIC 5 or an array of ASICs 5 constitute a radiation detector module, where one or multiple radiation detector modules constitute the ra- diation detector. An array of pixels 2 contacting the sensor material, which is sensitive to the radiation, in Fig. 1 has a size of 256 x 256 pixels. The pixelated ASIC 5 (on the right of Fig. 1) has the same number of input contacts 4 as the pixelated sensor has pixels, i.e. 256 x 256. Further, the ASIC 5 comprises I/O pads 6 for in put/output of electrical signals and peripheral circuitry, such as control blocks and guard rings, which consume a part of the ASIC surface.

Typically, the pixels 2 and the input con- tacts 4 of the ASIC 5 are electrically connected to each other in a one-to-one relationship of pixels and corre sponding input contacts, meaning that the number of input contacts 4 is equal to the number of pixels 2. For simplicity, corresponding pixels 2 and input contacts 4 are located adjacent to each other. In state of the art radiation detectors, the pixels in the outermost row and outermost column of the pixel matrix are usually larger than regular pixels within the pixel matrix, in order to cover the area above the peripheral circuitry of the ASIC with pixels in order to be sensitive to radiation in this region as well.

In an embodiment, one sensor tile is connected to multiple ASICs. Typically in this case, the pixels and input contacts of the ASIC are electrically connected to each other in a one-to-one relationship.

As shown in Fig. 2, pixels 2 and correspond ing input contacts 4 are conventionally located directly above/below each other, wherein a vertical above/below direction is defined as perpendicular to an extension of the sensor tile 1 and the pixel array in a horizontal plane. Typically the electrical connection is established by solder balls or bump bonding 3.

The radiation detector module in Fig. 2 is mounted to a high density interconnect (HDI) printed cir- cuit board 8 with read out electronics. In the state of the art, the electrical connection between the I/O pads 6 of the ASIC 5 and the HDI PCB 8 is established by wire bonds 7.

For larger detector area, several radiation detector modules as the one in Fig. 2 are arranged side by side, forming a radiation detector as shown in Fig. 3a and 3b. As can be seen from Figs. 2, 3a and 3b, arranging state-of-the-art detector modules side by side on the PCB

8 results in gaps 9 between the sensor tiles 1. Hence the radiation detector in the state of the art exhibits gaps

9 in the horizontal plane, where no sensor material is placed, meaning that no radiation or photons are detected in these gaps 9. This leads to a loss of details in a re sulting image and a loss of measured signals. In fig. 3a, one sensor tile is attached to each ASIC; while in fig. 3b, one sensor tile is connected to multiple ASICs. In fig. 3a, a further smaller gap is thus formed between tiles within the same detector module. This gap is omitted in fig. 3b. However, in this case, usually the pixels in the region between two ASICs have a larger pitch than regular pixels. In order to avoid these drawbacks, a solution in form of a redistribution layer between the pixels 2 and the input contacts 4 is suggested. This solution is shown in Figs. 4 to 7.

Fig. 4 shows an exploded view of a radiation detector module, which is composed of a sensor tile 1 and an ASIC 5 with similarities with those displayed on Fig.

1. In contrast to Fig. 1, however, the pixelated sensor tile 1 of the embodiment of Fig. 4 has the same size in the horizontal plane as the ASIC 5. This leads to the situation that the pixels 2 in contact with the sensor material of the sensor tile 1 occupy a larger area than corresponding input contacts 4 of the ASIC 5. As depicted in Fig. 5, the ASIC input contacts pitch, i.e. a distance between neighboring input contacts 4, is smaller than the sensor pixel pitch 2a, i.e. a distance between neighboring pixels 2 on the sensor tile 1. In such arrangement, at least some of the input contacts 4 are necessarily offset relative to the corresponding pixels 2.

Fig. 5 also shows a solution from the state of the art, comprising a redistribution layer 10, which establishes the one-to-one connection of pixels 2 with corresponding input contacts 4 through conductor tracks 11 in a dielectric material 12. Typically, the redistribution layer 10 is monolithically integrated on the sensor tile 1.

Figs. 6 and 7 show a perspective view and a top view, respectively, on the redistribution layer 10. Note that the vertical direction in Figs. 6 and 7 is reversed compared to the previous figures. The conductor tracks 11 in Figs. 6 and 7 are depicted as diagonal fea tures connecting the pixels 2 and the input contacts 4 on the shortest path possible. In a typical implementation of a radiation detector, however, the conductor tracks 11 follow the horizontal and vertical directions as sketched in Fig. 5 due to the manufacturing process.

The arrangement of electrically conducting pixels 2, conductor tracks 11 and input contacts 4 as shown in Figs. 5 to 7 leads to the formation of capacitances, e.g. between a certain pixel 2 and a conductor track 11 crossing the pixel in the dielectric redistribution layer 10. Such capacitance is schematically depicted in Fig. 10. It leads to cross-talk between pixels, lowers the signal-to-noise ratio and generates blurring of a re sulting image, hence decreasing the effective resolution. Thus the capacitance is undesired and called a "parasitic" capacitance. Figs. 8 to 19 show solutions to the described problem according to embodiments of the invention. Fig. 8 is a top view on six representative pixels 2 of a sensor tile 1 as used in a detector according to an embodiment of the present invention. While the pixels of a state-of- the-art detector (Figs. 1 to 7) are continuous in the horizontal plane, i.e. are represented by a continuous electrically conducting material, at least one pixel 2 according to the invention comprises a void 14. The void 14 corresponds to at least a portion of a projection of the conductor track 11 crossing the pixel 2. The projection is advantageously made in the vertical direction. In this way, parasitic capacitances 13 are minimized or avoided by minimizing or avoiding an overlap between pix els 2 and conductor tracks 11. It is evident that a size and shape of the void 14 are specific and potentially different for each pixel 2. The voids 14 of Fig. 8 do not fully corre spond to the projections of the conductors 11. Rather, the pixels 2 retain their outer rectangular or quadratic shape from the state of the art. This means the pixels 2 have continuous edges 15 made from electrically conduct- ing material. Such continuous edge 15 avoids that a pixel 2 is divided into several independent parts which may be on different electrical potentials. The electric field distribution inside the sensor ensures that a charge will even be collected in the case that it was created di- rectly above the void 14.

In general, however, it is desired that the void 14 corresponds to as much of the projection as pos sible, i.e. the void 14 occupies at least e.g. 80%, in particular at least 90%, of an area of the projections. Also it is preferred that many or all of the pixels 2 which are crossed by conductor tracks 11 in the redistri bution layer 10 exhibit such voids 14. This significantly improves the quality of the resulting image.

Alternatively or in addition, it is advanta- geous to apply the concept of the voids to capacitances forming between conductor tracks 11 and input contacts 4 crossed by the conductor tracks. In this case, at least one crossed input contact has a void corresponding to at least a portion of projections of the conductor tracks. Figs. 9 to 12 display further advantageous features of a radiation detector according to the inven tion. The embodiment shown in the cross-section of Fig. 9 through a sensor tile 1 and a redistribution layer 10 is characterized by a low-k material as dielectric material 12 of the redistribution layer 10. By using a low-k mate rial, it is possible to reduce parasitic capacitances 13 as can be seen from the generic formula for the capaci tance of a parallel-plate capacitor above. Thus the embodiment of Fig. 9 may have a thickness of the redistribution layer 10 in the range of 0.1 to 2 pm, e.g. 1 pm, while still reducing parasitic capacitances 13 to an ac ceptable level for imaging purposes.

Fig. 10 shows a cross-section similar to Fig. 9 but with a greater thickness of the redistribution layer 10. The thickness may be in the range of 2 to 10 pm, e.g. 5 pm. Also enlarging the thickness of the re distribution layer 10 reduces parasitic capacitances as can be understood with the above formula for a parallel- plate capacitor, since it enlarges the distance between conductor tracks 11 and crossed pixels 2. Nevertheless, arbitrary increments of the redistribution layer thick ness may yield an enhancement of both the conductor tracks resistance and self-capacitance. Furthermore, the required thickness range may lead to undesired complica tions of the fabrication process. Figs. 11 and 12 show a cross-section of a radiation detector with a substrate 15 according to an embodiment of the invention. Figure 11 shows the assembly of ASICs 5 into the functionalized substrate 15, where figure 12 displays the assembled ASICs 5 inside the func- tionalized substrate 15 together with the bump bonded sensors with redistribution layer 10. In conventional radiation detectors, the signal is transported through wire bonds 7 to the readout electronics 8, see e.g. Figs. 2 and 3, which leads to gaps 9 in the detector active area. According to the embodiment of the invention of Figs. 11 and 12, the ASIC 5 is mounted to a substrate 15, in particular into a pocket of the substrate 15. Further, I/O pads 6 of the ASIC 5 are connected, via a connection 17, to external conductive vias 16 in the substrate 15, which preferably is a dielectric functionalized substrate 15. The connection 17 may e.g. be established by printed mi cro wire, tab bonding or wire bonding. The dimensions of the substrate pockets and/or the vias 16 are optimized in order to minimize the detector gaps 9. In this way, a ra diation detector or a detector module is achieved that is well-suited for imaging, e.g. in medical applications. Fig. 12 shows another advantageous feature: a shield 18 is arranged on the redistribution layer 10 and faces the ASIC 5. The shield 18 faces an area of the ASIC 5 that is not covered by input contacts 4, but preferably faces the I/O pad 6 and/or the via 16 and/or the connec- tion 17 . Thus it shields the conductor tracks 11 from cross talk signals originating in the digital or analog signals in the connection 17 . The shield 18 may be made from a metal layer and preferably be covered by a dielectric layer or coating in direction towards the ASIC 5. Further, the shield 18 is preferably connected to a ground pad of the ASIC 5 or the substrate 15. In differ ent embodiment, the shield 18 is arranged on the ASIC 5 facing the redistribution layer 10. a shield (18) between the redistribution layer ( 10 ) and the at least one ASIC (5), which shield (18) is preferably arranged on the surface of the redis tribution layer ( 10 ) facing the at least one ASIC (5), and preferably facing at least one of an I/O pad (6) of the ASIC (5) or a conductive via ( 16) of an electric in- sulator substrate (15) holding the ASIC (5), and in particular is electrically conducting and is connected to ground .

Figs. 13 to 16 show features of a method of manufacturing a radiation detector according to embodi- ments of the invention. In this context, Figs. 13a to 16a as well as Figs. 17 and 18 show photolithography masks used in the method. In the first step, a sensor tile 1 is provided, i.e. comprising sensor material sensitive to the radiation. Then, metal pixels 2 are defined by photo- lithography and metallization, see Figs. 13a and 13b. The pixels 2 have voids 14 corresponding to at least portions of projections of conductor tracks crossing the pixels as described before. In the next step (Figs. 14a and 14b), a dielectric coating layer 12 is deposited on the sensor tile 1 and the pixels 2. Then, via holes 12a are opened through the dielectric coating layer 12 to every pixel 2. The holes 12a are defined by photolithography and formed by etching.

In the next step (Figs. 15a and 15b), redistribution tracks lib are defined by photolithography and metallization. In the same step, the holes 12a are filled by a conducting material forming vias 11a. The vias 11a and the redistribution tracks lib contribute to the conductor tracks 11 of the redistribution layer 10. Then, the surface of the dielectric coating layer 12 is passivated, e.g. with a thin dielectric layer 12b of e.g. Si02, SU8 or SiNx, and UBM 11c are defined by photolithography and metallization (Fig 16a and 16b). The UBM 11c are adapted to establish an electrical contact to the input contacts 4 of the ASIC 5. The dielectric coating layer 12, the thin dielectric layer 12b and the conductor tracks 11 contribute to the redistribution layer 10.

Figs. 17 and 18 show photolithography masks for vias 11a, redistribution tracks lib and UMB 11c in an outer part and an inner part, respectively, of a sensor tile of a radiation detector as used in an embodiment of the method. Evidently, in the outer part of the sensor 1 (Fig. 17), pixels 2 and corresponding input contacts 4, and thus vias 11a and UBM 11c, are further horizontally offset than in the inner part of the sensor tile 1 (Fig. 19). This means that redistribution tracks lib will be longer in the outer part than in the inner part. In other words, there is maximum redistribution at the sensor edges, whereas there is minimum sensor redistribution in the sensor middle.

In general, it is advantageous that conductor tracks 11, and in particular redistribution tracks lib, are routed such that their projections cover an as-small- as-possible area of the pixels 2. Assuming a constant de sired area of the redistribution tracks lib, this amounts to routing the redistribution tracks lib along gaps 21 between the pixels 2 as can be seen in Fig. 17. This again reduces parasitic capacitances between different pixels or input contacts, respectively.

While there are shown and described presently preferred embodiments of the invention, it is to be dis tinctly understood that the invention is not limited thereto but may be otherwise variously embodied and prac ticed within the scope of the following claims.