RADIO COMMUNICATION APPARATUS AND INTERLEAVING METHOD

Technical Field [0001] The present invention relates to a radio communication apparatus and interleaving method.

Background Art

[0002] In recent years, multimedia communication such as data communication and video streaming has continued to increase in popularity. Therefore, data sizes are expected to increase even more in the future, and growing demands for higher data rates for mobile communication services are also anticipated. [0003] Thus, a fourth-generation mobile communication system called IMT-Advanced has been studied by the ITU-R (International Telecommunication Union Radio Communication Sector), and an LDPC (Low-Density Parity-Check) code is one of error correcting codes for implementing a downlink speed of up to 1 Gbps. Use of an LDPC code as an error correcting code enables decoding processing to be parallelized, allowing decoding processing to be speeded up compared with the use of a turbo code that requires repeated serial execution of decoding processing.

[0004] LDPC encoding is performed using a parity check matrix containing a large number of Os and a small number

of Is. A transmitting-side radio communication apparatus encodes a transmission bit sequence using a parity check matrix, and obtains an LDPC codeword comprising systematic bits and parity bits. A receiving- s ide radio communication apparatus decodes received data by iteratively executing passing of the likelihood of individual bits in the parity check matrix row direction and the parity check matrix column direction, and obtains a received bit sequence. Here, the number of Is contained in each column in a parity check matrix is called the column degree, and the number of Is contained in each row in a parity check matrix is called the row degree. A parity check matrix can be represented by a Tanner graph, which is a two-part graph comprising rows and columns. In a Tanner graph , each row of a parity check matrix is called a check node, and each column of a parity check matrix is called a variable node. Variable nodes and check nodes of a Tanner graph are connected in accordance with the arrangement of Is in the parity check matrix, and a receiving- side radio communication apparatus decodes receive data by iteratively executing passing of likelihoods between connected nodes, and obtains a received bit sequence. [0005] A method of setting a coding rate higher than the LDPC code coding rate (hereinafter referred to as "mother coding rate") is "puncturing." Puncturing is a technology whereby specific bits of a codeword are thinned

out. This enables a coding rate higher than the mother coding rate to be set.

[0006] Here, an E ² RC (Efficiently Encodable Rate Compatible) -LDPC code is available as an LDPC code which takes into consideration minimization of error rate performance degradation due to puncturing (see Non- Patent Document 1) . The E ² RC-LDPC code is comprised of a sub matrix corresponding to systematic bits and a sub matrix corresponding to parity bits. Furthermore, the sub matrix corresponding to parity bits is designed using a definition called "SR (Step-Recoverable)." SR is expressed by a tree structure where variable nodes and check nodes are connected in accordance with the arrangement of Is in the sub matrix corresponding to parity bits. According to SR, a variable node is expressed as an SR node based on the number of steps (order) from the end of the tree structure. For example, a variable node of order n is expressed as an "n-SR node." According to an E ² RC-LDPC code, a parity bit corresponding to an SR node of higher order has a stronger relationship with parity bits corresponding to other SR nodes. Therefore, the E ² RC-LDPC code can minimize degradation of the error rate performances by puncturing in order from a parity bit corresponding to an SR node of lower order. According to the E ² RC-LDPC code, in a sub matrix corresponding to parity bits, a parity bit corresponding to a column closer to a column corresponding to a systematic bit becomes

an SR node of lower order and has higher priority ranking of puncturing .

[0007] HARQ (Hybrid ARQ) combines ARQ (Automatic Repeat reQuest) and error correcting coding. With HARQ, a receiving-side radio communication apparatus feeds back an ACK (Acknowledgment) signal as a response signal to the transmitting- side radio communication apparatus if there are no errors in receive data, and feeds back a NACK (Negative Acknowledgment) signal if there is an error. Also, the receiving-side radio communication apparatus combines retransmitted data from the transmitting-side radio communication apparatus with received data in the past, and decodes the combined data. By this means SINR and coding gain improvements are achieved, and received data can be decoded with fewer retransmissions than in the case of ordinary ARQ.

[0008] Furthermore, by changing a puncturing position of a codeword for every retransmission, HARQ forms transmissiondata (e.g., RV: redundancy version) of each transmission. Here, the use of a circular buffer i s under study to facilitate the configuration of transmission data of each transmission (see Non-Patent Document 2) . More specifically, the transmitting- side radio communication apparatus consecutively reads out transmission data that satisfies a desired coding rate (or desired code length) from the circular buffer in which the codeword is stored by changing the reading out start

position for every retransmission. Thus, by adopting a circular structured buffer (circular buffer) as the buffer into which a codeword is written, it is possible to define transmission data having a desired coding rate or desired code length in a simple manner and reduce the degree of complexity when the buffer is provided.

Non-Patent Document 1: J. Kim, et al . "Design of Efficiently-Encodable Rate-Compatible Irregular LDPC Codes", ICC2006 pp.1131-1136

Non-Patent Document 2: Rl-072604, Ericsson, et al . "Way forward on HARQ rate matching for LTE", 3GPP TSG RAN WGl #49, Kobe, Japan, May 7-11, 2007

Disclosure of Invention

Problems to be Solved by the Invention

[0009] However, when the LDPC codeword is stored in the circular buffer, a parity bit which is not transmitted as t ransmi ss ion data , thatis, a parity bit to be punctured may be interposed between bits of the LDPC codeword forming the transmi s s ion data . Therefore, the transmitting- side radio communication apparatus may be unable to consecutively read out the LDPC codeword from the circular buffer and may read out the LDPC codeword intermittently. [0010] For example, it is assumed that a 12-bit LDPC codeword (mother coding rate R _m =l/3) comprised of

systematic bits Sl to S4 and parity bits Pl to P8 is stored in the circular buffer. Here, when 10-bit transmission data is transmitted (in the case of coding rate R=2/5), the transmitting-side radio communication apparatus punctures two parity bits out of 12 bits of the LDPC codeword. That is, parity bits Pl and P2 with higher puncturing priority ranking are punctured. Therefore, the transmitting-side radio communication apparatus reads out systematic bits Sl to S 4 from the circular buffer, and sequentially skips parity bits Pl and P2 and reads out parity bits P3 to P8 from the circular buffer. In this way, when the LDPC codeword is stored in the circular buffer, the transmitting-side radio communication apparatus may be required to intermittently read out the LDPC codeword from the circular buffer. When the LDPC codeword is read out from the circular buffer intermittently, the transmitt ing- side radio communication apparatus needs to manage not only the reading start address but also addresses showing the positions of parity bits to be skipped. Therefore, reading processing at the circular buffer becomes complicated .

[0011] Furthermore, HARQ involves proces sing of reading out LDPC codewords corresponding to the number of retransmissions from the circular buffer. Therefore, HARQ involves processing of skipping parity bits to be punctured a plurality of times, which further complicates

the reading processing in the circular buffer. [0012] Consequently, even when parity bit s are punctured, a technique of consecutively reading out LDPC codewords from the circular buffer is strongly demanded. [0013] 11 i s therefore an obj ect of the present invent ion to provide a radio communication apparatus and interleaving method capable of consecutively reading out LDPC codewords from a circular buffer.

Means for Solving the Problem

[0014] A radio communication apparatus of the present invention employs a configuration having: an encoding section that performs LDPC coding on a transmission bit sequence using a parity check matrix to obtain a plurality of systematic bits and a plurality of parity bits; an interleaving section that sorts the plurality of parity bits according to a puncturing order; and a circular buffer that stores the plurality of systematic bits and the plurality of sorted parity bits.

Advantageous Effect of the Invention

[0015] According to the present invent ion , itispossible to read out LDPC codewords from a circular buffer consecutively.

Brief Description of Drawings [0016]

FIG.l is a block diagram showing a transmi tting-side radio communication apparatus according to Embodiment 1 of the present invention;

FIG.2 shows a parity check matrix according to Embodiment 1 of the present invention;

FIG.3 shows a Tanner graph of a sub matrix corresponding to parity bits according to Embodiment 1 of the present invention;

FIG.4 shows a tree structure of the sub matrix corresponding to parity bits according to Embodiment 1 of the present invention;

FIG.5 shows storing processing according to Embodiment 1 of the present invention;

FIG.6 shows reading processing according to Embodiment 1 of the present invention;

FIG.7 is a block diagram showing a configuration of a receiving-side radio communication apparatus according to Embodiment 1 of the present invention;

FIG.8 shows received data generation processing according to Embodiment 1 of the present invention (when transmission data is received for the first time);

FIG.9 shows received data generation processing according to Embodiment 1 of the present invention (when transmission data is received for the second time); FIG.10 shows column conversion of a parity check matrix according to Embodiment 2 of the present invention;

FIG.11 shows storing processing and reading

processing according to Embodiment 2 of the present invention;

FIG.12 shows column conversion of a parity check matrix according to Embodiment 3 of the present invention; and

FIG.13 shows storing processing and reading processing according to Embodiment 3 of the present invent ion.

Best Mode for Carrying Out the Invention

[0017] Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the following description, each column of a parity check matrix or a part corresponding to each variable node of a Tanner graph will be referred to as a "bit position." [0018] (Embodiment 1)

In the present embodiment, a plurality of parity bits are sorted according to orders of SR nodes corresponding to the parity bits.

[0019] FIG.l shows the configuration of transmitting- s ide radio communication apparatus 100 according to the present embodiment. [0020] In transmitting-side radio communication apparatus 100, a transmission bit sequence is input to CRC (Cyclic Redundancy Check) section 101. CRC section 101 performs error detecting encoding on the transmission

bit sequence using CRC and outputs the transmission bit sequence to which CRC parity bits are added, to encoding section 102.

[0021] Encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using a parity check matrix to obtain an LDPC codeword comprised of a plurality of systematic bits and parity bits. Here, an E ² RC-LDPC code is used as the LDPC code. Furthermore, encoding section 102 outputs the LDPC codeword to interleaver 103.

[0022] Interleaver 103 sorts the LDPC codeword inputted from encoding section 102 according to the puncturing order. More specifically, interleaver 103 sorts a plurality of parity bits according to orders of SR nodes corresponding to the parity bits. Furthermore, interleaver 103 sorts the plurality of systematic bits in reverse order and outputs the sorted LDPC codeword to transmission circular buffer 104. The sorting processing at interleaver 103 will be described later in detail.

[0023] Transmission circular buffer 104 stores the LDPC codeword inputted from interleaver 103 in a memory of a cyclic reading type buffer. Furthermore, transmission circular buffer 104 reads out the LDPC codeword from the memory according to a coding rate of the read LDPC codeword and an RV parameter showing the reading start position inputted from control section 112 , and outputs the read

LDPC codeword to modulation section 105. The storing processing and reading processing at transmission circular buffer 104 will be described later in detail. [0024] Modulation section 105 modulates the LDPC codeword inputted from transmission circular buffer 104 to generate data symbols and outputs the data symbols to multiplexing section 106.

[0025] Multiplexing section 106 multiplexes the data symbols, a pilot signal and a control signal inputted from control section 112 and outputs the generated multiplexed signal to radio transmitting section 107.

[0026] Radio transmitting section 107 performs transmission processing such as D/A conversion, ampIi fi cat ion and up-conversion on the multiplexed signal and transmits the signal from antenna 108 to a receiving-side radio communication apparatus. [0027] On the other hand, radio receiving section 109 receives a control signal transmitted from the receiving- side radio communication apparatus through antenna 108, performs reception processing such as down-conversion and A/D conversion on the control signal and outputs the control signal to demodulation section 110. This control signal includes a CQI (Channel Quality Indicator) and response signal generated by the receiving-side radio communication apparatus.

[0028] Demodulation section 110 demodulates the control signal and outputs the demodulated signal to decoding

s e c t i on 1 1 1 .

[0029] Decoding section 111 decodes the control signal and outputs the CQI and response signal included in the control signal to control section 112. [0030] Control section 112 controls the systematic bit length of the read LDPC codeword, read coding rate and RV parameter according to the CQI. Control section 112 then determines the systematic bit length, coding rate and RV parameter corresponding to the inputted CQI and outputs control information showing the determined systematic bit length, coding rate and RV parameter to transmission circular buffer 104 and multiplexing section 106. Control section 112 determines a lower coding rate for a CQI corresponding to channel quality with a lower inputted CQI . Furthermore, control section 112 controls retransmission of transmission data based on the response signal inputted from decoding section 111. [0031] Next, the sorting processing at interleaver 103 and storing processing at transmission circular buffer 104 will be described in detail.

[0032] FIG.2 shows an 8-rows * 12-columns parity check mat rix as an example . Asshownhere, a pari ty check matrix is represented by a matrix of M rows _* N columns, and comprises Os and Is. In the present embodiment, for ease of description, out of sub matrix Hi corresponding to systematic bits and sub matrix H ₂ corresponding to parity bits forming the parity check matrix, only sub matrix

H ₂ corresponding to parity bits will be described, and decription of sub matrix Hi corresponding to systematic bits will be omitted.

[0033] Each column of the parity checkmatrix correspond to a coded bit of the LDPC codeword. That is, when LDPC encoding is performed using the parity check matrix shown in FIG.2, a 12-bit LDPC codeword (systematic bits Sl to S4 and parity bits Pl to P8) is generated. [0034] Further, in sub matrix H ₂ of the parity check matrix shown in FIG.2, the column degree of the fifth column (parity bit Pl) is the number of Is on the fifth column, that is, two, and the column degree of the sixth column (parity bit P2) is the number of Is on the sixth column, that is, two. The same will apply to the seventh column to twelfth column (parity bits P3 to P8) .

[0035] Therefore, in the 12-bit LDPC codeword ,-the column degree of the fifth bit (parity bit Pl) is two, and the column degree of the sixth bit (parity bit P2) is two. The same will apply to the seventh to twelfth columns (parity bits P3 to P8).

[0036] Likewise, in sub matrix H ₂ of the parity check matrix shown in FIG.2, the row degree of the first row is the number of Is, that is, one, and the row degree of the second row is the number of Is, that is, one. The same will apply to the third to eighth rows.

[0037] Furthermore, the parity check matrix shown in FIG.2 can be expressed by a Tanner graph comprised of

rows and columns of the parity check matrix. [0038] FIG.3 shows a Tanner graph corresponding to sub matrix H ₂ of the parity check matrix in FIG.2. The Tanner graph comprises check nodes corresponding to the rows of the parity check matrix and variable nodes corresponding to the columns of the parity check matrix. That is, the Tanner graph corresponding to an 8-rows x 8-columns sub matrix H ₂ is a two-part graph comprising eight check nodes and eight variable nodes. [0039] Furthermore, each variable node of the Tanner graph corresponds to each coded bit of the LDPC codeword. [0040] Here, variable nodes and check nodes of the Tanner graph are connected in accordance with the arrangement of Is in the parity check matrix. [0041] A concrete description will be now given based on variable nodes. Variable node Pl of the Tanner graph shown in FIG.3 corresponds to the fifth column (N=5) of the parity checkmatrix shown in FIG.2. The column degree of the fifth column of the parity check matrix is two, and the rows in which a 1 is located in the fifth column are the first row and fifth row. Therefore, there are two connections at variable node Pl ; check node 1 and check node 5. Likewise, variable node P2 of the Tanner graph corresponds to the sixth column (N=β) of the parity check matrix. The column degree of the sixth column of the parity check matrix is two, and the rows in which a 1 is located in the sixth column are the second row

and sixth row. Therefore, there are two connections at variable node P2; check node 2 and check node 6. The same will apply to variable node P3 to variable node P8. [0042] Similarly, to give a concrete description based on check nodes. Check node 1 of the Tanner graph shown in FIG.3 corresponds to the first row (M=I) of the parity check matrix shown in FIG.2. The row degree of the first row of sub matrix H ₂ of the parity check matrix is one, and the column in which a 1 is located in the first row is the first column. Therefore, there is one connection at check node 1 ; variable node Pl. Likewise, check node 2 of the Tanner graph corresponds to the second row (M=2) of the parity check matrix. The row degree of the second row of sub matrix H ₂ of the parity check matrix is one, and the column in which a 1 is located in the second row is the second column. Therefore, there is one connection at check node 2; variable node P2. The same applies to check node 3 to check node 8. [0043] In this way, in a Tanner graph, variable nodes and check nodes are connected in accordance with the arrangement of Is in a parity check matrix. That is, the number of check nodes connected to each variable node in a Tanner graph is equal to the column degree of each column in a parity check matrix. Also, check nodes to which each variable node is connected in a Tanner graph are check nodes corresponding to rows in which a 1 is located in each column of a parity check matrix.

Similarly, the number of variable nodes connected to each check node in a Tanner graph is equal to the row degree of each row in a parity check matrix, and variable nodes to which each check node is connected in a Tanner graph are variable nodes corresponding to columns in which a 1 is located in each row of a parity check matrix. [0044] Furthermore, the Tanner graph corresponding to sub matrix H ₂ shown in FIG.3 can be expressed by a tree structure . [0045] FIG.4 shows a tree structure corresponding to the Tanner graph shown in FIG.3. Although the tree structure is different from the Tanner graph in notation, they are equivalent to each other. That is, the tree structure shown in FIG.4 is comprised of check nodes corresponding to rows of the parity check matrix and variable nodes corresponding to columns of the parity check matrix in the same way as the Tanner graph shown in FIG.3. [0046] Furthermore, in the tree structure, the variable node corresponding to each parity bit is defined as an SR node.

[0047] As shown in FIG.4, out of parity bits Pl to P8, paritybits Pl to P4 located at the end of the tree structure are defined as 1-SR nodes. Furthermore, parity bit P5 connected to parity bit Pl corresponding to the 1-SR node through check node 5 i s de fined as a 2-SR node . Inaddition, parity bit P6 connected to parity bit P2 corresponding to the 1-SR node through check node 6 is defined as a

2-SR node. Likewise, parity bit P7 connected to parity- bit P5 corresponding to the 2-SR node through check node 7 is defined as a 3-SR node, and parity bit P8 connected to parity bit P7 corresponding to the 3-SR node through check node 8 is defined as a 4-SR node.

[0048] According to an E ² RC-LDPC code, error correcting decoding is performed in order from a parity bit corresponding to an SR node of lower order. For example, when error- correcting decoding is performed on parity bit P6 corresponding to the 2-SR node shown in FIG.4, parity bit P2 corresponding to the 1-SR node is subjected to error correcting decoding through check node 2 (first step) . Next, parity bit P6 corresponding to the 2-SR node is subjected to error correcting decoding through check node 6 (second step) . The same applies to parity bits corresponding to other SR nodes. That is, according to the E ² RC-LDPC code, a parity bit corresponding to an SR node of higher order has a higher degree of relativity with other parity bits. In other words, a parity bit corresponding to a lower order SR node has a lower degree of relativity with other parity bits.

[0049] That is, according to the E ² RC-LDPC code, out of SR nodes of the tree structure, a parity bit corresponding to a lower order SR node has less degradation of the error rate performances due to puncturing. Therefore, when an LDPC codeword is punctured according to the E ² RC-LDPC code, puncturing is performed in order from a parity bit

corresponding to a lower order SR node.

[0050] Here, transmission circular buffer 104 cyclically reads out an LDPC codeword sequentially from the head of a buffer as transmission data to be transmitted to a receiving-side radio communication apparatus. That is, transmission circular buffer 104 can hardly transmit an LDPC codeword stored in the tail end of the buffer with fewer transmissions. In other words, transmission circular buffer 104 can easily puncture an LDPC codeword stored in the tail end of the buffer. Therefore, when an E ² RC-LDPC codeword is stored in transmission circular buffer 104, it is preferable to store in the tail end of the buffer parity bits with less degradation of the error rate performances due to puncturing, that is, parity bits corresponding to lower order SR nodes.

[0051] Therefore, interleaver 103 sorts a plurality of parity bits according to orders of SR nodes corresponding to parity bits. [0052] This will be described below more specifically. In the following descriptions, it is assumed that the transmission bit sequence length is 4 bits, LDPC codeword length N is twelve bits and mother coding rate R _m is 1/3. Therefore, when LDPC coding is performed on a 4-bit transmission bit sequence using the parity check matrix shown in FIG.2, an LDPC codeword with N= 12 bits comprised of four systematic bits and eight parity bits is obtained. Furthermore, it is assumed that systematic bit length

K determined by control section 112 is 4 bits and coding rate R is 1/2.

[0053] First, int erleaver 103 sort s a plurality of parity bits of an LDPC codeword such that parity bits corresponding to SR nodes of lower order are arranged closer to the tail end. That is, interleaver 103 sorts parity bits in descending order of SR node order. More specifically, interleaver 103 compares orders of corresponding SR nodes between parity bits Pl to P8 (fifth column to twelfth column of the parity check matrix shown in FIG.2) of the tree structure shown in FIG.4. That is, interleaver 103 makes comparisons between order 1 of SR node (1-SR) corresponding to parity bit Pl, order 1 of SR node (1-SR) corresponding to parity bit P2, order 1 of SR node (1-SR) corresponding to parity bit P3, order

1 of SR node (1-SR) corresponding to parity bit P4, order

2 of SR node (2-SR) corresponding to parity bit P5, order

2 of SR node (2-SR) corresponding to parity bit P6, order

3 of SR node (3-SR) corresponding to parity bit P7 and order 4 of SR node (4-SR) corresponding to parity bit

P8.

[0054] Therefore, the order of parity bit s cor responding to SR nodes of higher order in parity bits Pl to P8 (fifth column to twelfth column of the parity check matrix shown in FIG.2) is: variable node P8 (twelfth column) is first, variable node P7 (eleventh column) is second, variable node P6 (tenth column) and variable node 5 (ninth column)

are third, and variable nodes P4 to Pl (eighth column to fifth column) are fifth. In other words, the puncturing order in parity bits Pl to P8 (fifth column to twelfth column) , that is, puncturing priority ranking is: parity bits Pl to P4 (fifth column to eighth column) are first, parity bit P5 (ninth column) and parity bit P6 (tenth column) are fifth, parity bit P7 (eleventh column) is seventh and parity bit P8 (twelfth column) i s eighth . [0055] Furthermore, interleaver 103 sorts systematic bits of an LDPC codeword in reverse order. More specifically, as shown in FIG.5, interleaver 103 sorts the order of systematic bits Sl to S4 (first column to fourth column) to systematic bits S4 to Sl (fourth column to first column) .

[0056] In this way, as shown in FIG.5, interleaver 103 sorts the order of the 12-bit LDPC codeword comprised of four systematic bits Sl to S4 and eight parity bits Pl to P8 to systematic bits S4 to Sl and parity bits P8 to Pl. As shown in FIG.5, transmission circular buffer 104 stores the LDPC codeword sorted in order of systematic bits S4 to Sl and parity bits P8 to Pl. Further, as shown in FIG.5, in transmission circular buffer 104, parity bits stored closer to the tail end of the buffer have higher puncturing priority ranking.

[0057] Next, the reading processing at transmission circular buffer 104 will be described below in detail.

Here, it is assumed that systematic bit length K determined by control section 112 at the first transmission (initial transmission) and second transmission (first retransmission) is 4 bits and coding rate R is 1/2. Therefore, the first transmission data (initial transmission data) and the second transmission data

(first retransmission data) are comprised of four systematic bits and four parity bits.

[0058] As shown in FIG.6, transmission circular buffer 104 reads out an 8-bit LDPC codeword in order from systematic bit S4 which is the initial bit of the buffer as the first transmission data (initial transmission data) at the first transmission (initial transmission) . More specifically, transmission circular buffer 104 outputs the 8-bit LDPC codeword comprised of four systematic bits S4 to Sl and four parity bits P8 to P5, to modulation sect ion 105. Furthermore, as shown in FIG .6 , at the second transmission (first retransmission), transmission circular buffer 104 reads out the 8-bit LDPC codeword in order from parity bit P4 following parity bit P5, which is the last bit of the first transmission data (initial transmission data) as the second transmission data (first retransmission data) . More specifically, transmission circular buffer 104 outputs the 8-bit LDPC codeword comprised of four parity bits P4 to Pl and four systematic bits S4 to Sl, to modulation section 105.

[0059] Here, as shown in FIG.6, the bits not transmitted at the first transmission (initial transmission) are four parity bits Pl to P4. That is, four parity bits Pl to P4 are punctured at the first transmission (initial transmission) . Likewise, as shown in FIG.6, the bits not transmitted at the second transmission (first retransmission) are four parity bits P5 to P8. That is, four parity bits P5 to P8 are punctured at the second transmission (first retransmission) . That is, transmission circular buffer 104 punctures in order from parity bits Pl to P8, that is, in order from a parity bit having the highest puncturing priority ranking, at the first transmission (initial transmission) and the second transmission (first retransmission). [0060] In this way, as shown in FIG.6, transmission circular buffer 104 can generate an LDPC codeword with sequentially punctured parity bits in order from a parity bit with higher puncturing priority ranking by only cyclically reading out eight consecutive bits from the head of the buffer at the first transmission (initial transmission) . Likewise, as shown in FIG.6, transmission circular buffer 104 can generate an LDPC codeword with parity bits punctured according to puncturing priority ranking by only cyclically reading out eight consecutive bits in order from the bit following the last bit of the first transmission data (initial transmission data) at the second transmission (first

retransmission) .

[0061] Furthermore, transmitting-side radio communication apparatus 100 sorts a plurality of parity bits such that a parity bit having higher puncturing priority ranking is stored in the tail end of transmission circular buffer 104. Therefore, according to the E ² RC-LDPC code, parity bits located closer to systematic bits have higher puncturing priority ranking, and so parity bits are sorted in reverse order. Furthermore, transmitting-side radio communication apparatus 100 also sorts a plurality of systematic bits in reverse order. By this means, although the bits of an LDPC codeword are sorted in reverse order, it is possible to store the bits in transmission circular buffer 104 while keeping the order of Sl to S4 and Pl to P8. As described above, the sorting rule of the entire LDPC codeword is the same, so that it is possible to perform sorting processing without distinguishing between systematic bits and parity bits in the receiving- side radio communication apparatus . [0062] Next, the receiving-side radio communication apparatus according to the present embodiment will be described. FIG.7 shows the configuration of receiving- side radio communication apparatus 200 according to this embodiment. [0063] In receiving-side radio communication apparatus 200, radio receiving section 202 receives a multiplexed signal transmitted from transmitting- side radio

communication apparatus 100 (FIG.l) through antenna 201 , performs reception processing such as down-conversion and A/D conversion on the received signal and outputs the signal subjected to reception processing to separation section 203. This received signal includes a control signal specifying data symbols, pilot signal, and systematic bit length, coding rate and RV parameter determined by transmitting-side radio communication apparatus 100. [0064] Separation section 203 separates the received signal into the data symbols, the pilot signal and the control signal. Further, separation section 203 outputs the data symbols to demodulation section 204, the pilot signal to channel quality estimation section 209 and the control signal to reception circular buffer 205 and deinterleaver 206.

[0065] Demodulation section 204 demodulates the data symbols to obtain received data comprised of a plurality of bits and outputs the received data to reception circular buffer 205.

[0066] Reception circular buffer 205 stores likelihood information of a plurality of bits forming received data inputted from demodulation section 204 in a memory of a cyclic reading type buffer similar to transmission circular buffer 104 (shown in FIG.l) in accordance with the coding rate and RV parameter specified by control information inputted from separation section 203. Here,

when the first transmission data (initial transmission data) is received, reception circular buffer 205 pads bit positions in which no received data has been stored with padding bits where an LLR (Log-Likelihood Ratio) is zero. Further, reception circular buffer 205 reads out likelihood information of all the bit positions in which received data has been stored and outputs the read likelihood information to deinterleaver 206. Furthermore, when the second and subsequent transmission data (retransmission data) are received, reception circular buffer 205 specifies received bits forming the received data based on the control information (i.e., coding rate and RV parameter) inputted from separation section 103, combines the received data with the saved data, saves the obtained data and outputs the data to deinterleaver 206. Furthermore, when an ACK signal is received from error detecting section 208, that is, when the received data includes no error, reception circular buffer 205 discards the saved received data. Storing processing and reading processing at reception circular buffer 205 will be described later in detail. [0067] Deinterleaver 206 sorts likelihood information inputted from reception circular buffer 205 according to the puncturing order. More specifically, deinterleaver 206 sorts a plurality of parity bits according to orders of SR nodes corresponding to parity bits in the same way as interleaver 103 (shown in FIG.l) .

Furthermore, deinterleaver 206 sorts likelihood information of a plurality of systematic bits in reverse order, and outputs the likelihood information of the sorted plurality of bits to decoding section 201. The sorting processing at deinterleaver 206 will be described later in detail .

[0068] Decoding section 207 performs LDPC decoding on the likelihood information inputted from deinterleaver 206 using the same parity check matrix as the parity check matrix ( shown in FIG .2 ) used by encoding section 102 (shown in FIG.l) to obtain a decoded bit sequence. Decoding section 207 outputs the decoded bit sequence to error detecting section 208. [0069] Error detecting section 208 performs error detecting on the decoded bit sequence inputted from decoding section 207. When the error detecting result shows that decoded bits contain error, error detecting section 208 generates a NACK signal as a response signal and outputs the NACK signal to reception circular buffer 205 and control signal generation section 210, and, when the decoded bits contain no errors, generates an ACK signal as a response signal and outputs the ACK signal to reception circular buffer 205 and control signal generation section 210. Furthermore, when the decoded bits contain no errors , error detecting section 208 outputs the decoded bit sequence as a received bit sequence. [0070] On the other hand, channel quality estimation

section 209 estimates channel quality using a pilot signal inputted from separation section 203. Here, channel quality estimation section 209 estimates an SINR (Signal to Interference and Noise Ratio) of the pilot signal as channel quality and outputs the estimated SINR to control signal generation section 210.

[0071] Control signal generation section 210 generates a CQI corresponding to the SINR inputted from channel quality estimation section 209. Further, control signal generation section 210 outputs to encoding section 211 a control signal including the generated CQI and the response signal inputted from error detecting section 208. [0072] Encoding section 211 encodes on the control signal and outputs the encoded control signal to modulation section 212.

[0073] Modulation section 212 modulates the control signal and outputs the modulated control signal to radio transmitting section 213. [0074] Radio transmitting section 213 performs transmission processing such as D/A conversion, amplification and up-conversion on the control signal and transmits the control signal from antenna 201 to transmitting- side radio communication apparatus 100 (shown in FIG.1 ) .

[0075] Storing processing and reading processing at reception circular buffer 205 and sorting processing at

deinterleaver 206 will be described in detail. [0076] Here, it is assumed that mother coding rate R _n , is 1/3, systematic bit length K specified by the control signal inputted from separation section 203 is four and coding rate R is 1/2. Therefore, reception circular buffer 205 identifies that thebuffer size is 12 (Kx ( 1/R _m ) ) bits and the received data length is 8 (Kx (1/R)) bits. Furthermore, it is assumed that the start position of the received data in the circular buffer specified by an RV parameter at which the first transmission data (initial transmission data) is received is the first position of the buffer and the start position of the received data in the circular buffer specified by the RV parameter at which the second transmission data (first retransmission data) is received is the ninth position of the buffer .

[0077] As shown in FIG.8, the start position of the received data specified by the RV parameter at which the fi r s t t ransmi s s ion dat a ( initial transmi s s ion da t a ) shown in FIG .6 is received is the first position, and so reception circular buffer 205 stores received data Rl to R8 (S4 to Sl, P8 to P5) sequentially from the start bit position to the eighth bit position of the buffer. Furthermore, reception circular buffer 205 pads the bit positions other than the bit positions at which received data Rl to R8 have been stored with padding bits Pad where LLR= O. That is, as shown in FIG.8, reception circular buffer 205 pads

the ninth to twelfth bit positions of the buffer with 4 padding bits Pad. In this way, as shown in FIG.8, 12 bits of Rl to R8, Pad, Pad, Pad, Pad, that is, S4, S3, S2, Sl, P8, P7, P6, P5, Pad, Pad, Pad, Pad are stored in reception circular buffer 205.

[0078] As shown in FIG.8, when the first transmission data (initial transmission data) is received, the received data read out from reception circular buffer 205 are S4, S3, S2, Sl, P8, P7, P6, P5, Pad, Pad, Pad, Pad.

[0079] Next, systematic bit length K is four, and so deinterleaver 206 sorts the 12 -bit received data inputted from reception circular buffer 205 in reverse order from the fourth bit of the received data. More specifically, as shown in FIG.8, deinterleaver 206 sorts systematic bit Sl (which is the first position in the sorting order) located at the fourth position of the buffer to parity bit P8 (which is the twelfth position in the sorting order) located at the fifth position in reverse order. By this means, it is possible to obtain 12-bit data of the same data length as that of the LDPC codeword generated by t ransmi t t ing-s ide radio communication apparatus 100. Therefore, as shown in FIG.8, when the first transmission data (initial transmission data) is received, this 12-bit data comprised of Sl, S2, S3, S4, Pad, Pad, Pad, Pad, P5, P6, P7, P8 is inputted to decoding section 207. [0080] Next, when the second transmission data (first

retransmission data) is received, as shown in FIG.9, the received data length specified by the control information is eight bits and the start position of the received data specified by the RV parameter is the ninth position, so that reception circular buffer 205 stores received data Rl to R8 (P4 to Pl, S4 to Sl) sequentially from the ninth bit pos it ion of the buffer . More specifically, reception circular buffer 205 stores Rl to R4 in the ninth to twelfth bit positions of the buffer, respectively, and stores R5 to R8 in the first to fourth bit positions of the buffer, respectively. As shown in FIG.9, reception circular buffer 205 combines R5 to R8 stored in the first to fourth bit positions of the buffer with S4 to Sl already saved at the first to fourth bit positions of the buffer. In this way, as shown in FIG.9, 12 bits of S4, S3, S2, Sl, P8, P7, Pβ, P5, P4, P3, P2, Pl are stored in reception circular buffer 205.

[0081] Therefore, as shown in FIG.9, when the second transmission data ( first retransmi ssion data ) isreceived, the received data read out from reception circular buffer 205 is S4, S3, S2, Sl, P8, P7, Pβ, P5, P4, P3, P2, Pl. [0082] Next, systematic bit length K is four, and so deinter leaver 206 sorts the 12-bit received data inputted from reception circular buffer 205 in reverse order from the fourth bit of the received data in the same way as when the first transmission data (initial transmission data) is received. Therefore, when the second

transmission data ( first retransmission data ) is received, 12-bit data comprised of Sl, S2, S3, S4, Pl, P2, P3, P4, P5, Pβ, P7, P8 is inputted to decoding section 207. [0083] As described above, according to the present embodiment, a plurality of parity bits are sorted according to orders of SR nodes. By this means, the transmitting-side radio communication apparatus stores parity bits with higher puncturing priority ranking in positions closer to the tail end of the transmission circular buffer. That is, when an LDPC codeword is retransmitted, the LDPC codeword is punctured in order from parity bits with higher puncturing priority ranking. In other words, even when an LDPC codeword is read out from the transmission circular buffer by the number of retransmissions, it is possible to consecutively read out the LDPC codeword in ascending order of puncturing priority ranking without intermittently reading out the LDPC codeword. Therefore, according to the present embodiment, it is possible to consecutively read out the LDPC codeword from the transmission circular buffer and easily define transmission data at every transmission by only cyclically reading out the LDPC codeword from the transmission circular buffer. [0084] Furthermore, according to the present embodiment , the transmitt ing-side radio communication apparatus sorts a plurality of systematic bits in reverse order. This makes rules for sorting of systematic bits and parity

bits, that is, the entire LDPC codeword, the same. That is, although the arrangement order of each bit of the LDPC codeword is reversed, the order of mutually neighboring bits becomes the same before and after sorting. By this means, the receiving-side radio communication apparatus identifies the start bit of systematic bits and sorts bits in reverse order from the start bit, so that it is possible to obtain the LDPC codeword generated by the transmitting-side radio communication apparatus. Thatis, the receiving-side radio communication apparatus can sort without distinguishing between systematic bits and parity bits of the received data stored in the reception circular buffer. [0085] (Embodiment 2) According to the present embodiment, in a parity check matrix, column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits according to likelihoods of including errors in systematic bits. [0086] While a case has been described with Embodiment 1 where a read coding rate is higher than a mother coding rate, a case will be taken into consideration with the present embodiment where the read coding rate is lower than the mother coding rate. One of methods of setting a coding rate lower than the mother coding rate is repetition. Repetition is a technique of generating a plurality of identical bits by replicating (repeating)

a specific bit of an LDPC codeword. By this means, it is possible to set a coding rate lower than the mother coding rate. Furthermore, the receiving side can obtain a diversity effect by bit-combining those identical bits. [0087] Furthermore, when an LDPC codeword is repeated, a circular buffer cyclically reads out bits in order from a systematic bit stored in the head of the circular buffer as the repetition bit. [0088] Here, the receiving-side radio communication apparatus transfers likelihoods between variable nodes through check nodes and decodes received data by iteratively updating the likelihood of each variable node, By this means, variable nodes connected to more check nodes, that is, variable nodes having larger column degrees have a larger number of likelihoods received from checknodes. That is, when the column degrees of variable nodes become larger, the effect of updating likelihood becomes larger, so that the error rate performances improve. In other words, when the column degrees of variable nodes become smaller, the effect of updating likelihood becomes smaller, and consequently the error rate performances degrade. Therefore, when variable nodes are repeated, it is preferable to repeat variable nodes which have smaller column degrees and which are likely to include errors preferentially to complement and improve likelihoods . Thatis, when the column degrees of variable nodes become smaller, the effect of improving

likelihoods becomes larger through repetition. [0089] With the present embodiment, column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits in a parity check matrix according to column degrees of systematic bits.

[0090] Encoding section 102 (shown in FIG.l) of transmitting- side radio communication apparatus 100 according to the present embodiment performs column conversion on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix according to column degrees of systematic bits. Further, encoding section 102 performs LDPC coding on a transmission bit sequence inputted from CRC section 101 using the parity check matrix subjected to column conversion .

[0091] Bythismeans, according to the present embodiment , in the coding processing by encoding section 102, column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits in the parity check mat rix . Thatis, with the present embodiment , encoding section 102 serves as an encoding section for encoding a transmission bit sequence and as a conversion section for performing column conversion on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix.

[0092] A specific example of column conversion processing on the parity check matrix in encoding section

102 will be described below. Here, the parity check matrix shown in FIG.10 is comprised of sub matrix Hi corresponding to systematic bit s (N=I to 4) and sub matrix H ₂ corresponding to parity bits (N=5 to 12) . Furthermore, sub matrix H ₂ has the same configuration as that of sub matrix H ₂ according to Embodiment 1.

[0093] Encoding sect ion 102 compares column degrees (i.e. the number of connections to check nodes) among the first to fourth columns corresponding to systematic bits Sl to S4 of the parity check matrix shown in the upper part of FIG.10. That is, encoding section 102 makes comparisons between column degree 3 (where the number of connections to check nodes in variable node 1 is 3) of the first column, column degree 3 (where the number of connections to check nodes in variable node 2 is 3) of the second column, column degree 4 (where the number of connections to check nodes in variable node 3 is 4) of the third column and column degree 4 (where the number of connections to check nodes in variable node 4 is 4) of the fourth column.

[0094] Encoding section 102 then performs column conversion in such a way that columns are arranged in descending order of column degrees of systematic bits. That is, encoding section 102 converts the third column and fourth column shown in the upper part of FIG.10 to the first column and second column as shown in the lower part of FIG.10, respectively, and converts the first

column and second column shown in the upper part of FIG.10 to the third column and fourth column as shown in the lower part of FIG .10 , respectively. Bythismeans, while the column degrees of the first column to fourth column are (3, 3, 4, 4) in the parity check matrix shown in the upper part of FIG.10, the column degrees of the first column to fourth column are (4, 4, 3, 3) in the parity check matrix shown in the lower part of FIG.10, that is, the descending order of column degrees. [0095] In the same way as Embodiment 1, encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using the parity check matrix shown in the lower part of FIG.10, to obtain a 12-bit LDPC codeword comprised of four systematic bits Sl to S4 and eight parity bit s Pl to P8. Here, the column degrees of systematic bits Sl and S2 are four, and the column degrees of systematic bits S3 and S4 are three. [0096] Further, interleaver 103 sorts the LDPC codeword in the same way as Embodiment 1. More specifically, as shown in FIG.11, interleaver 103 sorts systematic bits S4 to Sl andparitybits P8 to Pl in that order. Therefore, as shown in FIG.11, transmission circular buffer 104 stores in the head of the buffer a plurality of systematic bits in ascending order of column degrees from systematic bit S4, and stores in the buffer a plurality of parity bits in ascending order of the puncturing priority ranking from parity bit P8.

[0097] Next, the reading processing in transmission circular buffer 104 will be described in detail. Here, it is assumed that LDPC codeword length N=I 2. Furthermore, it is also assumed that systematic bit length K of the first transmission data (initial transmission data) is four bits and coding rate R is 2/7. Furthermore, systematic bit length K of second transmission data (first retransmission data) is two bits and coding rate R is 1/4. That is, the first transmission data (initial transmission data) is comprised of four systematic bits and ten parity bits (including two repetition bits) , and the second transmission data (first retransmission data) is comprised of two systematic bits and six parity bits. [0098] As shown in FIG.11, at the first transmission (initial transmission), circular buffer 104 reads out a 14-bit LDPC codeword in order from systematic bit S4 which is the start bit of the buffer as the first transmission data (initial transmission data) . More specifically, transmission circular buffer 104 outputs to modulation section 105 a 14 -bit LDPC codeword comprised of four systematic bits S4 to Sl, eight parity bits P8 to Pl and two systematic bits S4 and S3 as repetition bits. Furthermore, as shown in FIG.11, at the second transmission (first retransmission), transmission circular buffer 104 reads out an 8-bit LDPC codeword in order from systematic bit S2 which is the bit following systematic bit S3 at the tail end of the first transmission

data (initial transmission data) as the second transmission data (first retransmission data) . More specifically, transmission circular buffer 104 outputs to modulation section 105 an 8 -bit LDPC codeword comprised of two systematic bits S2 and Sl and six parity bits P8 to P3.

[0099] Thus, when data is transmitted at a coding rate lower than a mother coding rate as in the case of the first t ransmi s s ion data ( initial transmission data ) shown in FIG.11, systematic bit s S 4 and S3 having smaller column degrees are repeated preferentially . Furthermore, when the second transmission data (first retransmission data) shown in FIG.11 is transmitted, parity bits Pl and P2 having high puncturing priority ranking are punctured in the same way as Embodiment 1. That is, according to the present embodiment, when data is transmitted at a coding rate lower than the mother coding rate, it is possible to obtain a maximum effect of improving the error rate performances through repetition. Furthermore, according to the present embodiment, similar to Embodiment 1, it is possible to minimize degradation of the error rate performances due to puncturing. [0100] Furthermore, decoding section 207 (shown in FIG.7) of receiving-side radio communication apparatus 200 performs column conversion on the parity check matrix in the same way as encoding section 102 and decodes the received data using the parity check matrix subjected

to the column conversion. That is, according to the present embodiment, decoding section 207 serves as a decoding section that decodes the received data and as a conversion section that performs column conversion on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix. [0101] Thus, according to the present embodiment, when data is transmitted at a coding rate lower than the mother coding rate, column conversion is performed on the parity check matrix such that systematic bits with smaller column degrees, that is, systematic bits which are likely to include errors, are stored in the head of the transmission circular buffer. By this means, it is possible to preferentially complement by repetition the likelihoods of systematic bits having smaller effects of improving likelihoods through likelihood updating. Therefore, with the present embodiment, it is possible to obtain a maximum effect of improving the error rate performances through repetition while effects similar to those in Embodiment 1 are obtained.

[0102] Although a case has been described with the present embodiment where encoding section 102 performs column conversion on a plurality of columns corresponding to a plural ity of sys tematic bit s , interleaver 103 (FIG.l) may also sort systematic bits of the LDPC codeword instead of performing column conversion on the parity check matrix More specifically, interleaver 103 sorts a plurality of

systematic bits of the LDPC codeword obtained through LDPC coding using the parity check matrix shown in the upper part of FIG.10 in descending order of column degrees . By this means, transmission circular buffer 104 stores systematic bits in ascending order of column degrees, so that it is possible to obtain effects similar to those in the present embodiment. [0103] (Embodiment 3)

Although a case has been described with Embodiment 2 where column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits according to column degrees of systematic bits, a case will be described with the present embodiment where column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits according to total row degrees .

[0104] When the number of connections of check nodes to variable nodes becomes smaller (that is, when the row degrees of check nodes become smaller) , the number of likelihoods transferred between variable nodes becomes smaller. Therefore, when variable nodes connected to check nodes have a smaller number of connections to variable nodes, the number of likelihoods received through the check nodes to which the variable nodes are connected becomes smaller. Therefore, when variable nodes connected to check nodes have a smaller number of connections to variable nodes, the effect of updating

s

4 1

likelihoods through LDPC coding becomes smaller, and the error rate performances degrade. Therefore, when variable nodes are repeated, variable nodes having a smaller total number of connections to variable nodes through check nodes, that is, variable nodes having smaller total row degrees may be repeated preferentially to complement and increase likelihoods. That is, when the total row degrees of variable nodes become smaller, the effect of improving likelihoods becomes larger through repetition.

[0105] Therefore, according to the present embodiment, column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix according to total row degrees. [0106] Encoding section 102 (shown in FIG.l) of transmitting-side radio communication apparatus 100 according to the present embodiment performs column conversion on a plurality of columns corresponding to a plurality of systematic bits of the parity check matrix according to total row degrees. Furthermore, encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using the parity check matrix subjected to the column conversion. [0107] That is, according to the present embodiment, in the same way as Embodiment 2, encoding section 102 serves as an encoding section that performs encoding on the transmission bit sequence and as a conversion section

that performs column conversion on a plurality of columns corresponding to a plurality of systematic bits of the parity check matrix.

[0108] A specific example of column conversion processing on the parity check matrix in encoding section 102 will be described below. Here, in the same way as Embodiment 2, the parity check matrix shown in FIG.12 is comprised of sub matrix Hi corresponding to systematic bits (N=I to 4) and sub matrix H ₂ corresponding to parity bits (N=5 to 12) . Furthermore, sub matrix H ₂ has the same configuration as that of sub matrix H ₂ in Embodiment 1. [0109] Encoding section 102 compares total row degrees (i.e., the total number of connections to variable nodes connected through check nodes) in the first column to fourth column corresponding to systematic bits Sl to S4 of the parity check matrix shown in the upper part of FIG.12. That is, encoding section 102 makes comparisons among a total number of Is (eleven) located in the third row, fifth row and seventh row in which a 1 is located in the first column in FIG.12 (i.e., total number of connections (eleven connections) to variable nodes connected to variable node 1 through check node 3, check node 5 and check node 7) , a total number of Is (nine) located in the second row, third row and sixth row in which a 1 is located in the second column (i.e., total number of connections (nine connections) to variable nodes connected to variable node 2 through check node

2, check node 3 and check node 6), a total number of Is (eight) located in the first row, second row and fourth row in which a 1 is located in the third column (i.e., total number of connections (eight connections) to variable nodes connected to variable node 3 through check node 1, check node 2 and check node 4) , and a total number of Is (thirteen) located on the first row, seventh row and eighth row in which a 1 is located in the fourth column (i.e., total number of connections ( thirteen connections ) to variable nodes connected to variable node 4 through check node 1, check node 7 and check node 8) . [0110] Furthermore, encoding section 102 performs column conversion on the parity check matrix such that columns are arranged in descending order of total row degrees of systematic bits. That is, encoding section 102 converts the fourth column shown in the upper part of FIG.12 to the first column as shown in the lower part of FIG.12 and converts the first column to third column shown in the upper part of FIG.12 to the second column to fourth column as shown in the lower part of FIG.12. By this means, while the total row degrees of the first column to fourth column in the parity check matrix shown in the upper part of FIG.12 are (11, 9, 8, 13) , the column degrees of the first column to fourth column in the parity check matrix subjected to the column conversion shown in the lower part of FIG.12 are (13, 11, 9, 8), that is, the total degrees are arranged in descending order of

total row degrees.

[0111] Furthermore, in the same way as Embodiment 1, encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using the parity check matrix shown in the lower part of FIG.12 to obtain a 12-bit LDPC codeword comprised of four systematic bits Sl to S4 and eight parity bits Pl to P8. Here, the total row degree of systematic bit Sl is thirteen, the total row degree of systematic bit S2 is eleven, the total row degree of systematic bit S3 is nine, and the total row degree of systematic bit S4 is eight .

[0112] In the same way as Embodiment 2 , as shown in FIG .13 , interleaver 103 sorts an LDPC codeword in order from systematic bits S4 to Sl and parity bits P8 to Pl. Therefore, as shown in FIG.13, transmission circular buffer 104 stores a plurality of systematic bits in the head of the buffer in order from systematic bit S4 having a smaller total row degree, and stores a plurality of parity bits in order from parity bit P8 with lower puncturing priority ranking.

[0113] Next, reading processing in transmission circular buffer 104 will be described in detail. Here, in the same way as Embodiment 2, it is assumed that LDPC codeword length N is twelve. Furthermore, it is assumed that systematic bit length K of the first transmission data (initial transmission data) is four bits and coding

rate R is 2/7. Furthermore, systematic bit length K of the second transmission data (first retransmission data) is two bits and coding rate R is 1/4.

[0114] As shown in FIG.13, in the same way as Embodiment 2, transmission circular buffer 104 outputs to modulation section 105 a 14-bit LDPC codeword comprised of four systematic bits S4 to Sl and eight parity bits P8 to Pl, and two systematic bits S4 and S3 as repetition bits at the first transmission (initial transmission) . Furthermore, as shown in FIG.13, similar to Embodiment 2, transmission circular buffer 104 outputs to modulation section 105 an 8-bit LDPC codeword comprised of two systematic bits S2 and Sl and six parity bits P8 to P3 at the second transmission (first retransmission) . [0115] In this way, when the first transmission data (initial transmission data) shown in FIG.13 is transmitted at a coding rate lower than the mother coding rate, systematic bits S4 and S3 having smaller total row degrees are repeated preferentially. Furthermore, when the second transmission data (first retransmission data) shown in FIG.13 is transmitted, parity bits Pl and P2 having high puncturing priority ranking are punctured in the same way as Embodiment 1. That is, according to the present embodiment, when data is transmitted at a coding rate lower than the mother coding rate, it is possible to obtain a maximum effect of improving the error rate performances through repetition in the same way as

Embodiment 2. Furthermore, in the same way as Embodiment 1, according to the present embodiment, it is possible to minimize degradation of the error rate performances due to puncturing. [0116] Furthermore, decoding section 207 (shown in FIG.7) of receiving-side radio communication apparatus 200 performs column conversion on the parity check matrix in the same way as encoding section 102 and decodes the received data using the parity check matrix subjected to the column conversion. That is, with the present embodiment, in the same way as Embodiment 2, decoding section 207 serves as a decoding section that decodes received data and as a conversion section that performs column conversion on a plurality of columns corresponding to a plurality of systematic bits of the parity check matrix .

[0117] In this way, according to the present embodiment, when data is transmitted at a coding rate lower than the mother coding rate, column conversion is performed on the parity check matrix such that systematic bits having smaller total row degrees, that is, systematic bits which are likely to include errors, are stored in the head of the transmission circular buffer. Therefore, according to the present embodiment , it is possible to obtain effects similar to those in Embodiment 2.

[0118] Although a case has been described with the embodiment where encoding section 102 performs column

conversion on a plurality of columns corresponding to a plurality of systematic bits, interleaver 103 (FIG.l) can also sort systematic bits of an LDPC codeword instead of performing column conversion on the parity check matrix. More specifically, interleaver 103 sorts a plurality of systematic bits of an LDPC codeword obtained through LDPC coding using the parity check matrix shown in the upper part of FIG.12 in descending order of total row degrees. By this means, systematic bits are stored in transmission circular buffer 104 in ascending order of total row degrees, so that it is possible to obtain effects similar to those in the present embodiment.

[ 0119] The embodiments of the present invention have been described above. [0120] Although a case has been described with the above embodiments where an E ² RC-LDPC code is used, the codes that can be used in the present embodiments are not limited to E ² RC-LDPC code, and any code which has at least puncturing priority ranking in a codeword (i.e., FEC: Forward Error Correcting codes) can be used.

[0121] Furthermore, A padding bit used in the above embodiments may be either a 1 or a 0, as long as this is known (common) to both the transmitting-side radio communication apparatus and receiving-side radio communication apparatus. For example, a padding bit sequence may be a sequence of all 0s, a sequence of all Is, or a common sequence comprising Os and Is.

[0122] Furthermore, although a case has been described with above Embodiments 2 and 3 where systematic bits having smaller column degrees or systematic bits having smaller total row degrees are identified as systematic bits which are likely to include errors, systematic bits forming a shorter cycle or systematic bits forming a small size Stopping-Set can be applied to the present invention as systematic bits which are likely to include errors. [0123] Furthermore, although a case has been described with the above embodiments where CRC codes are used as error detecting codes in the transmitting-side radio communication apparatus, the error detecting codes for the transmitting-side radio communication apparatus are not limited to CRC codes. [0124] Furthermore, although a case has been described with the above embodiments where a receiving-side radio communication apparatus specifies the start position for storing received data in accordance with an RV parameter, the RV parameter may not be used. For example, when the first transmission data (initial transmission data) is received, the receiving- side radio communication apparatus may sequentially store received data from the head of the buffer and sequentially store received data starting from the bit position following the bit position in the tail end of the received data stored upon receiving the first transmission data (initial transmission data) . By this means, the receiving- s ide radio communication

apparatus can specify the position for storing the received data without using control information from the transmitting-side radio communication apparatus. [0125] In the above embodiments, a case in which the present invention is implemented in an FDD (Frequency Division Duplex) system has been taken as an example, but it is also possible for the present invention to be implemented in a TDD (Time Division Duplex) system. In the case of a TDD system, correlativity between uplink propagation path characteristics and downlink propagation path characteristics is extremely high, and therefore t ransmitt ing-s ide radio communication apparatus 100 can estimate reception quality in receiving-side radio communication apparatus 200 using a signal from receiving-side radio communication apparatus 200. Therefore, in the case of a TDD system, channel quality may be estimated by transmitting-side radio communication apparatus 100 without having receiving-side radio communication apparatus 200 issue a channel quality notification by means of a CQI..

[0126] Furthermore, the parity check matrixes of FIG.2, FIG.10 and FIG.12 are shown as examples, and the parity check matrixes that can be used for the present embodiments are not limited to the parity check matrixes shown in FIG.2, FIG.10 and FIG.12.

[0127] Furthermore, the systernatic bit length and coding rate set by control section 112 of transmitting- side radio

communication apparatus 100 are not limited to those determined according to channel quality and may also be fixed to certain values.

[0128] In the above embodiments, SINR is estimated as channel quality, but SNR, SIR, CINR, received power, interference power, bit error rate, throughput, an MCS

(Modulation and Coding Scheme) that enables a predetermined error rate to be achieved, or the like, may be estimated as channel quality instead. Furthermore, CQI may also be expressed as CSI (Channel State Information ) .

[0129] Furthermore, although a case has been described with the above embodiments where a CQI is fed back from a receiving- s ide radio communication apparatus to the transmitting- side radio communication apparatus, an average SINR, average SIR and MCS parameter may also be fed back in the present invention.

[0130] Furthermore, variable nodes may also be referred to as "bit nodes." [0131] Furthermore, In a mobile communication system, transmitting-side radio communication apparatus 100 can be provided in a radio communication base station apparatus, and receiving- side radio communication apparatus 200 can be provided in a radio communication mobi Ie stat ion apparatus . Also, transmitting- side radio communication apparatus 100 can be provided in a radio communication mobile station apparatus, and

receiving-side radio communication apparatus 200 can be provided in a radio communication base station apparatus. By this means, a radio communication base station apparatus and radio communication mobile station apparatus can be implemented that offer the same kind of operation and effects as described above. [0132] Furthermore, the radio communication mobile station apparatus may also be referred to as a "UE," and radio communication base station apparatus may also be referred to as "Node B."

[0133] In the present embodiment, although the present invention is configured with hardware as an example, the present invention can also be implemented with software. [0134] Furthermore, each function block employed in the description of each of the aforementioned embodiments may typically be implemented as an LSI constituted by an integrated circuit. These may be individual chips or partially or totally contained on a single chip. "LSI" is adopted here but this may also be referred to as "IC," "system LSI," "super LSI," or "ultra LSI" depending on differing extents of integration.

[0135] Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. After LSI manufacture, utilization of an FPGA (Field Programmable Gate Array) or a reconfigurable processor where connections and settings of circuit cells in an

LSI can be reconfigured is also possible. [0136] Further, if integrated circuit technology comes out to replace LSI ¹ S as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Application of biotechnology is also possible.

Industrial Applicability [0137] The present invention is applicable to a mobile communication system or the like.