Field of the Invention

This invention relates to a network for signals of different bandwidth, and a rate controller for use in allocating bandwidth to a signal path through the network.

Background

It is known to link multi-user systems over large distances through leased telephone lines. For example, a workstation may be linked over a long distance to a host computer through a leased line in a telephone system. The line passes through a number of switching nodes and its bandwidth may be shared by a number of different users connected to the same host or different source end systems. The data is typically transmitted between the work station and host in a bi-directional manner, in bursts. The transmissions may be supported by asynchronous mode transmission mode (ATM) equipment. The bandwidth available to a particular transmission is initially determined by the signal source performing a routine in which the transmitted data rate is progressively increased in a test routine. The system at the destination sends back to the source a signal when the received signals become corrupted due to the data rate becoming too high, and in this way the data transmission bandwidth is set to the maximum value that the path can handle. Another bandwidth allocation technique is disclosed in EP-A-0 603 099.

When a number of signal sources and destinations share the same line, an unfair allocation of bandwidth can occur in which the shortest path tends to grab the most bandwidth because the acknowledgement signal returned during test routine occurs more quickly over a short path, so that the shorter path can acquire bandwidth more quickly. As a result, long paths tend to operate at a slower data rate than short paths. Another disadvantage is that the customer has to lease the telephone lines on a continuous basis, whereas the actual utilisation of the line varies greatly with time. For example, at night, a

low utilisation rate may be achieved so that the customer has to pay for time when the line is not actually being used.

Recently, proposals have been made to integrate leased lines into a telephone network system so that the available bit rate (ABR) of the leased line can be used for other purposes during periods of low data transmission so as to permit data users to be charged on the basis of time that data is actually transmitted rather than on a flat rate leasing basis.

One proposal is to use the so-called virtual source/destination (VS/ND) configuration in which a source end system (SES) is connected to a public telephone network through a node which acts as a so-called virtual source (VS) that feeds data from the SES into the network for onward transmission to a destination end system (DES) for example a host computer or another workstation. The DES is connected to the public network through a so-called virtual destination (ND) that receives signals from the virtual source. Also, the DES can communicate back to the SES so that the virtual source and virtual destination operate bi-directionally and each comprise a NS/VD. In PCT GB 95/00502 and EP 94301673.3 a NS/ND system is described in which the bandwidth allocated to a bi-directional ATM transmission path through a public telephone network is controlled by means of a dynamic bandwidth controller (DBC). The DBC acts as a VS/ND and a conneαion admission control function (CAC) reviews the available bandwidth of switching nodes disposed along the transmission path so that the DBC can optimally allocate bandwidth to the path depending on operational conditions in the public network.

The DBC communicates with the SES using a specially configured form of digital ATM signal known as a resource management (RM) signal, which is used to instruct the SES to transmit at a data rate corresponding to a particular bandwidth determined by the DBC to be acceptable for the network. Also, the DBC reviews data signals received from the SES to police

the data transmission rate to ensure that it falls within the acceptable bandwidth. The DBC also buffers signals received from the SES and provides certain data re-shaping and rate control functions.

s The use of NS/ND architecture overcomes the contention difficulties associated with prior networks but has the disadvantage that a CAC function needs to be overlaid for all the switches of the public telephone network in order to provide the DBC with bandwidth control information. However, in practice, the network provider may wish to introduce VS/ND facilities 0 progressively through the network and the introduction of a CAC and a DBC funαion as described in PCT GB 95/00502 and EP 94301673.3 would be initially expensive as it implies that all of the switches of the system would need to be replaced by switches that can handle ABR formatted signals.

s Summary of the Invention

With a view to overcoming the problem, the present invention provides a network for signals of different bandwidth, comprising: an input for signals from a source end system; an output for the signals; a plurality of switching nodes for seleαively providing a signal communication path between the 0 input and the output; a dynamic bandwidth controller for controlling the bandwidth allocated to the path for signals from the source end system; and a plurality of rate controllers each associated with a respeαive one of the switching nodes for determining the bandwidth available for the path through the node; the dynamic bandwidth controller being operative to interrogate the S rate controllers such as to determine the bandwidth available for the path and provide a signal to instruα the source end system of the available bandwidth.

By the use of a plurality of individual rate controllers, each associated with a respeαive switching node, the use of a separate CAC is avoided, which 0 permits the switching nodes of an existing network progressively to be changed to handle ABR signals so that the ABR service can be progressively introduced through the network.

Preferably the rate controllers each include means for transmitting a signal representative of the bandwidth available for the path through its associated node, to the rate controller associated with a next switching node along the path, and bandwidth determining means for determining the bandwidth available for the path through the node as a funαion of the lowermost of the aαual available bandwidth and the bandwidth signalled to be available through the preceding node.

The invention also includes a rate controller for use with one of a plurality of switching nodes conneαed in a network comprising an input for signals from a source end system, an output for the signals, a signal communication path between the input and the output through the plurality of switching nodes, and a dynamic bandwidth controller for controlling the bandwidth allocated to the path for signals from the source end system, the rate controller comprising: means for transmitting a signal representative of the bandwidth available for the path through the node, to the rate controller associated with a next switching node along the path, and bandwidth determining means for determining the bandwidth available for the path through the node as a funαion of the lowermost of the aαual available bandwidth and the bandwidth signalled to be available through the preceding node.

The invention also extends to a method of allocating bandwidth to a signal path through a network for signals of different bandwidth that comprises an input for signals from a source end system, an output for the signals, a plurality of switching nodes for seleαively providing a signal communication path between the input and the output, the method comprising: controlling the bandwidth allocated to the path for signals from the source end system; and successively, for each node in the path, transmitting a signal representative of the bandwidth available for the path through the node to the next switching node along the path, and determining the bandwidth available for the path through the node as a funαion of the lowermost of the aαual available bandwidth and the bandwidth signalled to be available through the

preceding node.

Currently, international standards for an ABR service are being developed. Reference is direαed to ITU Draft Revised Recommendation 1.371, Traffic Control and Congestion Control in B-ISDN. 1995 and Ed. Shirish Sathaye, ATM Forum Traffic Management Specification, Version 4.0, 1995. The proposed standards include predetermined formats for the RM signals that are used to communicate between the VS/VD and the SES/DES. However, the network provider may wish to use proprietary RM signals within the network itself.

In accordance with the present invention there is provided a network for signals of different bandwidth, comprising: an input for signals from a source end system; an output for the signals; a plurality of switching nodes for seleαively providing a signal communication path between the input and the output; means for producing network resource management signals as a funαion of bandwidth availability in the network; and a dynamic bandwidth controller responsive to the resource management signals for controlling the bandwidth allocated to the path for signals from the source end system; the dynamic bandwidth controller is configured to communicate with the source end system using resource management signals in a different format to the network resource management signals.

Thus, in accordance with the invention, RM cells according to an agreed standard can be used between the network and the SES or DES whereas proprietary RM signal formats can be used within the network itself.

Brief Description of the Drawings

In order that the invention may be more fully understood an embodiment thereof will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram of a network in accordance with the invention;

Figure 2 is a block diagram showing in more detail the signal path PVCl of Figure 1;

Figure 3 illustrates in more detail the signal paths between one of the switches shown in Figure 2 and its associated rate controller; Figure 4 is a detailed block diagram of the rate controller;

Figure 5 is a more detailed block diagram of the dynamic bandwidth controller (DBC); and

Figure 6 is a schematic diagram of a RM cell.

Detailed Description

Referring to Figure 1, source end systems SES1, SES2 send signals over permanent virtual conneαions (PVCl, PVC2) through a switch network which includes switches SW1-SW3, SWN. The switched network may comprise a public telephone network. As shown in Figure 1, SES1 communicates with a source end system SES3 and the data flow between the source end systems is bi-direαional. The source end systems transmit ATM signals and can operate at different data rates in order to control the bandwidth of the transmitted signals. As is well known in the art, the ATM signals comprise a bit sequence comprising a series of header bits followed by data bits.

Each of the switches SW1-SWN, comprise ATM switches which have a plurality of input ports and a plurality of output ports so that a plurality of switching paths can be set up through the switch under the control of conventional internal switching circuitry, which may be software controlled. ATM switches are well known per se and will not be described in detail herein. The switch has an overall bandwidth capacity which can be allocated between the various signal paths depending on the required bandwidth for each of them.

As will be explained in more detail hereinafter, the bandwidth allocation for the individual switches SW is performed by a respeαive rate controller. As

shown in Figure 1, switches SW2, SW3 have respeαive rate controllers RCl, RC2.

The system described herein utilises a virtual source and virtual destination VS/VD as described previously. Considering the path PVCl, switch SWl in combination with a dynamic bandwidth controller DBCl constitutes a VS in the network for signals from SESl. Similarly, switch SWN and an associated dynamic bandwidth controller DBC2 constitutes a virtual destination VD for the signals from SWl so that they can be communicated through output Ol to SES3. For signals travelling from SES3 to SESl, switch SWN and DBC2 constitute a virtual source with SW1/DBC1 constituting a virtual destination. Similarly, SW1/DBC1 constitutes a VS for signals from SES2. The signal transmission and bandwidth allocation for signal path PVCl will now be described in more detail. ATM signals from SESl are direαed through the switch SWl to the dynamic bandwidth controller DBCl which as previously explained aαs as a VS/VD for SESl. The struαure of DBCl is as described in PCT GB 95/00502 and EP 943016173.3. It provides policing, buffering and re-shaping and rate control funαions.

The DBCl also aαs as a VS for path PVC2 from SES2. The ATM signals from the sources SESl are fed to input ports 11,12 of the switch SWl and are direαed to DBCl and hence to output ports of the switch.

Bandwidth control in the network is achieved by the use of resource management RM signals. These comprise ATM signals of the same general struαure as the data being transmitted and include header bits which constitute routing data representative of the route of the path through the switches known in the art as the virtual path or conneαion index VPI/VCI. The RM signals also include control data which are used to control the bandwidth settings of various devices in the network, as will be explained in more detail hereinafter.

Referring to Figure 5, the DBCl includes an aαivity deteαor 10 which deteαs when ATM signals are being transmitted by the source end system SESl or SES2, and a buffer 11 which includes a plurality of buffer circuits to receive ATM signals received at inputs 11,12 to the switch SWl respeαively. A signal indicative of the fill level of the buffers is fed to a controller 12, which,as explained in PCT GB 95/00502 allocates bandwidth to the PVC's 1,2. Signals from the buffer 11 are fed to a shaper/scheduler circuit 13 and, under the control of controller 12, are fed to an appropriate output port of the switch SWl dependent upon the routing information in the header bits of the ATM signal.

Also, the controller 12 and shaper/scheduler 13 can be used to transmit RM signals along the various PVC's. A typical example of the struαure of a RM signal used in this embodiment is shown in Figure 6 and comprises a series of header bits H which includes the VPI/NCI which constitutes routing information that corresponds to the routing information of the ATM data signals so that the RM signals can be routed along the same path as the ATM data signals. Additionally, the RM signals include data bits ID indicating the DBC or RC which has generated the RM signals. Also, data bits CR define the cell rate or bandwidth available at the switch for the signal path PVC at which the RM signal was generated. Considering now path PVCl in more detail, DBCl generates an RM signal that indicates the bandwidth available for ATM signals passing through switch SWl, and the resulting RM signal is transmitted over control path 1-2 shown in Figure 2 to switch SW2. Referring again to Figure 5, DBCl is arranged to receive RM signals fed back from the switch SW2 and the RM signals are received by feedback circuits 14 which, in turn feed RM signals to SESl in order to control its operation.

The funαional relationship between switch SW2 and its associated rate controller RCl will now be described with reference to Figures 2 and 3.

ATM data signals passing along PVCl from SESl through switch SWl are fed to an input port of switch SW2. The header bits of the ATM signals, which

include routing information are, in a conventional manner compared with a routing table and as a result, the ATM switch direαs the ATM data signals to an appropriate output port of switch SW2 so as to be routed on to the next switch along the path i.e. switch SW3.

However, for RM signals received from DBCl, the switch SW2 is programmed to divert the RM signals to the rate controller RCl. As will be described in more detail hereinafter, the rate controller RCl is configured to review, in response to the RM signal from DBCl, the bandwidth available to signals on path PVCl through switch SW2. The rate controller then compares this bandwidth with the bandwidth or cell rate CR indicated by the RM signal from DBCl and chooses whichever is the lower. It will be appreciated that the lower value constitutes the maximum bandwidth available on the seαion of path PVCl between the input port to switch SWl and the output port of switch SW2.

The rate controller RCl then generates its own RM signal with header bits corresponding to route information for the next seαion of the path PVCl, namely control path 2-3 shown in Figure 2. The RM signal is received by switch SW3 and associated rate controller RC2 which performs a control funαion in a similar way to switch SW2 and RCl. The process is repeated for further switches and rate controlling along the path PVCl until an end switch SWN is reached.

As shown in Figure 1, the end switch SWN has an associated dynamic bandwidth controller DBC2 which, as previously explained, operates both to provide DBC funαions and rate control funαions in a similar way to the rate controllers RC. Upon receipt of the RM signal from the preceding switch SW, namely switch SW3 as shown in Figure 2, the switch SWN routes the RM signal to DBC2. The controller of DBC2 chooses the lowermost value of the available bandwidth for switch SWN and the value of the bandwidth indicated by the bit CR in the RM signal from RC2. It will be appreciated

that the lowermost value is representative of the maximum bandwidth available along the entire path PVCl since, for each switching node, it is necessary to consider the lowermost bandwidth, which will aα as a restriαion for the entire path.

DBC2 is configured to transmit a RM signal backwardly along the path PVCl to the switch SW3 and associated rate controller RC2 which then operates to allocate bandwidth to path PVCl at switch SW3 according to the path bandwidth signal generated by DBC2, which is indicated by the cell rate CR of the RM signal transmitted by DBC2 to RC2.

Rate controller RC2 then itself generates a RM signal which is transmitted back to rate controller RCl and has a CR bit corresponding to the value of the path bandwidth signal generated by DBC2. The rate controller RCl then sets the available bandwidth for PNC1 through SW2 according to the value of the path bandwidth signal. RCl then in a similar manner, passes the path bandwidth signal back to DBCl, which allocates bandwidth to PNCl through switch SWl according to the path bandwidth signal.

Thus, all of the switches SW1-SWΝ in path PVCl are set to the maximum available bandwidth for the entire path PVCl. DBCl then generates a RM signal which is transmitted to SESl, instruαing the source to transmit data at a rate corresponding to this maximum available bandwidth for path PVCl.

The dynamic bandwidth controller DBCl then performs a policing funαion for the signals transmitted on PVCl. If the data rate exceeds the permitted rate set by the RM signal from DBCl, for more than a predetermined period, cells will be discarded by the DBC for the data transmission along path PVCl in order to prevent SESl unallowably capturing more than its allocated bandwidth.

The struαure of the rate controller RCl will now be described in more detail

with reference to Figure 4, it being understood that all of the rate controllers RC can have an identical architeαure. The rate controller RCl comprises a RM cell reader 15 which reads data from RM cells fed thereto from the corresponding switch SW2. The cell reader 15 reads the header bits from the RM cell in order to determine routing information, reads the ID information to determine which RC/DBC has generated the RM cell, and also the CR bits in order to determine the bandwidth information. This data is fed to a controller 16, which is typically microprocessor based, with an associated operating memory, and performs a number of different funαions as now will be explained. The first funαion comprises bandwidth allocation as shown by funαion block 17. The controllers 16 reviews the bandwidth allocated to the various PVCs (and other channels) which are routed through the switch SW2, and also has information concerning the maximum available bandwidth through the switch. The maximum available bandwidth which can be allocated to a particular PVC can be determined by an algorithm known per se, for example the so-called Robin Hood algorithm which is described in EP 94301673.3 which "robs" bandwidth from a path which is "rich" in bandwidth and gives it to a "poor" path according to a predetermined funαion.

The controller 16 also performs a route discovery funαion 18 in which the route is identified from the VPI/VCI header bits of the incoming RM signal. A RM cell writer 20 is used to generate RM cells for transmission back to the switch SW with header bits corresponding to the relevant route as determined by funαion 18, an ID cell corresponding to the identity of the rate controller and a CR cell which indicates the lowermost of the available bandwidth as indicated by funαion 17 and the bandwidth indicated by the incoming RM cell read by cell reader 15. The resulting RM cell is thus transmitted back to the switch SWl for onward transmission forwardly along the path to switch SW3.

As previously explained, the switch SWN aαs an end switching node and DBC2 transmits back along the path a RM signal which constitutes a path

bandwidth signal representative of the bandwidth available for the entire path, so that all of the rate controllers RC can allocate bandwidth for the path at their respeαive switches according to the path bandwidth signal. To this end, the controller 16 shown in Figure 4 includes a wait funαion 19 during which it waits for the reception of a RM signal transmitted backwardly along the path from rate controller RC2, which contains a CR cell corresponding to the path bandwidth signal derived from DBC2. Upon receipt of this RM signal by reader 15, the controller 16 operates to set the bandwidth for path PVCl, using funαion 17, so as to correspond to the path bandwidth signal.

When the ATM data signals from SESl go quiet, it is no longer necessary to maintain a bandwidth allocation for the path PVCl. In this situation, the dynamic bandwidth controller DBCl transmits a RM signal to RCl which contains a zero level CR bit.The processor has an associated bandwidth release funαion 21, so that the controller 16 releases the bandwidth allocated to path PVCl and the bandwidth allocation funαion 17 can be re-run so as to distribute the bandwidth amongst other aαive paths. From the foregoing it will be appreciated that the rate controller RCl responds to RM signals transmitted both forwardly and backwardly along the path PVCl. This enables the route funαion 18 shown in Figure 4 to develop a map of the relevant input and output ports of switch SWl for the respeαive PVCs. Thus, the memory of the controller 16 can be used to build up a collation between the input ports that receive RM signals from a particular path that are transmitted forwardly and a corresponding output which receives an RM signal from the next switching node along the path, from which RM signals are transmitted backwardly. This information can be correlated with the routing information of forwardly direαed RM signals so that when an RM signal is received and a further RM signal is to be generated and transmitted forwardly by a particular rate controller, the rate controller can refer to the memory map that has been built up to determine which output port the RM signal should be direαed to so that it is correαly forwarded to the next switching node on the path concerned.

Furthermore, the rate controller RCl may use an internal RM signal protocol, which generates header bits according to a local standard. The header bits may be translated when the RM signal is fed to the switch by internal software associated with the switch itself, so as to convert the local protocol of the rate controller in to a common standard used between the switches SW1-SWN.

Also, the described network permits different RM signal protocols to be used in different parts of the network. For example, communication between the switches SWl and SWN and the respeαive source end systems SESl, SES3 may be carried out with RM signals according to an internationally accepted standard, whereas the RM signals used between the switches SW1-SWN may be to a different standard preferred by the network operator. In this situation, DBCl and DBC2 include translation means in order to recognise RM signals according to the international standard and then to generate RM signals for forward transmission within the network according to a separate network standard.