The invention relates to sensors. More specifically but not exclusively it relates to sensors such as inertial sensors, for example accelerometers and gyroscopes capable of high levels of quadrature rejection to minimise errors in signal channels of such sensors.

Many types of inertial sensors are known. Angular velocity sensors incorporating a MEMS type ring are known and such examples can be seen in, for example, GB2322196. In such angular velocity sensors a vibrating planar ring or hoop-like structure is disclosed. The ring-like structure is suspended in space by a suitable support mount for detecting turning rate, linear acceleration and angular acceleration. Turning rate is sensed by detecting vibrations coupled by Coriolis forces, whereas linear acceleration and angular acceleration are sensed by lateral, vertical and rocking movement of the entire ring or hoop-like structure within its mount.

High levels of quadrature bias, >1000 s, which is at 90° to the required rate signal (<17s) may be present in mechanical MEMS gyroscopes and is not easily reduced without expensive mechanical trimming. This requires the secondary channel of the MEMS gyroscope to have high levels of quadrature rejection, in the order of or greater than 60dB, which is equivalent to a phase accuracy of the demodulator of <0.05°. Additionally, due to the high levels of undesirable quadrature signals, the demodulator circuit within the secondary channel is subject to high levels of significantly fast changes in voltage over a very short period of time (dv/dt).

In order to solve these issues and to produce an accurate system, the use of high performance circuits, very accurate phase, high bandwidth and fast slew rates is required. This can increase the cost and size of the sensor.

According to the invention there is provided an angular velocity sensor comprising a ring type sensor having primary and secondary elements, the sensor further comprising primary and secondary channels connected to said primary and secondary elements, the primary channel comprising primary driver means for initiating and maintaining resonant oscillations in the primary elements, the secondary channel comprising detector means for detecting signals generated by the secondary elements in response to movement of the sensor, the detecting means including a differential amplifier and synchronous detectors generating an output signal dependent upon the movement of the sensor, wherein the secondary channel further comprises means for improving quadrature rejection in the secondary channel signal, said means comprising a series of circuits including a synchronous detector, passive and active filters and a decimator, said output signal being passed through the series of circuits and thereby suppressing high levels of quadrature signals.

According to the invention there is further provided a method of reducing quadrature rejection in the secondary channel signal of a MEMS angular velocity sensor comprising the steps of detecting the signal using a synchronous detector; filtering the signal using passive filtering means; filtering the signal using active filtering means; decimating the signal so as to suppress any remaining quadrature component of the signal; and averaging offset from the output of the active filter.

In this way, the secondary channel signal is modified to include a number of stages that combine to provide overall in the region of 88dB of suppression, although different levels of suppression may be achieved by suitable variation of the stages. Additionally, the architecture utilised is designed to minimise the required performance of the various stages, reducing the required phase accuracy, reducing the required bandwidth, reducing the required slew rates and therefore reducing the current consumption. In this way a sensor having high levels of quadrature rejection is produced using relatively low performance circuitry.

The invention will now be described with reference to the accompanying diagrammatic drawings in which:

Figure 1 is a schematic drawing of an angular sensor in accordance with one form of the invention including circuitry capable of reducing high levels of quadrature rejection.

As shown in Figure 1 , the MEMS ring structure 1 of the angular velocity sensor comprises inner 2 and outer 3 peripheries extending around a common axis, the drives and pickoffs operating differentially. Piezoelectric primary drive means 4 are provided that cause the sensor to vibrate on supports (not shown). The supports may include a plurality of flexible support beams (not shown) for supporting the sensor and for allowing it to vibrate in response to the piezoelectric primary drive means input in a substantially undamped oscillation mode. This enables the resonator to move relative to the support means in response to turning rate of the system including the sensor.

A detecting circuit 5 is provided to which a series of signals 6 are input from the sensor. The signals output by the sensor include primary pickoff signals 6a and secondary pickoff signals 6b and the transducer plates are arranged such that the signals are of a differential form. These signals are output from primary and secondary portions of the sensor. The primary pickoff differential transducer signal is input to a differential charge amplifier (primary pickoff amplifier) 7 which provides a high level of gain to provide a low noise differential sinusoidal output signal at the carrier frequency. This signal is then passed through a synchronous detector 8 and suitable filtering to provide a control signal to the primary driver circuit 1 to set the level of the drive applied to the MEMS to ensure the primary pickoff amplifier output is on a controlled fixed level. The output of the primary pickoff amplifier 7 is also applied to the primary phase lock loop (PLL) and voltage controlled oscillator (VCO) 10 which locks the frequency of the ring to its natural primary resonance frequency to provide clocks for the synchronous detectors 8. The output of the primary pickoff amplifier 7 is also applied to the primary phase shift circuit 11 which amplifies the signal by a factor of two and shifts the phase of the differential signal by 90°. The output of the phase shift circuit 11 is applied to the primary driver circuit 1 which multiplies the differential sinusoidal output of the phase shift circuit 11 by the AGC control signal to generate the differential MEMS driver waveforms.

The outputs of the secondary portions of the sensor 6b are input to a secondary pickoff amplifier 13. The outputs of the secondary pickoff amplifier 13 are then connected to the inputs of two synchronous detectors 14, 15. The quadrature channel synchronous detector 14 is used to generate a base band voltage proportional to the amount of quadrature signal. The signal (rate) channel synchronous detector 15 is used in combination with a set of series circuits; namely discrete functional blocks that process the signal sequentially to generate a base band signal that is proportional to the rate signal such that the combination of the functional blocks rejects the high level of quadrature signal on the output of the pickoff amplifier. The quadrature rejection circuitry comprises 4 stages;

Stage 1 is a synchronous detector 20 and uses a set of simple switches that ensure fast switching times and therefore accurate synchronous detection. Using simple switches with fast switching times ensures phase accurate synchronous detection and very low signal distortion while being very simple and using minimal supply current.

Stage 2 is a passive filter 21 and may be a simple first order RC low pass filter. This is required as the output of the synchronous detector contains large dv/dt discontinuities which are significantly reduced by the passive filter prior to being applied to further circuitry, for example an active filter 22. It can be difficult for an active filter to process a signal with large dv/dt discontinuities as the finite bandwidth and slew rates associated with active circuits would lead to an asymmetric time response and therefore significantly reduced quadrature rejection.

Stage 3 is an active filter 22 and may be a simple first order low pass filter. This filter 22 further attenuates any artefacts of the demodulation process and provides additional smoothing of the required dc signal level. An op-amp within the active filter 22 is chopped to suppress flicker noise and is arranged to be 45° after the demodulator clock to ensure it is not coincident with the sampling points.

Stage 4 is a decimator stage 23 which acts to suppress any remaining quadrature component of the signal typically by sampling the ripple generated by the quadrature signal and averaging this to zero and averaging the offset from the output of the active filter 22. The decimator 23 samples at four times the carrier frequency rate and averages these samples to provide an output at the carrier frequency rate. This suppresses any carrier frequency or twice carrier frequency components resulting from the demodulation and filtering stages and avoids sub-sampling these down to form dc offsets. Any remaining ripple generated by the quadrature signal is sampled and rejected by the decimation process.

The four stages will now be described in more detail.

In Stage 1, the input carrier frequency is demodulated using the correct phase clock signal using simple switches and outputs a full-wave rectified sine-wave which can be averaged to provide a dc signal. Any quadrature signal will generate a ripple signal with large dv/dt discontinuities on the demodulated output signal. This is passed through the passive filter 22, which starts to smooth the full-wave rectified sine-wave. The demodulator and passive filter are placed before the active filter 22 as due to the very large quadrature signal the chopped sin wave from the demodulator has very large voltage discontinuities which makes it unsuitable as an input for many active circuits. The finite bandwidth and slew rates of active circuits would lead to asymmetric time response and significantly degrade the quadrature suppression. The use of the passive filter first converts these large voltage discontinuities to much smaller dv/dt discontinuities. The output of the passive filter then defines currents into the active low pass filter, which by its nature is able to reduce the discontinuities to even smaller gradients. The signals required from the op-amp are now very much in the small signal response region with only a few artefacts of the demodulation process reducing the required performance of the op-amp in the active filter. To further enhance the quadrature rejection the switches in the demodulator are designed to provide balance resistance around the mid rail voltage. The active filter 22 provides both additional smoothing of the required dc signal and low output impedance for interfacing to the following circuits. The op-amp in the active filter is also chopped to suppress flicker noise of this stage and is arranged to be 45° after the demodulator clocks to ensure that the chopping does not occur at the sampling points.

The output of the active filter 22 is then passed into a decimator 23 which enhances the quadrature suppression by sampling the ripple generated by the quadrature signal and averaging this to zero and averages the offset from the output of the active filter 22.

The decimator samples at four times the carrier frequency and provides an average output at the carrier frequency rate. The demodulated signal contains frequencies that are twice the carrier frequency and therefore have to be sampled at twice the highest frequency to avoid aliasing. It will be appreciated that other multiplication factor above 4 would work (8, 16 etc) but would add further delays and complexity Using this method suppresses any carrier frequency or twice carrier frequency components resulting from the demodulator and filtering stages and avoids sub-sampling these down to form dc offsets. It also zeros any remaining quadrature signal and averages the inputs offsets of the previous stages as they appear as a chopped offset. In this manner, very high suppression of large quadrature signals is achieved. Additionally, there are reduced performance requirements for active circuits, lower gain bandwidth, slew rates and power consumption. The output of stage 4 of the quadrature rejection stages is input to a rate channel programme gain amplifier and output buffer stage 25 and subsequently output to an A to D converter 26 to produce the required signal dependent on the movement of the sensor. It will be appreciated that the scheme described above may be used where the output for the MEMS transducers are not differential. The order of the stages described may be varied but the order described has been found to minimise the circuit requirements and achieve optimum quadrature rejection. It will be appreciated that although the invention is described with reference to an angular velocity sensor of the type described above, it may equally be applied to a sensor such as a piezo ring case, the same applying to other forms of transduction such as piezo, capacitive, inductive. It will further be appreciated that the inner and outer electrodes only relate to the piezo. Anti phase signals can be obtained from 45deg to 135deg etc from non piezo pick offs, such as inductive or capacitive pickoffs.