Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/052982
Kind Code:
A3
Abstract:
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor (402) connected in cascode with a second transistor (404), wherein an input clock (Clk_in) node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit (406) having an input coupled to the input clock node, wherein an output (Div_out) of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node (Clk_out) of the circuit is coupled to drains of the first and second transistors.

Inventors:
PAUL, Animesh (5775 Morehouse Drive, San Diego, California, 92121-1714, US)
ZHUANG, Jingcheng (5775 Morehouse Drive, San Diego, California, 92121-1714, US)
CHEN, Xinhua (5775 Morehouse Drive, San Diego, California, 92121-1714, US)
SRIDHARA, Ravi (5775 Morehouse Drive, San Diego, California, 92121-1714, US)
Application Number:
US2017/051336
Publication Date:
April 26, 2018
Filing Date:
September 13, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
QUALCOMM INCORPORATED (ATTN: International IP Administration, 5775 Morehouse DriveSan Diego, California, 92121-1714, US)
International Classes:
H03K5/156; H03K21/02
Foreign References:
JP2000013197A2000-01-14
JPS5643755A1981-04-22
US20010028267A12001-10-11
US4125811A1978-11-14
US20130038350A12013-02-14
US20130082769A12013-04-04
US7839192B12010-11-23
Attorney, Agent or Firm:
ROBERTS, Steven E. et al. (Patterson & Sheridan, L.L.P.24 Greenway Plaza, Suite 160, Houston Texas, 77046-2472, US)
Download PDF: