Title:
READ-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) READ PORT(S), AND RELATED MEMORY SYSTEMS AND METHODS
Document Type and Number:
WIPO Patent Application WO/2016/137685
Kind Code:
A3
Abstract:
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.
Inventors:
ATALLAH FRANCOIS IBRAHIM (US)
BOWMAN KEITH ALAN (US)
HANSQUINE DAVID JOSEPH WINSTON (US)
JEONG JIHOON (US)
NGUYEN HOAN HUU (US)
BOWMAN KEITH ALAN (US)
HANSQUINE DAVID JOSEPH WINSTON (US)
JEONG JIHOON (US)
NGUYEN HOAN HUU (US)
Application Number:
PCT/US2016/016120
Publication Date:
October 27, 2016
Filing Date:
February 02, 2016
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
G11C11/412; G11C11/418; H01L27/11
Foreign References:
| US20070177419A1 | 2007-08-02 | |||
| US4660177A | 1987-04-21 | |||
| US20080117665A1 | 2008-05-22 | |||
| US20020159312A1 | 2002-10-31 | |||
| US6341083B1 | 2002-01-22 |
Attorney, Agent or Firm:
TERRANOVA, Steven, N. (PLLC106 Pinedale Springs Wa, Cary North Carolina, US)
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