Title:
READ CIRCUIT OF STORAGE CLASS MEMORY
Document Type and Number:
WIPO Patent Application WO/2017/215119
Kind Code:
A1
Abstract:
A read circuit of storage class memory comprises: an array; a read reference circuit, having the same bit line parasitic parameters as the array, having the same read transmission gate parasitic parameters as the array, used to generate a read reference current; a sense amplifier, providing the same current mirror parasitic parameters as the reference side, used to generate a read current from a selected memory cell, compare the said read current with the said read reference current and output a readout result. In the present invention, the said read current and the said read reference current are generated at the same time, the transient curve of the said read reference current is between the low resistance state read current and the high resistance state read current from an early stage. The present invention largely reduces the read access time, has a good process variation tolerance, has a wide application, and is easy to be used in the practical product.
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Inventors:
LEI YU (CN)
CHEN HOUPENG (CN)
LI XI (CN)
WANG QIAN (CN)
SONG ZHITANG (CN)
CHEN HOUPENG (CN)
LI XI (CN)
WANG QIAN (CN)
SONG ZHITANG (CN)
Application Number:
PCT/CN2016/096649
Publication Date:
December 21, 2017
Filing Date:
August 25, 2016
Export Citation:
Assignee:
SHANGHAI INST MICROSYSTEM & INFORMATION TECH CAS (CN)
International Classes:
G11C13/00
Foreign References:
| CN106205684A | 2016-12-07 | |||
| CN103295626A | 2013-09-11 | |||
| CN101976578A | 2011-02-16 | |||
| CN104347113A | 2015-02-11 | |||
| CN1838313A | 2006-09-27 |
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (CN)
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