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Patent Searching and Data


Title:
READING CIRCUIT FOR RESISTANCE CHANGE MEMORY DEVICE AND METHOD FOR READING SAME
Document Type and Number:
WIPO Patent Application WO/2019/087769
Kind Code:
A1
Abstract:
Provided are: a reading circuit which is for a resistance change memory device and which is capable of reducing area size while advantageously saving power; and a method for reading same. A bit line BL to which a memory cell 12 is connected and a dummy bit line DBL to which a reference cell 14 is connected are both pre-charged. A sense amplifier detects a difference in potential during discharging between the pre-charged bit line BL and the pre-charged dummy bit line DBL via the memory cell 12 and the reference cell 14 having been pre-charged. The reference cell 14 has a feedback unit 30, a selection transistor 28, and a reference transistor 27, having a function as a resistor during discharging of the dummy bit line DBL. The feedback unit 30 changes the gate potential of the reference transistor 27 in accordance with a change in potential during the discharging of the dummy bit line DBL.

Inventors:
TANOI Satoru (2-1-1 Katahira, Aoba-ku, Sendai-sh, Miyagi 77, 〒9808577, JP)
ENDOH Tetsuo (2-1-1 Katahira, Aoba-ku, Sendai-sh, Miyagi 77, 〒9808577, JP)
Application Number:
JP2018/038563
Publication Date:
May 09, 2019
Filing Date:
October 16, 2018
Export Citation:
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Assignee:
TOHOKU UNIVERSITY (2-1-1, Katahira Aoba-ku, Sendai-sh, Miyagi 77, 〒9808577, JP)
International Classes:
G11C11/16; G11C7/14; G11C13/00
Attorney, Agent or Firm:
DORAIT IP LAW FIRM (411 La Tour Shinjuku, 15-1 Nishishinjuku 6-chome, Shinjuku-k, Tokyo 23, 〒1600023, JP)
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