RECEIVER ARCHITECTURES UTILIZING COARSE ANALOG TUNING AND ASSOCIATED METHODS

Title:

RECEIVER ARCHITECTURES UTILIZING COARSE ANALOG TUNING AND ASSOCIATED METHODS

Document Type and Number:

WIPO Patent Application WO2004093327

Kind Code:

A3

Abstract:

Receiver architectures and associated methods are disclosed that provide initial analog coarse tuning (102) of desired channels (108) within a received signal spectrum (107), such as a set-top box signal spectrum for satellite communications. These architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry (102) allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) (106) that provides a coarse tune analog mixing signal (116). Once mixed down, the desired channel may then be fine-tuned through digital processing (104), such as through the use of a wide-band analog-to-digital converter (ADC) or a narrow-band tunable bandpass ADC.

Inventors:

KHOINI-POORFARD RAMIN (US)
KRONE ANDREW W (US)

Application Number:

PCT/US2004/010765

Publication Date:

December 29, 2005

Filing Date:

April 07, 2004

Export Citation:

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Assignee:

SILICON LAB INC (US)
KHOINI-POORFARD RAMIN (US)
KRONE ANDREW W (US)

International Classes:

H03D3/00; H03L7/18; H04N5/50; H04N7/20; (IPC1-7): H04N7/20

Foreign References:

US6912378B2	2005-06-28
US6118824A	2000-09-12
US6218972B1	2001-04-17
US6563645B2	2003-05-13
US6912378B2	2005-06-28
US6625464B1	2003-09-23
US6631255B1	2003-10-07
US6549744B2	2003-04-15
US6218972B1	2001-04-17
US5742638A	1998-04-21
US6332006B1	2001-12-18

Other References: