TECHNICAL FIELD

[0001] The present invention generally relates to a receiver for processing multi channel signals received in a VHF data exchange system (VDES) and a method thereof.

BACKGROUND

[0002] VHF Data Exchange System (VDES) is a technology for maritime communications developed by the International Association of Marine Aids to Navigation and Lighthouse Authorities (IALA) and is widely discussed at the International Telecommunications Union (ITU) and the International Maritime Organization (IMO). VDES is a digital data exchange system developed to offer a globally interoperable and commonly available maritime data communication capability for ship-to-shore, shore-to-ship, ship-to-ship, and global coverage via satellite for the safety and security at sea. It was developed primarily to address the emerging indications of overloading in the existing Automatic Identification System (AIS) and to simultaneously enable a wider seamless data exchange for e-navigation, potentially supporting the modernization of Global Maritime Distress and Safety System (GMDSS). VDES also functions to support a number of existing applications, such as radio and NavTex (Navigational Telex), electronically and automatically through an integrated system, as compared to multiple independent systems currently in use. This may streamline many documentation processes ship crew may undertake, such as weather reporting, thereby reducing the possibility of human error.

[0003] VDES for ship-to-ship communications may comprise five physical channels, namely, Automatic Identification System (AIS) 1 , AIS 2, Application Specific Message (ASM) 1 , ASM 2, and VDE 1. Each physical channel is assigned to a different frequency band in the VHF (Very High Frequency) spectrum, such as illustrated in FIG. 1. In particular, FIG. 1 shows an allocation of various frequency bands for the physical channels in VDES. These VDES physical channels are designed to cater to specific applications and offer a variety of data rates in order to maximize the capacity of the system. For instance, the 9.6 kbps (kilobits per second) AIS channels are used primarily for ship status reporting while the higher speed VDE 1 channel is used for higher capacity transmission. These five physical channels may share a common slot-based Time Division Multiple Access (TDMA) system, where each slot can only be assigned to a single ship at any one time. For a given slot, the ship has the flexibility to transmit on just one of the physical channels or it can simultaneously transmit on multiple physical channels. For example, simultaneous transmission on multiple physical channels may be referred to as a multi-channel transmission. A single-channel transmission may be considered as a special case of the multi-channel transmission. Advantages of employing a multi-channel transmission may include an increase in the achievable throughput as compared to a single-channel transmission, and diversity through the transmission of the data over multiple physical channels in different frequency bands.

[0004] At a conventional receiver, in the case of a multi-channel transmission, the signal received via each of the multiple physical channels may be independently synchronized, and then independently demodulated and decoded to produce a corresponding decoded sub-packet. A data packet may then be produced based on the decoded sub-packets. However, processing signals received via multiple physical channels in such a conventional manner has been found to suffer from various signal processing problems or inaccuracies, such as inaccuracies in synchronization of signals received via multiple physical channels, thereby negatively affecting the performance (e.g., higher signal processing error rate) of the receiver.

[0005] A need therefore exists to provide a receiver for processing multi-channel signals received in VDES and a method thereof that seek to overcome, or at least ameliorate, one or more of the deficiencies in conventional receivers in VDES, such as but not limited to, improving signal processing reliability or accuracy, such as accuracy in synchronization of signals (multi-channel signals) received via multiple physical channels, thereby resulting in an improvement in the performance (e.g., reduced signal processing error rate) of the receiver. It is against this background that the present invention has been developed. SUMMARY

[0006] According to a first aspect of the present invention, there is provided a method of processing multi-channel signals received in a VHF Data Exchange System (VDES), using at least one processor, the multi-channel signals comprising a plurality of received signals transmitted via a plurality of physical channels of the VDES, respectively, the method comprising: determining individual synchronization information for each of the plurality of received signals, respectively, to obtain a plurality of individual synchronization information; determining joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; synchronizing each of the plurality of received signals based on the joint synchronization information to obtain a plurality of synchronized signals; demodulating the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated sub-packets; and producing a data packet based on the plurality of demodulated sub-packets.

[0007] According to a second aspect of the present invention, there is provided a receiver for processing multi-channel signals received in a VHF Data Exchange System (VDES), the multi-channel signals comprising a plurality of received signals transmitted via a plurality of physical channels of the VDES, respectively, the receiver comprising: a memory; and at least one processor communicatively coupled to the memory and configured to: determine individual synchronization information for each of the plurality of received signals, respectively, to obtain a plurality of individual synchronization information; determine joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; synchronize each of the plurality of received signals based on the joint synchronization information to obtain a plurality of synchronized signals; demodulate the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated sub-packets; and produce a data packet based on the plurality of demodulated sub-packets.

[0008] According to a third aspect of the present invention, there is provided a computer program product, embodied in one or more non-transitory computer-readable storage mediums, comprising instructions executable by at least one processor to perform a method of processing multi-channel signals received in a VHF Data Exchange System (VDES), using at least one processor, the multi-channel signals comprising a plurality of received signals transmitted via a plurality of physical channels of the VDES, respectively, the method comprising: determining individual synchronization information for each of the plurality of received signals to obtain a plurality of individual synchronization information; determining joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; synchronizing each of the plurality of received signals based on the joint synchronization information to obtain a plurality of synchronized signals; demodulating the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated sub-packets; and producing a data packet based on the plurality of demodulated sub-packets.

BRIEF DESCRIPTION OF THE DRAWINGS [0009] Embodiments of the present invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:

FIG. 1 depicts an allocation of various frequency bands for various physical channels in VDES;

FIG. 2 depicts a schematic block diagram of a conventional transmitter configured to generate multi-channel signals based on a data packet for transmission (for multi channel transmission); FIG. 3 depicts a schematic block diagram of an example illustration of a Time- Division Multiple Access (TDMA) configuration or utilization for multi-channel transmission;

FIG. 4 depicts a schematic block diagram of a conventional receiver configured for processing an example multi-channel transmission (multi-channel signals) received;

FIG. 5 depicts a flow diagram of a method of processing multi-channel signals received in a VDES, according to various embodiments of the present invention;

FIG. 6 depicts a schematic block diagram of a receiver for processing multi channel signals received in a VDES, according to various embodiments of the present invention, such as corresponding to the method of processing multi-channel signals received in a VDES shown in FIG. 5;

FIG. 7 depicts a schematic drawing of a VDES for wireless communication according to various embodiments of the present invention;

FIG. 8 depicts a schematic block diagram of an example receiver for processing multi-channel signals in a VDES, according to various example embodiments of the present invention;

FIG. 9 depicts a schematic block diagram of an example configuration of a multi channel pre-processing block of the receiver, according to various example embodiments of the present invention;

FIG. 10 depicts a more detailed schematic block diagram of the example multi channel pre-processing block shown in FIG. 9, according to various example embodiments of the present invention;

FIG. 11 depicts a plot comparing the performance of a receiver with an example 2-channel joint pre-processing according to various example embodiments of the present invention with that of an example single-channel baseline pre-processing;

FIG. 12 depicts a schematic block diagram of an example configuration of the multi-channel post-processing block, according to various example embodiments of the present invention;

FIG. 13 depicts a flowchart of the multi-channel post-processing block, according to various example embodiments of the present invention; and FIG. 14 depicts a plot comparing the performance of a receiver with an example 2-channel joint post-processing according to various example embodiments of the present invention with that of an example single-channel baseline post-processing.

DETAILED DESCRIPTION

[0010] Various embodiments of the present invention provide a receiver for processing multi-channel signals received in VHF Data Exchange System (VDES) and a method thereof.

[0011] As described in the background, VDES for ship-to-ship communications comprises a plurality of physical channels, such as five physical channels, namely, Automatic Identification System (AIS) 1, AIS 2, Application Specific Message (ASM) 1, ASM 2, and VHF Data Exchange (VDE) 1. Each physical channel is assigned to a different frequency band in the VHF spectrum, such as illustrated in FIG. 1. In particular, FIG. 1 shows an allocation of various frequency bands for various physical channels in VDES. These VDES physical channels are designed to cater to specific applications and offer a variety of data rates in order to maximize the capacity of the system. For instance, the 9.6 kbps AIS channels are used primarily for ship status reporting while the higher speed VDE 1 channel is used for higher capacity transmission. These five physical channels may share a common slot- based Time Division Multiple Access (TDMA) system, where each slot may only be assigned to a single ship at any one time. For a given slot, the ship has the flexibility to transmit on just one of the physical channels or it can simultaneously transmit on multiple physical channels. For example, simultaneous transmission on multiple physical channels may be referred to as a multi-channel transmission (including multi-channel signals). A single-channel transmission may be considered as a special case of the multi-channel transmission. Advantages of employing a multi-channel transmission may include an increase in the achievable throughput as compared to a single-channel transmission, and diversity through the transmission of the data over multiple channels in different frequency bands.

[0012] FIG. 2 depicts a schematic block diagram of a conventional transmitter 200 configured to generate multi-channel signals based on a data packet for transmission (for multi-channel transmission). In the transmitter 200, a data packet p DES to be transmitted is inverse multiplexed (IMUX) into five sub-packets denoted as / IS I, / IS 2, /MSM 1, /MSM 2, and py DE ₁ . The example conventional multi-channel transmission illustrated in FIG. 2 shows that all five physical channels are being used for transmission of the data packet pw _DES . However, it will be appreciated by a person skilled in the art that the data packet may alternatively be transmitted using any combination of two or more of these five physical channels or using only a single physical channel, depending on various requirements of the transmission. At each physical channel, as shown in FIG. 2, the sub packet may be concatenated with its associated Cyclic Redundancy Check (CRC) code. The purpose of the CRC code is to enable or facilitate detection of erroneous sub-packets at the receiver. The five CRC concatenated sub-packets, denoted as CAIS 1, MAIS 2, CASM 1, 6'ASM 2, and CVDE 1, may then each be encoded and modulated according to the specifications of the corresponding physical channel to produce the signals LΆK I, VAIS 2, SASM 1, VASM 2, and VVDE 1 for transmission, as shown in FIG. 2. Example coding and modulation schemes associated or assigned to each of the five physical channels are provided in Table 1 below.

Table 1 - Example coding and modulation schemes of the corresponding channels

[0013] For example, as shown in Table 1, the ASM 1 and ASM 2 physical channels may have the flexibility of choosing either a ½ rate or ¾ rate turbo code or an uncoded mode, while the VDE 1 channel may always be protected by a turbo code of either ½ rate or ¾ rate. The VDE 1 channel may also have the option of choosing a modulation scheme of either p/4-QPSK, 8PSK or 16QAM. In addition, the VDE 1 channel may have the flexibility of using a bandwidth of either 25 kHz, 50 kHz, or 100 kHz. The options to be used for the transmission may be determined by the upper MAC layer of the transmitter and may be conveyed to the receiver via a header embedded in each sub-packet. After coding and modulation, the signals from all of the physical channels may then be transmitted simultaneously as multi-channel signals on a single time slot.

[0014] FIG. 3 depicts a schematic block diagram of an example illustration of a Time-Division Multiple Access (TDMA) configuration or utilization 300 for multi channel transmission. In the example shown in FIG. 3, Ship 1 may utilize all five physical channels (multi-channel transmission, namely, via the AIS 1, AIS 2, ASM 1, ASM 2 and VDE 1 channels) to transmit its data packet at time slot 2, Ship 2 may utilize three physical channels (multi-channel transmission, namely, via the AIS 2, ASM 1 and ASM 2 channels) to transmit its data packet at time slot 4, while Ship 3 may only utilize a single physical channel (single-channel transmission, namely, via the VDE 1 channel) to transmit its data packet at time slot 5.

[0015] FIG. 4 depicts a schematic block diagram of a conventional receiver 400 configured for processing an example multi-channel transmission (multi-channel signals) received. At the conventional receiver 400, the signal received at each physical channel, denoted by TAIS I, /'A is 2, /'ASM 1, /"ASM 2, and r DE 1, is independently synchronized without any considerations of the signals received from the other physical channels, as illustrated by the synchronization blocks (SYNC blocks) in FIG. 4. Each synchronization block may be configured to perform frame detection and timing and frequency synchronization of the corresponding physical channel. Subsequently, each individual physical channel is independently demodulated and decoded. The resultant decoded sub-packet of each physical channel, denoted by CA 1, CAB 2, CASM 1, CASM 2, and CVDE 1, is then input to the corresponding post-processing block. Again, each post-processing block is performed independently for each physical channel regardless of the other physical channels. A data packet may then be produced by multiplexing the decoded sub-packets of the multiple physical channels. However, various embodiments of the present invention identified that processing signals received via multiple physical channels in such a conventional manner may suffer from various signal processing problems or inaccuracies, such as inaccuracies in synchronization of signals received via multiple physical channels, thereby negatively affecting the performance (e.g., higher signal processing error rate) of the receiver. [0016] A post-processing technique based on symbol inversion has been previously disclosed for satellite-based AIS. In this post- processing technique, if a data packet (or a sub-packet) is detected to contain symbol errors as indicated by the CRC code, pairs of symbols having the lowest probabilities (likelihoods) may be inverted. Due to the characteristics of GMSK (Gaussian Minimum Shift Keying) modulation and NRZI (Non- Return-to-Zero-Inverted) coding, symbol errors may almost always occur in pairs of symbols that are separated by a further symbol. Therefore, a pair of symbols selected for inversion constitutes to symbols separated by a symbol. Each time a pair of symbols is inverted, the CRC code may be validated in order to determine if the data packet is now free of errors. By selecting and inverting those pairs of symbols that are most likely to be wrong, the probability of correcting an erroneous packet is increased, thus improving the performance of the receiver. In this post-processing technique, the number of pairs of symbols to be selected for inversion for error correction is predetermined regardless of the channel conditions. Various embodiments of the present invention identified that predetermining the number of pairs of symbols to be selected for inversion for error correction may be ineffective and/or inefficient. For example, in the case of relatively good channel conditions, more pairs of symbols than necessary may be selected for inversion. On the other hand, in the case of relatively bad channel conditions, insufficient pairs of symbols may be selected for inversion.

[0017] Accordingly, various embodiments of the present invention provide a receiver for processing multi-channel signals received in VDES and a method thereof that seek to overcome, or at least ameliorate, one or more of the deficiencies in conventional receiver in VDES, such as but not limited to, improving signal processing reliability or accuracy, such as accuracy in synchronization of signals (multi-channel signals) received via multiple physical channels, thereby resulting in an improvement in the performance (e.g., reduced signal processing error rate) of the receiver.

[0018] FIG. 5 depicts a flow diagram of a method 500 of processing multi-channel signals received in a VDES, using at least one processor, according to various embodiments of the present invention. The multi-channel signals comprises a plurality of received signals transmitted via a plurality of physical channels of the VDES, respectively. The method 500 comprises: determining (at 502) individual synchronization information for each of the plurality of received signals, respectively, to obtain a plurality of individual synchronization information; determining (at 504) joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; synchronizing (at 506) each of the plurality of received signals based on the joint synchronization information to obtain a plurality of synchronized signals; demodulating (at 508) the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated sub-packets; and producing (at 510) a data packet based on the plurality of demodulated sub-packets.

[0019] In various embodiments, the plurality of physical channels may be any two or more of an AIS channel, an ASM channel and a VDE channel of the VDES. In various embodiments, the plurality of physical channels may be any two or more of an AIS 1 channel, an AIS 2 channel, an ASM 1 channel, an ASM 2 channel, and a VDE 1 channel of the VDES. It will be appreciated by a person skilled in the art that the number and type of physical channels of the VDES may be determined by the International Telecommunications Union (ITU) (e.g., supported by the International Association of Marine Aids to Navigation and Lighthouse Authorities (IALA)) and form part of the ITU standard. Accordingly, for example, the plurality of physical channels may be as determined by the ITU currently or as adapted/changed in the future.

[0020] In various embodiments, the plurality of received signals are transmitted by a transmitter based on time-division multiple access (TDMA), such as described hereinbefore with reference to FIG. 3.

[0021] In various embodiments, the received multi-channel signals comprises a plurality of received signals which have been transmitted over a plurality of physical channels of the VDES, respectively. In this regard, the plurality of received signals may respectively correspond to a plurality of sub-packets modulated (and may also be coded) at a transmitter for transmission, such as described hereinbefore with reference to FIG. 2. Furthermore, the plurality of sub-packets at the transmitter for transmission may be derived (e.g., inverse multiplexed) from a data packet (or simply data) desired to be transmitted over the plurality of physical channels. In various embodiments, the plurality of received signals may be two received signals, three received signals, four received signals, or five received signals transmitted via corresponding two physical channels, three physical channels, four physical channels, or five physical channels, respectively. [0022] In relation to 502, in various embodiments, the individual synchronization information (or individual synchronization data) for a received signal refers to synchronization information determined for or in relation to that particular received signal (that is, individual in the sense of being for or belong to that particular received signal), and may comprise one or more types of synchronization information (which may also be referred to as a set of synchronization information). In particular, the individual synchronization information for a received signal may comprise any one or more types of synchronization information (set of synchronization information) that may be utilized or required for frame detection and timing and frequency synchronization in relation to the received signal with respect to the physical channel via which the received signal was transmitted. In various embodiments, the individual synchronization information, for example, may comprise a frequency offset (e.g., to be used or utilized for frequency synchronization), and a phase offset and a timing offset (e.g., to be used or utilized for timing synchronization and frame synchronization). In this regard, it will be appreciated by a person skilled in the art that various existing techniques for determining individual synchronization information (e.g., the frequency offset, the phase offset and the timing offset) for a received signal are known in the art and thus need not be described herein for clarity and conciseness.

[0023] In relation to 504, in various embodiments, the joint synchronization information (or joint synchronization data) for the plurality of received signals refers to synchronization information determined for synchronizing (to be utilized to synchronize) each of the plurality of received signals. That is, each of the plurality of received signals is synchronized based on the same set of synchronization information (which may herein be referred to as “joint synchronization information”). In this manner, the set of synchronization information for the plurality of received signals may thus be referred to as being jointly determined or decided. Similar to the individual synchronization information, the joint synchronization information may comprise one or more types of synchronization information (a set of synchronization information) that may be utilized or required for frame detection and timing and frequency synchronization in relation to the plurality of received signals with respect to the plurality of physical channels via which the plurality of received signals were transmitted. In various embodiments, the one or more types of synchronization information (set of synchronization information) in the joint synchronization information are the same as or corresponds to the one or more types of synchronization information (set of synchronization information) in the individual synchronization information. Accordingly, in various embodiments, the joint synchronization information may also comprise a frequency offset, a phase offset and a timing offset.

[0024] In relation to 506, in various embodiments and as described hereinbefore, each of the plurality of received signals may be synchronized based on the joint synchronization information (i.e., the same set of synchronization information) for frame detection and timing and frequency synchronization. In this manner, the plurality of received signals may thus be referred to as being jointly synchronized. In various embodiments and as described hereinbefore, the joint synchronization information may comprise a frequency offset, a phase offset and a timing offset, and thus each of the plurality of received signals may be synchronized based on the frequency offset, the phase offset and the timing offset. In this regard, it will be appreciated by a person skilled in the art that synchronizing a received signal based on various types of synchronization information (e.g., frequency offset, phase offset and timing offset) is known in the art and thus need not be described herein for clarity and conciseness. It will be appreciated by a person skilled in the art that the above-mentioned synchronized signals obtained may simply refer to signals that have been subjected to synchronization as described hereinbefore, but does not necessarily mean that the signals are perfectly synchronized without errors or inaccuracies.

[0025] In relation to 508, each of the plurality of synchronized signals may be demodulated with respect to a corresponding physical channel to obtain a corresponding demodulated sub-packet. For example, a synchronized signal may be demodulated based on a demodulation scheme corresponding to the modulation scheme in which the synchronized signal has been modulated at the corresponding physical channel at the transmitter before being transmitted. In various embodiments, the method 500 may further comprise decoding one or more of the plurality of synchronized signals with respect to corresponding one or more of the plurality of physical channels, respectively, to obtain one or more decoded sub-packets, in the case where the one or more synchronized signals have been coded at the corresponding physical channel at the transmitter before being transmitted. For example, a synchronized signal may be decoded based on a decoding scheme corresponding to the coding scheme in which the synchronized signal has been coded at the corresponding physical channel at the transmitter before being transmitted. Accordingly, in various embodiments, at 508, the method 500 may comprise demodulating and decoding the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated and decoded sub-packets.

[0026] In relation to 510, the data packet may be produced by multiplexing the plurality of demodulated sub-packets (or demodulated and decoded sub-packets). In this regard, the data packet produced may then be or correspond to the data packet transmitted at the transmitter.

[0027] In relation to 502, in various embodiments, the above-mentioned determining individual synchronization information for each of the plurality of received signals comprises estimating, for each of the plurality of received signals, one or more types of signal offsets for the received signal (i.e., for the respective received signal). In this regard, the individual synchronization information for the received signal may thus comprise the estimated one or more types of signal offsets for the received signal.

[0028] In various embodiments, the one or more types of signal offsets is selected from a group consisting of a frequency offset, a phase offset and a timing offset. In this regard, it will be appreciated by a person skilled in the art that various techniques for estimating various types of signal offsets, such as the frequency offset, the phase offset and the timing offset, are known in the art and thus need not be described herein for clarity and conciseness.

[0029] In relation to 504, in various embodiments, the above-mentioned determining joint synchronization information for the plurality of received signals comprises selecting one of the plurality of individual synchronization information for the plurality of received signals as the joint synchronization information. [0030] In relation to 506, in various embodiments, the above-mentioned selecting one of the plurality of individual synchronization information as the joint synchronization information is based on a plurality of signal condition information for the plurality of received signals, respectively. In various embodiments, the signal condition information for a received signal may include a noise parameter estimated for the received signal, such as a Signal to Interference plus Noise Ratio (SINR) estimated based on a preamble of the received signal. In various embodiments, such a noise parameter may also be referred to as channel interference information associated with the corresponding physical channel via which the received signal was transmitted.

[0031] In various embodiments, the above-mentioned selecting one of the plurality of individual synchronization information as the joint synchronization information is further based on feedback information, whereby the feedback information comprises a plurality of channel condition information associated with the plurality of physical channels, respectively.

[0032] In various embodiments, each of the plurality of channel condition information comprises an error information based on whether a prior demodulated sub packet demodulated with respect to the associated physical channel contains one or more errors.

[0033] In relation to 508, in various embodiments, the above-mentioned demodulating the plurality of synchronized signals comprises determining signal condition information for each of the plurality of synchronized signals, respectively, with respect to the corresponding physical channel to obtain a plurality of signal condition information.

[0034] In various embodiments, the signal condition information comprises at least one of a noise parameter and a symbol error probability parameter.

[0035] In various embodiments, the method 500 further comprises: checking each of the plurality of demodulated sub-packets for one or more errors; and correcting, for each of the plurality of demodulated sub-packets determined to include one or more errors, the demodulated sub-packet based on symbol inversion. In particular, the above-mentioned correcting the demodulated sub-packets comprises: determining a number of symbol inversion based on the signal condition information; and correcting the demodulated sub packet based on the number of symbol inversion determined.

[0036] FIG. 6 depicts a schematic block diagram of a receiver 600 for processing multi-channel signals received in a VDES, according to various embodiments of the present invention, such as corresponding to the method 500 of processing multi-channel signals received in a VDES as described hereinbefore with reference to FIG. 5 according to various embodiments. The receiver 600 comprises a memory 602 and at least one processor 604 communicatively coupled to the memory 602 and configured to: determine individual synchronization information for each of the plurality of received signals, respectively, to obtain a plurality of individual synchronization information; determine joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; synchronize each of the plurality of received signals based on the joint synchronization information to obtain a plurality of synchronized signals; demodulate the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated sub packets; and produce a data packet based on the plurality of demodulated sub-packets. It will be appreciated by a person skilled in the art that the receiver 600 may be a receiver system of the VDES, which may also be embodied as a receiver device or a receiver apparatus.

[0037] It will be appreciated by a person skilled in the art that the at least one processor 604 may be configured to perform the required functions or operations through set(s) of instructions (e.g., software modules) executable by the at least one processor 604 to perform the required functions or operations. Accordingly, as shown in FIG. 6, the receiver 600 may further comprise an individual synchronization information determinator (e.g., an individual synchronization information determining module or circuit) 606 configured to perform the above-mentioned determining (at 502) individual synchronization information for each of the plurality of received signals, respectively, to obtain a plurality of individual synchronization information; a joint synchronization information determinator (e.g., a joint synchronization information determining module or circuit) 608 configured to perform the above-mentioned determining (at 504) joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; a signal synchronizer (e.g., a signal synchronizing module or circuit) 610 configured to perform the above-mentioned synchronizing (at 506) each of the plurality of received signals based on the joint synchronization information to obtain a plurality of synchronized signals; a signal demodulator (e.g., a signal demodulator module or circuit) 612 configured to perform the above-mentioned demodulating (at 508) the plurality of synchronized signals with respect to the plurality of physical channels, respectively, to obtain a plurality of demodulated sub-packets; and a data packet producer (e.g., a data packet producing module or circuit) 614 configured to perform the above-mentioned producing (at 510) a data packet based on the plurality of demodulated sub-packets.

[0038] It will be appreciated by a person skilled in the art that the above-mentioned modules are not necessarily separate modules, and two or more modules may be realized by or implemented as one functional module (e.g., a circuit or a software program) as desired or as appropriate without deviating from the scope of the present invention. For example, two or more of the above-mentioned individual synchronization information determinator 606, joint synchronization information determinator 608, signal synchronizer 610, signal demodulator 612 and data packet producer 614 may be realized (e.g., compiled together) as one executable software program (e.g., software application or simply referred to as an “app”), which for example may be stored in the memory 602 and executable by the at least one processor 604 to perform the functions/operations as described herein according to various embodiments.

[0039] In various embodiments, the receiver 600 corresponds to the method 500 as described hereinbefore with reference to FIG. 5, therefore, various functions or operations configured to be performed by the least one processor 604 may correspond to various steps of the method 500 described hereinbefore according to various embodiments, and thus need not be repeated with respect to the receiver 600 for clarity and conciseness. In other words, various embodiments described herein in context of the method 500 are analogously valid for the corresponding receiver 600, and vice versa. [0040] For example, in various embodiments, the memory 602 may have stored therein the individual synchronization information determinator 606, the joint synchronization information determinator 608, the signal synchronizer 610, the signal demodulator 612, and/or the data packet producer 614, which respectively correspond to various steps of the method 500 as described hereinbefore according to various embodiments, which are executable by the at least one processor 604 to perform the corresponding functions/operations as described herein.

[0041] FIG. 7 depicts a schematic drawing of a VDES 700 for wireless communication according to various embodiments of the present invention. The VDES 700 comprises a transmitter 702 configured to generate multi-channel signals based on a data packet for transmission and a receiver 600 configured to receive the multi-channel signals and process the multi-channel signals received to produce the data packet, whereby the receiver 600 may be configured as described hereinbefore with reference to FIG. 6 according to various embodiments. For example, the transmitter 702 may be a conventional transmitter capable of generating multi-channel signals based on a data packet for transmission in a VDES, such as described hereinbefore with reference to FIG. 2. It will be appreciated by a person skilled in the art that the VDES 700 may include any number of transmitters and any number of receivers, as desired or as appropriate.

[0042] A computing system, a controller, a microcontroller or any other system providing a processing capability may be provided according to various embodiments in the present disclosure. Such a system may be taken to include one or more processors and one or more computer-readable storage mediums. For example, the receiver 600 described hereinbefore may include a processor (or controller) 604 and a computer- readable storage medium (or memory) 602 which are for example used in various processing carried out therein as described herein. A memory or computer-readable storage medium used in various embodiments may be a volatile memory, for example a DRAM (Dynamic Random Access Memory) or a non-volatile memory, for example a PROM (Programmable Read Only Memory), an EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM), or a flash memory, e.g., a floating gate memory, a charge trapping memory, an MRAM (Magnetoresistive Random Access Memory) or a PCRAM (Phase Change Random Access Memory).

[0043] In various embodiments, a “circuit” may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in an embodiment, a “circuit” may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g., a microprocessor (e.g., a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A “circuit” may also be a processor executing software, e.g., any kind of computer program, e.g., a computer program using a virtual machine code, e.g., Java. Any other kind of implementation of the respective functions which will be described in more detail below may also be understood as a “circuit” in accordance with various alternative embodiments. Similarly, a “module” may be a portion of a system according to various embodiments in the present invention and may encompass a “circuit” as above, or may be understood to be any kind of a logic-implementing entity therefrom.

[0044] Some portions of the present disclosure are explicitly or implicitly presented in terms of algorithms and functional or symbolic representations of operations on data within a computer memory. These algorithmic descriptions and functional or symbolic representations are the means used by those skilled in the data processing arts to convey most effectively the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities, such as electrical, magnetic or optical signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

[0045] Unless specifically stated otherwise, and as apparent from the following, it will be appreciated that throughout the present specification, discussions utilizing terms such as “determining”, “synchronizing”, “demodulating”, “decoding”, “producing”, “selecting”, “correcting”, “transmitting”, “receiving”, “estimating”, “performing” or the like, refer to the actions and processes of a computer system, or similar electronic device, that manipulates and transforms data represented as physical quantities within the computer system into other data similarly represented as physical quantities within the computer system or other information storage, transmission or display devices.

[0046] The present specification also discloses a system (e.g., which may also be embodied as a device or an apparatus) for performing the operations/functions of the methods described herein. Such a system may be specially constructed for the required purposes, or may comprise a general purpose computer or other device selectively activated or reconfigured by a computer program stored in the computer. The algorithms presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose machines may be used with computer programs in accordance with the teachings herein. Alternatively, the construction of more specialized apparatus to perform the required method steps may be appropriate.

[0047] In addition, the present specification also at least implicitly discloses a computer program or software/functional module, in that it would be apparent to the person skilled in the art that the individual steps of the methods described herein may be put into effect by computer code. The computer program is not intended to be limited to any particular programming language and implementation thereof. It will be appreciated that a variety of programming languages and coding thereof may be used to implement the teachings of the disclosure contained herein. Moreover, the computer program is not intended to be limited to any particular control flow. There are many other variants of the computer program, which can use different control flows without departing from the spirit or scope of the invention. It will be appreciated by a person skilled in the art that various modules described herein (e.g., the individual synchronization information determinator 606, the joint synchronization information determinator 608, the signal synchronizer 610, the signal demodulator 612, and/or the data packet producer 614) may be software module(s) realized by computer program(s) or set(s) of instructions executable by a computer processor to perform the required functions, or may be hardware module(s) being functional hardware unit(s) designed to perform the required functions. It will also be appreciated that a combination of hardware and software modules may be implemented.

[0048] Furthermore, one or more of the steps of a computer program/module or method described herein may be performed in parallel rather than sequentially. Such a computer program may be stored on any computer readable medium. The computer readable medium may include storage devices such as magnetic or optical disks, memory chips, or other storage devices suitable for interfacing with a general purpose computer. The computer program when loaded and executed on such a general-purpose computer effectively results in an apparatus that implements the steps of the methods described herein.

[0049] In various embodiments, there is provided a computer program product, embodied in one or more computer-readable storage mediums (non-transitory computer- readable storage medium), comprising instructions (e.g., the individual synchronization information determinator 606, the joint synchronization information determinator 608, the signal synchronizer 610, the signal demodulator 612, and/or the data packet producer 614) executable by one or more computer processors to perform a method 500 of processing multi-channel signals received in a VDES as described hereinbefore with reference to FIG. 5. Accordingly, various computer programs or modules described herein may be stored in a computer program product receivable by a system therein, such as the receiver 600 as shown in FIG. 6, for execution by at least one processor 604 of the receiver 600 to perform the required or desired functions.

[0050] The software or functional modules described herein may also be implemented as hardware modules. More particularly, in the hardware sense, a module is a functional hardware unit designed for use with other components or modules. For example, a module may be implemented using discrete electronic components, or it can form a portion of an entire electronic circuit such as an Application Specific Integrated Circuit (ASIC). Numerous other possibilities exist. Those skilled in the art will appreciate that the software or functional module(s) described herein can also be implemented as a combination of hardware and software modules.

[0051] It will be appreciated by a person skilled in the art that the terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. [0052] In order that the present invention may be readily understood and put into practical effect, various example embodiments of the present invention will be described hereinafter by way of examples only and not limitations. It will be appreciated by a person skilled in the art that the present invention may, however, be embodied in various different forms or configurations and should not be construed as limited to the example embodiments set forth hereinafter. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0053] FIG. 8 depicts a schematic block diagram of an example receiver 800 for processing multi-channel signals (which may also be referred to herein as a multi-channel receiver) in a VDES according to various example embodiments of the present invention. As shown in FIG. 8, the receiver 800 may comprise a multi-channel pre-processing block (or multi-channel pre-processing module or circuit) 803 and a multi-channel post processing block (or multi-channel post-processing module or circuit) 805. In various example embodiments, the multi-channel pre-processing block 803 may be configured to gather or obtain (e.g., determine) all the initial detection and synchronization information (e.g., corresponding to the “individual synchronization information” described hereinbefore according to various embodiments) across the multiple physical channels, as well as feedback information received from the multi-channel post-processing block 805, in order to jointly determine or decide for the frame detection and timing and frequency synchronization of the multiple physical channels. In various example embodiments, the multi-channel pre-processing block 803 may also be configured to gather or obtain (e.g., determine) a plurality of signal condition information for the plurality of received signals, respectively. For example, the signal condition information for a received signal may include a noise parameter estimated for the received signal, such as a SINR estimated based on a preamble of the received signal. For example, such a noise parameter estimated for the received signal may thus indicate a condition (e.g., a noise level) of the corresponding physical channel via which the received signal was transmitted. In various example embodiments, the signal condition information (e.g., including a plurality of noise parameters for the plurality of received signals, respectively) may be fed forward to multi-channel post-processing block 805. Furthermore, in various example embodiments, the multi-channel post-processing block 805 may improve the efficiency of the post processing by exploiting knowledge of the condition of each physical channel. The multi channel pre-processing block 803 and the multi-channel post-processing block 805 will be described in more detail below, according to various example embodiments of the present invention.

Multi-Channel Pre-Processing Block 803

[0054] In multi-channel transmission, in various example embodiments, any combination of two or more of the physical channels may be used to transmit the data. Without loss of generality and without limitation, various example embodiments will now be described assuming that all physical channels (i.e., all of the five physical channels as described hereinbefore) are used for transmission, such as illustrated in FIG. 2. In various example embodiments, the multi-channel signals (LΆB I, VAIS 2, .VASM I , .VASM 2, and _* S"VDE 1) to be transmitted are derived from the same source (e.g., a data packet /?VDES desired to be transmitted) and are intended for the same destination (e.g., the same receiver). As a result, any timing and frequency offset due to a mismatch in the crystal clock between the transmitter and receiver will be similarly experienced by all the signals (i.e., the multi-channel signals). On the other hand, various example embodiments note that since each physical channel may be assigned to a different carrier frequency and possibly a different bandwidth (e.g., for the VDE 1 channel), the signal received (/'AIS 1, /'A is 2, /'ASM 1, /"ASM 2, and rvDE 1) for each physical channel may be impaired differently as compared to other physical channels. These impairments may, for example, include adjacent frequency interferences and noise, and may impact the signal processing accuracy, such as the accuracy of the frame detection and offset estimation during synchronization. Accordingly, various example embodiments provide a multi-channel pre-processing block 803 for improving signal processing reliability or accuracy, such as the accuracy of the frame detection and offset estimation during synchronization.

[0055] FIG. 9 depicts a schematic block diagram of an example configuration of the multi-channel pre-processing block 803 according to various example embodiments of the present invention. As shown, the multi-channel pre-processing block (or multi channel pre-processing module or circuit) 803 comprises a plurality of individual synchronization information blocks (e.g., modules or circuits) 906-1, 906-2, 906-3, 906- 4, 906-5 (e.g., corresponding to the “individual synchronization information determinator” 606 described hereinbefore according to various embodiments) configured to determine individual synchronization information for each of the plurality of received signals, respectively, to obtain a plurality of individual synchronization information; a pre-processing controller (e.g., module or circuit) 908 (e.g., corresponding to the “joint synchronization information determinator” 608 described hereinbefore according to various embodiments) configured to determine joint synchronization information for the plurality of received signals based on the plurality of individual synchronization information; and a plurality of signal synchronizing blocks (e.g., modules or circuits) 910-1, 910-2, 910-3, 910-4, 910-5 (e.g., corresponding to the “signal synchronizer” 610 described hereinbefore according to various embodiments) configured to synchronize each of the plurality of received signals, respectively, based on the joint synchronization information to obtain a plurality of synchronized signals. In various example embodiments, the pre-processing controller 908 may be configured to determine the joint synchronization information (e.g., select one of the plurality of individual synchronization information as the joint synchronization information) based on a plurality of signal condition information for the plurality of received signals, respectively. For example, the signal condition information for a received signal may include a noise parameter (e.g., SINR) for the received signal estimated based on a preamble of the received signal. As shown in FIG. 9, the plurality of synchronized signals may then be demodulated (or demodulated and decoded) to obtain a plurality of demodulated sub packets (or demodulated and decoded sub-packets). In the example multi-channel pre processing block 803, the number of individual synchronization information blocks 906- 1, 906-2, 906-3, 906-4, 906-5 provided and the number of signal synchronizing blocks 910-1, 910-2, 910-3, 910-4, 910-5 provided may correspond to (e.g., same as) the number of physical channels.

[0056] Accordingly, in various example embodiments, after the initial detection and synchronization process of each individual channel performed by each individual synchronization information block 906-1, 906-2, 906-3, 906-4, 906-5, all the synchronization information (e.g., the plurality of individual synchronization information for the plurality of received signals), as well as the reliability information (e.g., corresponding to the “signal condition information” for the plurality of received signals and/or the “feedback information” described hereinbefore according to various embodiments) may be fed to the pre-processing controller 908 to make a joint determination or decision for the frame, timing and frequency synchronization (e.g., to determine a joint synchronization information for the plurality of received signals). In various example embodiments, such a joint determination may be configured in order to ascertain the most accurate estimation amongst the multiple physical channels, or be implemented as a joint estimation based on the plurality of received signals. In this regard, one of the plurality of individual synchronization information (e.g., the one considered or determined to be the most accurate or reliable) may be selected for the plurality of received signals as the joint synchronization information. In various other example embodiments, other techniques for determining or estimating the joint synchronization information based on the plurality of individual synchronization information may be employed as desired or as appropriate, such as based on a trade-off between system complexity and performance. In addition, in various example embodiments, such a joint determination may be further based on (or aided by) the feedback information from the multi-channel post-processing block 805 providing channel condition information associated with the plurality of physical channels, such as based on the success or failure of the CRC check using an iterative process to achieve refined synchronization and improved demodulation/decoding results. The synchronized signal of each individual physical channel may then be passed to the corresponding demodulation and decoding blocks (e.g., modules or circuits).

[0057] By way of an example only for illustrative purpose and without limitation, assuming that the VDE 1 and ASM 1 channels are used to transmit a data packet. For example, the VDE 1 channel may experience a high level of adjacent frequency interference while the ASM 1 channel may be relatively free of any interference. As a result, the individual synchronization information determined (e.g., frequency offset, phase offset and timing offset estimated) from the VDE 1 channel may not be reliable (e.g., determined by a metric based on the correlation of received signal (e.g., correlation peak value) with preamble) and may fluctuate significantly while the individual synchronization information determined (e.g., frequency offset, phase offset and timing offset estimated) from the ASM 1 channel may be relatively more reliable. In this case, in various example embodiments, the pre-processing controller 908 may be configured to select the individual synchronization information determined (e.g., offsets estimated) from the ASM 1 channel to be used to synchronize the received signals on both the VDE 1 and ASM 1 channels (i.e., selected as the joint synchronization information for both received signals). Furthermore, in various example embodiments, if the multi-channel pre-processing block 803 determines that both physical channels experience the same or similar interferences (e.g., within a predetermined similarity or difference threshold), it may use the feedback information (e.g., the channel condition information associated with the physical channels), such as the result of the CRC check on the received signals from the physical channels, from the post-processing block to select the individual synchronization information from one of the physical channels (e.g., the individual synchronization information associated with the physical channel deemed have the least error). For instance, if the received signal on the ASM 1 channel is decoded error-free while the received signal on the VDE 1 channel experienced errors (e.g., CRC check failed), the multi-channel pre-processing block 803 may then be configured to select the individual synchronization information associated with the ASM 1 channel may then be selected to be the joint synchronization information for the VDE 1 and ASM 1 channels, that is, to be used for synchronizing both the received signals with respect to the VDE 1 and ASM 1 channels.

[0058] FIG. 10 depicts a more detailed schematic block diagram of the example multi-channel pre-processing block 803 shown in FIG. 9, according to various example embodiments of the present invention. As shown in FIG. 10, in various example embodiments, the plurality of individual synchronization information blocks 906-1, 906- 2, 906-3, 906-4, 906-5 shown in FIG. 9 may be implemented as a plurality of correlators. Accordingly, the plurality of correlators 906-1, 906-2, 906-3, 906-4, 906-5 may be configured to determine individual synchronization information for each of the plurality of received signals, respectively, to output a plurality of individual synchronization information, which are fed into the pre-processing controller 908. The pre-processing controller 908 may comprise a joint packet detector (e.g., module or circuit) 908-1, a joint frequent offset estimator (e.g., module or circuit) 908-2 and a joint residual frequency offset estimator (e.g., module or circuit) 908-3. The joint packet detector 908-1 may be configured to determine or estimate the joint timing offset and the joint phase offset (e.g., based on a frame synchronization technique) for the plurality of received signals based on the plurality of individual synchronization information received. The joint frequency offset estimator 908-2 may be configured to determine or estimate the joint frequency offset for the plurality of received signals based on the plurality of individual synchronization information received. In various example embodiments, the joint frequency offset estimator 908-2 may include Doppler shift estimation. In this regard, the joint timing offset, the joint phase offset and the joint frequency offset refer to the timing offset, the phase offset and the frequency offset determined or estimated (e.g., selected as described hereinbefore according to various embodiments) for synchronizing the plurality of received signals. Accordingly, the joint synchronization information as described hereinbefore according to various embodiments may include the joint timing offset, the joint phase offset and the joint frequency offset. The joint residual frequency offset estimator may be configured to perform a residual frequency offset estimation and compensation (which may also be referred to as frequency tracking) jointly for the plurality of received signals (which may be referred to as a joint residual frequency offset estimation and compensation) based on the plurality of individual synchronization information received from the plurality of correlators 906-1, 906-2, 906-3, 906-4, 906-5, after the timing synchronization and frequency offset compensation. In various example embodiments, the pre-processing controller 908 may be further configured to receive feedback information, such as from the multi-channel post-processing block 805. For example, the pre-processing controller 908 may receive CRC feedbacks that may serve as a criteria for selecting or weighting while performing joint synchronization information estimation based on the reliability of each individual channel inputs (e.g., based on the plurality of channel condition information associated with the plurality of physical channels, respectively).

[0059] Accordingly, in various example embodiments, the multi-channel pre processing block 803 may be configured to receive initial synchronization information (e.g., corresponding to the “plurality of independent synchronization information” as described hereinbefore according to various embodiments), such as in relation to timing, frequency and frame from all individual physical channels, as well as feedback information from the multi-channel post-processing block 805, such as error information relating to demodulated sub-packets with respect to the physical channels (e.g., CRC-pass or fail information).

[0060] FIG. 11 depicts a plot comparing the performance of a receiver with an example 2-channel joint pre-processing (corresponding to the multi-channel pre processing block 803) according to various example embodiments of the present invention with that of an example single-channel baseline pre-processing. In particular, the performance gain achieved with the example 2-channel joint pre-processing over the example single-channel baseline pre-processing can be clearly observed. In the example 2-channel joint pre-processing, two separate VDE channels (separated in the frequency domain) of 25 kHz bandwidth each transmitting different data simultaneously from the same source were performed. For the example single-channel baseline pre-processing, a single VDE channel transmitting over either a 25 kHz bandwidth or a 50 kHz bandwidth was performed. Timing and frequency synchronization and tracking were performed in each of the example 2-channel joint pre-processing and the example single-channel baseline pre-processing. It can be observed that for the example single-channel baseline pre-processing, there is no difference in performance between the 25 kHz bandwidth and the 50 kHz bandwidth. However, by exploiting the characteristics in the multi-channel transmission, a gain of 2 to 3 dB over the single-channel baseline can be achieved with the joint multi-channel pre-processing. Thus, the technical advantages of joint multi channel pre-processing according to various example embodiments of the present invention is clearly evident and has been demonstrated.

Multi-Channel Post-Processing Block 805

[0061] In various example embodiments, the Signal to Interference plus Noise Ratio (SINR) (e.g., corresponding to the “noise parameter” described hereinbefore according to various embodiments) may be estimated from the Error Vector Magnitude (EVM) during the demodulation process for each physical channel. In various example embodiments, as described hereinbefore, the SINR may alternatively or additionally be estimated by the multi-channel pre-processing block 803 and fed forward to multi-channel post-processing block 805. This SINR value may then be used to determine the quality of each physical channel and may be fed to the multi-channel post-processing block 805. In various example embodiments, higher SINR values constitutes a better channel quality. Furthermore, in various example embodiments, probability information about the decoded symbols, for example, either from the turbo decoder output or from the demodulator output in the case of no coding, may be used by the multi-channel post processing block 805 in order to determine which symbols are likely to be in error (e.g., corresponding to the “symbol error probability parameter” described hereinbefore according to various embodiments).

[0062] FIG. 12 depicts a schematic block diagram of an example configuration of the multi-channel post-processing block 805 according to various example embodiments of the present invention, and FIG. 13 depicts a flowchart of the multi-channel post processing block 805 according to various example embodiments of the present invention. As shown in FIG. 12, the multi-channel post-processing block (or multi channel post-processing module or circuit) 805 comprises a plurality of error checking blocks (or modules or circuits) 1216-1, 1216-2, 1216-3, 1216-4, 1216-5 configured to check each of the plurality of demodulated sub-packets (or demodulated and decoded sub-packets), respectively, for one or more errors; an error correction parameter determinator (or error correction parameter determining module or circuit) 1220 (which may also be referred to as a post-processing controller) configured to determine a number of symbol inversion (error correction parameter) based on the signal condition information, and a plurality of error correcting blocks (or modules or circuits) 1218-1, 1218-2, 1218-3, 1218-4, 1218-5 configured to correct, for each of the plurality of demodulated sub-packets determined to include one or more errors, the respective demodulated sub-packet based on symbol inversion. In particular, in correcting the demodulated sub-packet, the error correction parameter determinator 1220 may be configured to determine the number of symbol inversion based on the signal condition information (e.g., the noise parameter and/or the symbol error probability parameter described hereinbefore according to various embodiments); and the error correcting block may be configured to correct the demodulated sub-packet based on the number of symbol inversion determined from the error correction parameter determinator 1220 to obtain a corresponding corrected sub-packet. It will be appreciated by a person skilled in the art that the above-mentioned corrected sub-packet obtained may simply refer to a sub-packet that have been subjected to error correction as described hereinbefore, but does not necessarily mean that the signals are perfectly corrected without errors or inaccuracies. [0063] Accordingly, in various example embodiments, after the demodulation and decoding process, the decoded sub-packets CAIS I, CAIS 2, CASM 1, CASM 2, and CVDE 1, may be checked for errors by the plurality of error checking blocks 1216-1, 1216-2, 1216-3, 1216-4, 1216-5 using the corresponding embedded CRC (cyclic redundancy check) code. The status (or result) of the error check (e.g., CRC check) may then be passed to the post processing controller (e.g., corresponding to the error correction parameter determinator described hereinbefore) 1220, which represents the “brain” of the multi-channel post processing block 805. For those sub-packets which passed the error check, no further processing (i.e., no further correction) of the sub-packets is required. For those sub packets that failed the error check, the post-processing controller 1220 may obtain their corresponding signal condition information, and based on these information, determine the number of symbols for symbol inversion for each erroneous sub-packet. For example, the number of symbol inversion may be denoted by XAIS 1, VAIS 2, XASM 1, XASM 2, and XVDE 1. In various example embodiments, if the signal condition information associated with the sub-packet signal is good (e.g., satisfies a predetermined signal condition or threshold, such as high SINR values and high symbol probabilities), then fewer number of symbol inversion may be assigned to correct that sub-packet and vice versa.

[0064] In various example embodiments, in the case when the same data are transmitted across the channels, a more effective symbol inversion post-processing may be achieved by applying the symbol inversion only on the conflicting symbols between the two decoding streams, in order to speed up the process. For instance, if there are three conflicting symbols identified between the two streams, symbol inversion post processing may be performed on these three symbols.

[0065] In various example embodiments, after the error correction by the plurality of error correcting blocks 1218-1, 1218-2, 1218-3, 1218-4, 1218-5 (e.g., the symbol inversion) is completed, the corrected sub-packets may be checked again for any further errors. This process may be repeated again for those sequences that are still erroneous with the number of symbol inversion re-allocated accordingly (e.g., determined in the same manner as described above). In various example embodiments, this iterative process may end if all sequences are correctly decoded or that a maximum number of iterations is reached.

[0066] In various example embodiments, there may be constraint(s) to the complexity for the multi-channel post-processing block 805, and the post-processing controller 1220 may be configured to assign the number of symbol inversion appropriately to each failed sub-packet such that predetermined constraint(s) is not violated. By way of example only and without limitation, the predetermined constraint(s) may include the maximum number of allowable symbol inversion or the time required to complete the post processing, or both.

[0067] By way of an example only and without limitation, assuming that VDE 1, ASM 1, and ASM 2 channels are used to transmit a data packet and the maximum allowable number of symbol inversion is six. The received signal on the VDE 1 channel may be correctly decoded and hence may not be involved in the post-processing. Both signals on the ASM 1 and ASM 2 channels may have failed the error check (e.g., CRC check). The signal on ASM 1 channel exhibits a higher SINR value as compared to the signal on ASM 2 channel. In this case, the post-processing controller 1220 may be configured to assign two inversion symbols to the received signal on the ASM 1 channel and four inversion symbols to the received signal on the ASM 2 channel. In this regard, assigning more inversion symbols to the received signal on the ASM 2 channel may increase the likelihood of being able to correct the erroneous symbols as a lower SINR value leads to more symbol errors. In this regard, the complexity and performance of the multi-channel post-processing may be dependent on the number of pairs of symbols selected for inversion, which constitutes a design parameter for the post-processing technique. For example, bad channel conditions may result in more erroneous symbols such that a higher number of symbol inversion in the post-processing may increase the likelihood of error correction. However, this is also increase the complexity of the post processing. On the other hand, such a high number of symbol inversion may be unnecessary in good channel conditions since there may be fewer erroneous symbols. Compare to the conventional post-processing technique as discussed in the background, the number of symbol inversion is fixed and is likely to be evenly distributed among the channels, e.g., two symbol inversion for each channel. Hence, for example, based on such a conventional post-processing technique, the likelihood of being able to correct the symbol errors on ASM2 channel is significantly lower.

[0068] Accordingly, in various example embodiments, the multi-channel post processing block 805 may be configured to receive, with respect to all individual physical channels, respective signal condition information (e.g., comprising a noise parameter, such as the estimated SINR value based on the EVM from the demodulation, and/or a symbol error probability parameter, such as the estimated probability (likelihood) of the decoded symbol from the turbo decoding).

[0069] In various example embodiments, during the course of symbol inversion, the sub-packet may be checked for errors using the embedded CRC code. If the sub-packet still fails the CRC check after all the symbols have been inverted, the sub-packet may be discarded as shown in FIG. 12. If so, a request for retransmission of that sub-packet may be initiated. All the passed sub-packets will then be multiplexed to obtain the data packet. For example, the data packet is deemed to be complete once all its sub-packets are correctly received.

[0070] FIG. 14 depicts a plot comparing the performance of a receiver with an example 2-channel joint post-processing (e.g., corresponding to the multi-channel post processing block 805) according to various example embodiments of the present invention with that of an example single-channel baseline post-processing. In particular, the performance gain achieved with the example 2-channel joint post-processing over the single-channel baseline post-processing can be clearly observed. In the example 2- channel joint post-processing, the same data is assumed to be transmitted simultaneously on both AIS 1 and AIS 2 channels. The example 2-channel joint post-processing entails an 8-bit inversion algorithm guided by the difference of the two decoded streams from the two AIS channels, as well as the bits’ soft information in the form of the log- likelihood ratio (LLR) metric. For the example single-channel baseline post-processing, a single AIS channel (either AIS 1 or AIS 2) is assumed, where the same 8-bit inversion algorithm was invoked and is guided only by the bits’ LLR metric. It can be observed that there is 1 dB performance gain achieved in the multi-channel case with joint post processing according to various example embodiments over the single-channel case. Furthermore, closer inspection reveals that the bit flipping algorithm in a single channel case does not exhibit any significant performance improvement as compared to one without any bit flipping (AIS baseline). Performance gain by bit inversion may only be achieved by exploiting the properties in a multi-channel transmission. Thus, the technical advantages of multi-channel post-processing according to various example embodiments of the present invention is clearly evident and has been demonstrated.

[0071] Accordingly, the pre-processing and/or post-processing techniques according to various example embodiments of the present invention have a number of technical advantages, such as but not limited to, one or more of the following:

• various example embodiments are not limited to post-processing with symbols inversion, but include both pre-processing and post-processing technical solutions;

• various example embodiments provide a multi-channel post-processing technique that is applicable to multi-channel reception, as opposed to a single-channel reception in conventional post-processing techniques;

• various example embodiments provide a multi-channel post-processing technique having design parameter(s) (e.g., the number of symbols for inversion) that is adaptable according to the channel conditions of all the physical channels (e.g., by the post-processing controller), as opposed to a fixed pre-determined value in conventional post-processing techniques;

• various example embodiments provide a multi-channel pre-processing technique across multi-channels, which may refer to joint detection and synchronization, in terms of timing, frequency and frame;

• various example embodiments provide a multi-channel transmission which may refer to transmitting the same data in dual AIS/ASM channels; or transmitting different data in dual AIS/ASM channels; and

• in the case the same data are transmitted in dual AIS/ASM channels, more effective symbols inversion post-processing according to various example embodiments may be achieved by applying inversion only on the difference of the two decoding streams, to speed up the process. [0072] Accordingly, various example embodiments advantageously improve the detection and synchronization accuracy by providing a joint signal detection and synchronization mechanism across multi-channels in VDES. Furthermore, various example embodiments advantageously improve the bit error rate performance of the receiver by providing an additional error correction capability. Various example embodiments are applicable to multi-channel cases and are simple in implementation. [0073] According to various example embodiments, there is provided multi-channel pre-processing and post-processing modules which exploit the knowledge of the signal information and condition of each physical channel of the VDES. For example, knowledge may include the estimated timing and frequency offsets from the synchronization, EVM from the synchronization process in the pre-processing block 803 and/or the demodulation process in the post-processing block 805, and symbol probabilities from the turbo decoder and CRC check information from data packet.

[0074] According to various example embodiments, there is provided a joint detection and synchronization technique for VDES multi-channel transmission which gathers all the initial detection and synchronization information across the multiple channels, as well as the feedback information from the multi-channel post-processing block in order to jointly make decisions for the frame detection, timing and frequency synchronization of the multiple channels.

[0075] According to various example embodiments, there is provided an improved post-processing management that adapts the number of symbol inversions across the multiple channels by taking into consideration the signal condition of all the channels in terms of the SINR in order to improve the overall error correction success rate.

[0076] According to various example embodiments, in the case when the same data is transmitted across the multiple channels, a more effective symbol inversion post processing can be achieved by applying inversion only on the difference between the two decoding streams, in order to speed up the process.

[0077] While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.