CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a Continuation-In-Part of Application Serial No. 13/775,282, filed 25 February 2013 ("Parent Application"), which is a Continuation-In-Part of Application Serial No. 13/033,098, filed 23 February 2011 ("Related Application /"), which is in turn related to Provisional Application Serial Number 61/316,299, filed 22 March 2010 ("Parent Provisional"), and hereby claims benefit of the filing date thereof pursuant to 37 CFR § 1.78(a)(4). The Parent Application is also a Continuation-In-Part of Application Serial No. 12/885,517, filed 19 September 2010 ("Related Application 2"), which is also in turn related to the Related Provisional, and hereby claims benefit of the filing date thereof pursuant to 37 CFR § 1.78(a)(4). Collectively, all of the above shall be hereinafter referred to as comprising "Related References". The subject matter of all of the Related References, each in its entirety, is expressly incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

[0002] The present invention relates generally to ultra-wideband communication systems, and, in particular, to a receiver for use in an ultra-wideband communication system.

2. Description of the Related Art.

[0003] In general, in the descriptions that follow, we will italicize the first occurrence of each special term of art which should be familiar to those skilled in the art of ultra-wideband (" UWB") communication systems. In addition, when we first introduce a term that we believe to be new or that we will use in a context that we believe to be new, we will bold the term and provide the definition that we intend to apply to that term. In addition, throughout this description, we will sometimes use the terms assert and negate when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, we may refer to the mutually exclusive boolean states as logic_0 and logic_l . Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.

[0004] In general, in an ultra-wideband ("UWB") communication system, a series of special processing steps are performed by a UWB transmitter to prepare payload data for transmission via a packet-based UWB channel. Upon reception, a corresponding series of reversing steps are performed by a UWB receiver to recover the data payload. Details of both series of processing steps are fully described in IEEE Standards 802.15.4 ("802.15.4") and 802.15.4a ("802.15.4a"), copies of which are submitted herewith and which are expressly incorporated herein in their entirety by reference. As is known, these Standards describe required functions of both the transmit and receive portions of the system, but specify implementation details only of the transmit portion of the system, leaving to implementers the choice of how to implement the receive portion.

[0005] One or more of us have developed certain improvements for use in UWB communication systems, which improvements are fully described in the following pending applications or issued patents, all of which are expressly incorporated herein in their entirety:

[0006] "A Method and Apparatus for Generating Codewords", US 7, 787,544, issued 31 July 2010;

[0007] "A Method and Apparatus for Generating Codewords", Application Serial No. 11/309,222, filed 13 July 2006, now abandoned;

[0008] "A Method and Apparatus for Transmitting and Receiving Convolutionally Coded Data", US 7,636,397, issued 22 December 2009;

[0009] "A Method and Apparatus for Transmitting and Receiving Convolutionally Coded Data", Application Serial No. 12/590, 124, filed 3 November 2009, and the Issue Fee on which was paid on 11 December 2012; and

[0010] "Convolution Code for Use in a Communication System", Application Serial No. 13/092, 146, filed 21 April 2011.

[0011] One particular problem in multi-path, spread-spectrum systems, including UWB, is channel- induced noise present in the received signal. One common technique for significantly reducing the noise level relative to the receive level is to develop, during reception of a training sequence portion of the preamble of each transmitted packet, an estimate of the channel impulse response ("CIR"). Following detection in the received packet of the start-of-frame delimiter ("SFD"), the best CIR estimate is reversed in time and the complex conjugate is developed. This conjugate CIR estimate is thereafter convolved with the payload portion of the packet using a channel matched filter ("CMF'). Shown in Fig. 1 is a UWB receiver 10 adapted to operate in this manner. As is known, the signal received via an antenna 12 is continuously conditioned by a filter 14. During reception of the training sequence, channel estimator 16 develops from the conditioned signal the conjugate CIR estimate. During reception of the payload data, detector 18 employs a CMF (not shown) to convolve the conditioned signal with the conjugate CIR estimate, thereby significantly improving the signal-to-noise ratio ("SNR") and facilitating recovery of the payload data. See, also, "Efficient Back-End Channel Matched Filter (CMF)", US 7,349,461, issued 25 March 2008. [0012] As noted in 802.15.4a, §5.5.7.1, "UWB devices that have implemented optional ranging support are called ranging-capable devices (RDEVs)." (Emphasis in original.) For certain applications, such RDEVs are commonly implemented in the form of a relatively compact, autonomous radio-frequency identification ("RFID") tag or the like. Due to the small fonn factor and limited power supply, it is especially important to select circuit implementations that provide maximum performance at minimum power. Unfortunately, in known implementations of the UWB receiver, improvements in perfonnance usually come at the expense of power. For example, it is known that a rake filter provides good performance in multi-path, spread-spectrum systems such as UWB. See, e.g., slide 21 of "The ParthusCeva Ultra Wideband PFTY Proposal", IEEE P802.15 Working Group for Wireless Personal Area Networks, March 2003, a copy of which is submitted wherewith and which is expressly incorporated herein in its entirety by reference. However, known rake filter implementations tend to consume significantly more power than other prior art techniques.

[0013] In ranging systems, as in other RF systems, the receiver must coordinate its internal operation to the signal being received from the transmitter. In general, the receiver must achieve synchronism with the received carrier signal, a process referred to as carrier recovery. In addition, the receiver must further achieve synchronism with the infonnation signals superimposed on the carrier, a process referred to as timing recovery. We submit that prior art techniques for performing both carrier recovery and timing recovery in the digital domain are less than optimum.

[0014] We submit that what is needed is an improved method and apparatus for use in the receiver of a UWB communication system to perform both carrier recovery and timing recovery in the digital domain. In particular, we submit that such a method and apparatus should provide performance generally comparable to the best prior art techniques but more efficiently than known implementations of such prior art techniques.

BRIEF SUMMARY OF THE INVENTION

[0015] In accordance with a preferred embodiment of our invention, we provide a method for use in an ultra-wideband (UWB) communication system in which a modulated carrier signal is transmitted via a transmission channel having an impulse response. In one embodiment, in a carrier acquisition mode of operation, the method performs both carrier and timing recovery. In one other embodiment, in a data recovery mode of operation, the method performs both carrier and timing recovery. In yet another embodiment, the method performs both carrier and timing recovery in both a carrier acquisition mode of operation and a data recovery mode of operation. In accordance with our invention, in all modes of operation, a plurality of complex estimates of the impulse response are sequentially developed. Of course, in alternative embodiments, the complex estimates may be developed in parallel, or in some other convenient sequence. [0016] In general, in the carrier acquisition mode of operation, carrier recovery is performed by: developing a first accumulated estimate of the impulse response as a function of selected first and second ones of the plurality of complex estimates; and then recursively developing a complex product vector as a function of a selected third one of the complex estimates, developing a carrier error angle as a function of the complex product vector, and accumulating the third complex estimate with the first accumulated estimate. In the carrier acquisition mode of operation, timing recovery is performed by: developing a second accumulated estimate of the impulse response as a function of a second set of the complex estimates; correlating with the second accumulated estimate a third set of the complex estimates; developing an estimated peak of the correlation, that peak corresponding to a selected on-time estimate in the third set of complex estimates; and developing a timing phase error as a function of the on-time estimate, a selected early estimate in the third set of complex estimates preceding the on-time estimate, and a selected late estimate in the third set of complex estimates following the on-time estimate.

[0017] In general, in the data acquisition mode of operation, carrier recovery is performed by: filtering the carrier signal as a function of a second accumulated estimate (developed, e.g., as described above) to develop a filtered carrier signal; and then recursively despreading the filtered carrier signal to develop a carrier error angle, and rotating the filtered carrier signal as a function of the carrier error angle. In the data acquisition mode of operation, timing recovery is performed by: developing a third accumulated estimate of the impulse response as a function of a selected fourth set of the complex estimates; filtering the carrier signal as a function of the third accumulated estimate to develop a filtered carrier signal; despreading the filtered carrier signal to develop a set of timing error metrics comprising an early metric, an on-time metric and a late metric; and developing the timing phase error as a function of at least a selected one of these metrics.

[0018] The methods of our invention may be embodied in computer readable code on a suitable computer readable medium such that when a processor executes the computer readable code, the processor executes the respective method.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0019] Our invention may be more fully understood by a description of certain preferred embodiments in conjunction with the attached drawings in which:

[0020] Fig. 1 illustrates, in block diagram form, a prior art receiver adapted for use in a UWB communication system;

[0021] Fig. 2 illustrates, in block diagram form, one embodiment of the receiver shown in Fig. 1, but constructed in accordance with our invention; [0022] Fig. 3 illustrates, in block diagram form, the portion of the receiver shown in Fig. 2 that performs carrier and timing recovery when the receiver is operating in a carrier acquisition mode;

[0023] Fig. 4 illustrates, in block diagram form, the portion of the receiver shown in Fig. 2 that performs carrier and timing recovery when the receiver is operating in a data recovery mode;

[0024] Fig. 5 illustrates, in block diagram form, the error angle calculation block shown, e.g., in Fig. 3;

[0025] Fig. 6 illustrates, in relative isolation, those components of the receiver shown in Fig. 3 adapted to perform carrier recovery;

[0026] Fig. 7 illustrates, in block diagram form, a programmable scaler adapted for use with our carrier loop filter shown in Fig. 6;

[0027] Fig. 8 illustrates, in signal wave form, our approach to scale the filtered phase error estimate and apply it to the accumulator more often than once per symbol in the case of 850kb/s;

[0028] Fig. 9 illustrates, in signal wave form, our approach to scale the filtered phase error estimate and apply it to the accumulator more often than once per symbol in the case of 6.8Mb/s;

[0029] Fig. 10 illustrates, in signal wave form, our approach to scale the filtered phase error estimate and apply it to the accumulator more often than once per symbol in the case of 1 lOkb/s;

[0030] Fig. 11 illustrates, in block diagram form, a rotator adapted for use with our carrier loop filter shown in Fig. 6;

[0031] Fig. 12 illustrates, in relative isolation, those components of the receiver shown in Fig. 4 adapted to perform timing recovery;

[0032] Fig. 13 illustrates, in block diagram form, a resampler adapted for use with our timing recovery loop shown in Fig. 12; and

[0033] Fig. 14 illustrates, in flow diagram form, a process for seeding the timing loop filter shown in Fig. 12.

[0034] In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers, and is not intended to imply or suggest that our invention requires identity in either function or structure in the several embodiments.

DETAILED DESCRIPTION OF THE INVENTION

[0035] Shown in Fig. 2 is a UWB receiver 10' constructed in accordance with our invention. As in the prior art system shown in Fig. 1, the signal received by antenna 12 is continuously conditioned by filter 14. The conditioned signal is then periodically sampled by an analog-to-digital converter ("ADC") 20 and provided as a continuous series of digital samples. In accordance with a preferred embodiment of our invention, ADC 20 is specially adapted to provide each digital sample in ternary form, i.e., [-1, 0, +1]. In view of the difficulty of currently available standard digital circuit technology efficiently to represent a 3- value variable in the form of a single ternary trit, we anticipate, at least in the near term, such variables will require representation using 2 conventional, binary bits, wherein a first one of the bits represents the numeric component of the variable, i.e., [0, 1], and the second bit represents the sign of the variable, i.e., [+, -]. In this regard, it could be argued that circuit technology has not progressed all that much since Soviet researchers built the first (perhaps only?) documented ternary-based computer systems. See, "A Visit to Computation Centers in the Soviet Union," Comm. of the ACM, 1959, pp. 8-20; and "Soviet Computer Technology— 1959", Comm. of the ACM, 1960, pp. 131-166; copies of which are submitted herewith and which are expressly incorporated herein in their entirety by reference.

[0036] In the context of our invention, our trit can be distinguished from a conventional sign+magnitude implementation such as that described in Amoroso83, cited above. Consider the strategy for AID conversion shown in Fig. 5 of Amoroso83; and, note, especially, that there are three separate and distinct switching thresholds: (i) a sign threshold [To]; (ii) a positive magnitude threshold [To + Δ]; and (iii) a negative magnitude threshold [T ₀ - Δ]. (See, also, Amoroso83, p. 1119, lines 21-24.) We have discovered that adapting the ADC to use ONLY a positive magnitude threshold [T ₀ + Δ] and a negative magnitude threshold [T ₀ - Δ] results in only a very small loss in resolution, while improving the performance of an impulse radio UWB receiver. Accordingly, in our preferred embodiment, ADC 20 implements only positive/negative magnitude thresholds [T ₀ + Δ], thereby simplifying the circuit while simultaneously improving both the conversion time of the ADC 20 and, in general, the performance of the receiver. Such an implementation lends itself naturally to our trit-based scheme, wherein the three defined states indicate, for example, that:

[-1] => the input is below the negative magnitude threshold [T ₀ - Δ];

[0] => the input is between the negative magnitude threshold [T ₀ - Δ] and the positive magnitude threshold [T ₀ + Δ]; and

[+1] => the input is above the positive magnitude threshold [T ₀ + Δ].

In contrast to a conventional sign+magnitude implementation, our trit-based ADC 20 can be readily adapted to operate either at a higher sample rate (improved performance but with more power) or at an equivalent sample rate (substantially equivalent performance but with less complexity, thereby reducing both circuit size and power consumption). [0037] Additional details relating to the construction and operation of our UWB receiver 10' can be found in the Related References. As explained in the Related References, receiver 10' initially operates in an acquisition mode, during which the components are configured to detect an incoming UWB signal transmitted by a remote UWB transmitter (not shown), and to achieve synchronism with that transmission, a process referred to as acquisition. Having achieved acquisition, receiver 10' transitions into a data mode, during which the components are configured to recover data contained within each transmitted packet, a process referred to as demodulation or data recovery.

[0038] Shown in Fig. 3 are the components of our receiver 10' that perform carrier and timing recovery when the receiver 10' is operating in the acquisition mode. As explained in our Related References, during operation, ADC 20 develops trit-valued samples of both the in-phase, Sr[5:0], and quadrature, Si[5:0], components of the received signals. In the acquisition mode, these samples are passed to the correlator 24, where they are correlated against the predefined preamble code. If a valid preamble is present, the output of the correlator 24 comprises a noisy estimate of the channel impulse response ("CIR"). This noisy CIR estimate is passed, without carrier and timing recovery, to accumulator 26. If a preamble is present, then, as accumulator 26 adds symbols together, the CIR estimate will grow faster than the noise floor. By comparing successive accumulated groups of CIR estimates, the acquisition control logic (described in our Related References) can determine if there is a valid preamble present.

[0039] Once a preamble has been identified, the carrier recovery logic is activated to correct carrier error in the received data. Logic 46 computes an instantaneous phase error estimate of the received UWB signal by performing an inverse tangent operation on the in-phase, i.e., real, and quadrature, i.e., imaginary, components of the signal phasor. A carrier loop filter 48 uses this estimate to compute a correction angle to be applied to the current input to the accumulator 26. This correction angle is developed as a carrier recovery phase signal (7-bits unsigned) wherein the output range is 0.0 to almost 2.0, and where the value 2.0 is equivalent to one revolution. A look-up-table ("LUT') 50 converts the correction angle to a corresponding pair of cosine (5-bits, including a sign bit) and sine (5-bits, including a sign bit) values. Using these sine and cosine values, a rotator 52 rotates the correlated samples by implementing a complex multiplication for each sample, followed by rounding to return the output real and imaginary samples to 7- bit signed values. The rotated correlated samples are then resampled by resample 54 for use by the accumulator 26.

[0040] There is a finite probability that a detected preamble is not valid. Accordingly, our accumulator 26 spends some time assessing the quality of the incoming signal. If the quality is found to be poor, the preamble is rejected and accumulator 26 resumes searching for a preamble. If the quality is found to be sufficiently high, the next task is to search for a start-of-frame-delimiter ("SFD") by comparing the incoming correlator samples against the accumulated CIR estimate. This is performed for each symbol, and the result quantised to a 2-bit signed value. This 2-bit signed value should be +1 throughout the preamble, but then, once the SFD pattern is received, it should follow the pattern of the SFD. For example, for a short SFD, this would be [0, +1, 0, -1, +1, 0, 0, -1]. A corresponding search pattern is used to find this sequence on the 2-bit quantised values. This allows the SFD pattern to be identified, and the time to transition to data mode determined.

[0041] Shown in Fig. 4 are the components of our receiver 10' that perform carrier and timing recovery when the receiver 10' is operating in the data mode. No later than the end of the acquisition mode, the CIR estimate developed by accumulator 26 is loaded into the channel-matched-filter ("CMF") 36. Once receiver 10' switches to data mode, the ADC 20 samples are passed to the CMF 36, which gathers the energy of the received UWB pulses together, thereby compensating for the smearing effect of the multi- path channel. The resulting output pulses are passed through the timing and carrier recovery loops to compensate for any offset, and then into despreader 40. Despreader 40 applies the same pseudo-random noise ("PN") spreading sequence used in the transmitter (not shown) to generate the burst, and integrates over the burst. As despreader 40 does not know if a logic_l or a logic_0 is being transmitted, it despreads at both possible locations to produce two estimates. These two estimates provide the soft input to the Viterbi decoder 42, which produces a maximum likelihood estimate of the bit sequence. The first section of the packet to be demodulated is the PHY header ("PHR"), which contains information about the data rate and the number of octets transmitted. As is known, this is protected by a single-error-correct-double-error detect ("SECDED") code. Once the PFTR is decoded, the relevant information is extracted to allow the demodulation, i.e., recovery, of the data payload. The remaining payload is then passed through the Viterbi decoder 42 to Reed-Solomon ("RS") decoder 44 to correct any errors or report errors that cannot be corrected.

[0042] As shown in Fig. 3, in the acquisition mode, the instantaneous phase error estimate is derived from the output of correlator 24 as follows:

1. The accumulated samples, Sr[14:0] and Sr[14:0], are quantized and the conjugate calculated in logic block 56;

2. The complex correlated samples from resampler 54 are multiplied by the conjugate by multiplier 58; and

3. The products are summed by summer 60 to produce the complex instantaneous phase error estimate phasor, comprising Sr[15:0] and Si[15:0].

[0043] As shown in Fig. 4, in the data mode, the complex instantaneous phase error estimate phasor simply comprises the outputs of despreader 40, comprising Sr[15:0] and Si[15:0]. [0044] The instantaneous phase error estimate phasor is then converted to a corresponding angle by logic block 62. As shown in Fig. 5, the complex error estimate phasor consists of two 17-bit signed numbers. The angle of the phasor is determined by dividing the imaginary component of the phasor, Si[15:0], by the real component, Sr[15:0]. Ideally the resulting quotient would then be passed to an inverse tangent function to compute the exact angle; however, for the purposes of our carrier recovery algorithm, we have determined that the quotient per se is a sufficient approximation to the angle. To simplify the division computation, we first identify the sign and quadrant of the phasor, and then compute the absolute value of the real and imaginary parts. These absolute values are then passed to the division computation, and the resulting angle is post-processed to map it into the appropriate quadrant/sign. The remapped estimate is then subjected to rounding and saturation to produce the signed 7-bit instantaneous phase error estimate, S[0:-5], in radians.

[0045] The structure of carrier loop filter 48 can be seen in greater detail in Fig. 6. As shown, the instantaneous phase error estimate is passed through a proportional gain arm 48a and an integral gain arm 48b. The gains, K _p and K _i5 are controlled by a gear-shifting algorithm to allow the loop to lock quickly, and then to rapidly tighten to a narrow bandwidth to minimise the impact of noise on the carrier recovery algorithm. The gear shifting is controlled by a counter (e.g., see, Fig. 7) that counts the number of phase error estimates supplied to the loop, and selects a respective scaling factor. (The default gear shifting table is described below.) The filtered phase error estimate is accumulated in a carrier phase accumulator 48c to track the over-all phase error, and to adjust the instantaneous phase error to track frequency errors of up to +/- 40ppm.

[0046] When receiver 10' transitions from acquisition to data mode, the rate of update of the carrier recovery loop 48 will change (from the preamble symbol interval to the data symbol interval); this requires that the integral term in the carrier for this change as follows:

992 1024 33/32

1016 10124 129/128

992 8192 8*(33/32)

1016 8192 8*(129/128)

Table 1 : Carrier Loop Filter Scaling Table

[0047] In data mode, we have determined that the application of the phase rotation in a single "lump" at the end of each symbol has a negative impact on the performance of the receiver. For the 6.8Mb/s case, the phase is applied at the end of a group of 8 symbols, so the symbols towards the end of this group suffer from increased phase error as compared to those at the start. Similarly for the 850kb/s case, the symbols representing a logic_l will have a higher phase error than those representing a logic_0. Worst of all is the 1 lOkb/s case, which will suffer from a phase error increase throughout a symbol and, depending on the hop position of the symbol, will have an effectively random phase en-or to start with if the carrier offset is high enough. To compensate for this, our preferred embodiment will smooth the phase rotation during the data demodulation phase.

[0048] As shown in Fig. 7, our approach is to scale the filtered phase error estimate and apply it to the accumulator more often than once per symbol. In the case of 850kb/s, the filtered phase error will be scaled down by a factor of 2 and accumulated twice (i. e., every 64 clock cycles) during the phase update interval. (See, e.g., Fig. 8.) This means that instead of the phase adjustment being applied in a single lump at the end of the interval, it will be distributed over the course of the symbol, thereby allowing the despread data towards the end of the interval to have a more accurate phase correction. In the case of 6.8Mb/s, the filtered phase error will be scaled down by a factor of 8 and accumulated 8 times (i.e., every 16 clock cycles) during the phase update interval. (See, e.g., Fig. 9.) In the case of the l lOkb/s, the filtered phase error estimate will be scaled down by a factor of 64 and accumulated 64 times (i.e. , every 16 clock cycles) during the phase update interval. (See, e.g., Fig. 10.) The despreader 40 will control when the phase rotation is applied, so that the phase rotation is updated just before it is needed for demodulation of a burst.

[0049] In our preferred embodiment, we implement a register-based field programmable gear shifting mechanism. Ten gears may be configured; one is reserved for demodulation mode, allowing nine acquisition gears. Each gear is assigned: a count at which it is activated; a K _p value; and a K _; value. Writing a value of logic_0 as the count for a gear other than the first gear terminates the gear shifting table; whilst still switching to the demodulation gear when the acquisition phase is over. Note that two sets of demodulation coefficients must be specified, one for the 110Kbps data rate case, and one for the 850K and 6.81Mbps cases. The default values for each of the available programmable registers are given in the following table:

CR5 64 0x4: 3*2 ^"10 0x5: 2 ^"5

CR6 128 0x3: 3*2 ^" " 0x4: 2 ^"6

CR7 192 0x2: 3*r ¹² 0x4: 2 ^"6

CR8 256 0x1 : 3*2 ^"13 0x3 : r ⁷

CR9 1023 0x0: 3*r ¹⁴ 0x3 : T ¹

Table 2: Carrier Recovery Loop Gear Shifting Table factors are coded as follows:

0x5 = r ⁵

0x6 = ΐ ⁴

0x7 = 2 ^"3

[0050] Under very noisy conditions, the carrier recovery loop may fail to lock correctly. This will result in a preamble rejection in the accumulator 26 (if this mode is enabled), effectively giving the carrier recovery loop another shot. The timing recovery loop can still fail to lock, however, and it does not get another chance since by the time this has an effect the preamble will likely be confirmed.

[0051] Preferably, LUT 50 updates the SIN (5-bits signed) and COS (5-bits signed) values under the control of accumulator 26 during acquisition mode and by despreader 40 during data mode. This is in order to prevent phase changes being applied at times when the data is important to the algorithm in question, so it must be applied outside of the impulse response during acquisition, and outside of a burst position during demodulation.

[0052] Rotator 52 takes the SIN and COS values from LUT 50 and applies them to the incoming data vectors. This rotation is applied to the correlator 24 outputs during acquisition, and to the CMF 36 outputs during data demodulation. As shown in Fig. 12, the first stage, TO, selects between the registered outputs of correlator 24 and CMF 36 depending on the mode. The second stage, Tl, performs the 4 multiplications that are required for a full complex multiplication, these multiplication results are then registered. The third stage, T2, sums the real components and the imaginary components of the complex multiplication, applies rounding to return the rotated samples to a precision of 7-bits (signed) and registers them for the output. Therefore the total latency of the rotator 52 is four clock cycles, C0-C3.

[0053] Our timing estimation is based on an early-late gating algorithm. As illustrated in Fig. 3 and Fig. 4, the source of data for this algorithm is dependent upon the phase of reception: during acquisition mode, the necessary timing information is derived from the output of CMF 36; and, during data mode, the despreader 40 provides the necessary timing information. In both cases the information is used to generate an instantaneous timing estimate. This estimate is conditioned and passed into a timing loop filter 64 typical of a second order loop. The timing loop filter 64 output provides sample-level timing adjustment information to the resampler 54 during acquisition mode, and clock cycle level adjustments to the accumulator 26 and despreader 40 during data mode.

[0054] As shown in Fig. 12, during acquisition mode, the timing estimate is derived from early/on- time/late samples from the output of the CMF 36. Once the preamble has been detected, the accumulator 26 will start writing CIR coefficients to the CMF 36. As noted before, the output of the correlator 24 provides an instantaneous noisy estimate of the CIR. As the timing offset error accumulates in the accumulator 26, the position of this estimate within the symbol will slowly vary. Quantizing the correlator 24 output and feeding it into the CMF 36 result in a correlation peak at the output of the CMF 36 corresponding to the position of the noisy impulse response estimate in the correlator 24 output symbol. In our preferred embodiment, the functions of quantisation of the correlator 24 output and routing to CMF 36 are performed by resampler 54.

[0055] As the timing of the incoming signal changes, the position of this correlation peak in the output of the CMF 36 will move. In general, this movement will be gradual relative to one preamble symbol duration and therefore can be tracked. The accumulator 26 provides a timing flag to indicate when the correlation peak is expected at the output of the CMF 36. This flag is based on the latency of the accumulator 26 and CMF 36 relative to the estimated impulse response location. Initially, this will be very accurate as the timing phase error will be negligible, but, as the phase error accumulates, the peak will move, thus providing the desired timing information. The correlation peak is ideally the on-time sample, with the early and late samples being the one immediately preceding and following the on-time sample respectively. These three samples are passed to a phase detector 66 (see, Fig. 3) that computes an instantaneous timing phase error for the timing loop filter 64.

[0056] During demodulation, the despreader 40 provides dedicated early and late outputs in addition to the normal on-time output used as part of the demodulation process. These outputs are provided for both possible burst positions (depending on if the data is a logic_0 or a logic_l); thus, an early instantaneous decision is needed in order to identify which of the two sets of early/on-time/late samples to use in computing the instantaneous timing phase error estimate. Once this decision is made, the computation is performed and the error passed to the the timing loop filter 64.

[0057] The phase error estimation is based on the previously described early/on-time/late samples. A difference computation is perfonned by computational block 68. The difference between the early and late values is computed and checked against the on-time (on-time should be greater). If the on-time value is negative or zero (after conditioning), then the data is unreliable and the phase estimate zeroed. The difference is divided by twice the peak and the result checked to be less than 0.75 (otherwise it is considered unreliable) and passed out as the instantaneous timing error estimate in the format S[-l:-4]. This instantaneous timing error estimate is then passed on to the timing loop filter 64.

[0058] As shown in Fig. 12, timing loop filter 64 comprises a proportional gain arm 64a and an integral gain arm 64b. The gains, Kp and Ki are controlled by a gear-shifting algorithm to allow the loop to lock quickly and then rapidly to tighten to a narrow bandwidth to minimise the impact of noise on the timing recovery algorithm. The gear shifting is controlled by a counter (e.g., see, Fig. 7) that counts the number of timing error estimates supplied to the loop and operates, in one example, as follows:

0-5 0 0

5-28 31/(2 ^"7 ) 0

28-80 31/(r ⁷ ) 20/(2 ^" ")

80-120 15/(2 ^'7 ) 5/(2 ^"n )

120 onwards l l/(2 ^"7 ) l/(2 ^"n )

Table 3: Timing Estimation Loop Gear Shifting Table

[0059] Timing loop filter accumulator 64c accumulates the lower noise estimate of the timing phase error to track the timing phase error and adjust the sampling phase error between 0 and +15.875 samples. Timing loop filter 64 also develops phase_increment ("Inc") and phase_decrement ("Dec") signals that are used to adjust the timing in units of 16 samples because they either drop or add a clock cycle delay in the accumulator 26 (during acquisition) or despreader 40 (during demodulation). Therefore, if an adjustment of -2.5 samples is required, then phase_inc is used to introduce an offset of -16 samples, while the phase error driving resampler 40 will apply a correction of +13.5 samples, giving the overall required phase adjustment of -2.5 samples. Similarly, for example, an adjustment of +19.125 samples may be achieved by applying a +16 sample adjustment with the phase dec signal, followed by an additional +3.125 sample correction in the resampler 54. By way of illustration, a suitable embodiment of resample 54 is illustrated in Fig. 13.

[0060] The carrier recovery loop needs to lock quickly in order to successfully receive the signal, whereas the timing recovery loop can take longer. As a result, if the carrier recovery loop fails to lock soon after the preamble is found, then the preamble will be rejected, allowing the carrier recovery loop another chance to lock. The timing recovery loop, however, does not get a second chance, so, to improve the chances of lock, the timing recovery loop can be seeded with an estimate based on the carrier loop integrator. Preferably, seeding is enabled via the use of a control signal: if the state of this signal is, e.g., logic_0, then timing seeding does not take place and the gearing table (see, below) must be set up to allow for this (initially wide bandwidth to allow acquisition, then narrowing as the lock improves); but, if the state of this signal is, e.g., logic_l, then timing seeding is enabled and the loop is assumed close to lock from the outset, and a more aggressive gearing table can be used. In our preferred embodiment, seeding is enabled by default.

[0061] We have determined that the value of the loop integrator in the carrier recovery loop can be used to seed the loop integrator in the timing recovery loop, thereby giving the timing recovery loop a jump start and enhancing the chances of it locking. The formula we prefer to use to compute the seed value is: I« _m Scale%I _ca where:

lam = timing loop integrator;

I car = carrier loop integrator;

F _s = sampling rate; and

F _c = carrier frequency.

Since F _s and F _c are related this is simpler in practice:

As shown in Fig. 14, we prefer to allow the carrier recovery loop to settle on a good quality estimate before seeding the timing recovery loop; we define the delay in terms of the carrier recovery loop gearing counter and prefer to make this threshold value programmable. Once this gearing counter threshold value is reached, the value held in the carrier recover loop integrator is scaled according to the table above (depending on the channel setting) to produce a timing seed value with the precision S[-l :-15]. Rounding does not need to be applied to this computation, just truncation, because the computation is a one-time event in the receiver 10' and does not take part in a recursive loop— therefore the bias introduced by not rounding will not accumulate to cause significant inaccuracy.

[0062] In our preferred embodiment, we implement a register-based field programmable gear shifting mechanism. Ten gears may be configured; one is reserved for demodulation mode, allowing nine acquisition gears. Each gear is assigned: a count at which it is activated; a K _p value; and a K _; value. Writing a value of logic_0 as the count for a gear other than the first gear terminates the gear shifting table; whilst still switching to the demodulation gear when the acquisition phase is over. Note that two sets of demodulation coefficients must be specified, one for the 110Kbps data rate case, and one for the 850K and 6.81Mbps cases. The default values for each of the available programmable registers are given in the following table: Register Value Default

fount |' ⁾ :0| ; | 14: 10| K _p | 19: 15|

TRO 0XF80OO 0 0 31

TR1 0x8141E 30 5 16

TR2 0X58428 40 1 11

TR3 0X00000 0 0 0

TR3 0X00000 0 0 0

TR5 0X00000 0 0 0

TR6 0X00000 0 0 0

TR7 0X00000 0 0 0

TR8 0X00000 0 0 0

TR9 0X5A161 N/A 1 /8(1 10Kbps) 11

Table 4: Timing Estimator Default Programmable Gear Shifting Register Values where:

Value comprises a 20-bit variable expressed in hexadecimal format;

Count comprises bits [9:0] of the Value;

Ki comprises bits [14: 10] of the Value; and

Kp comprises bits [19: 15] of the Value.

The K factors are coded as follows:

Table 5: Gear Shifting Register Value Decode

[0063] Although we have described our invention in the context of particular embodiments, one of ordinary skill in this art will readily realize that many modifications may be made in such embodiments to adapt either to specific implementations. By way of example, it will take but little effort to adapt our invention for use with a different ADC scheme when it can be anticipated that the target application will not be subject to significant levels of in-channel CW interference. Further, the several elements described above may be implemented using any of the various known semiconductor manufacturing methodologies, and, in general, be adapted so as to be operable under either hardware or software control or some combination thereof, as is known in this art. Alternatively, the several methods of our invention as disclosed herein in the context of special purpose receiver apparatus may be embodied in computer readable code on a suitable computer readable medium such that when a general or special purpose computer processor executes the computer readable code, the processor executes the respective method.

[0064] Thus it is apparent that we have provided an improved method and apparatus for use in the receiver of a UWB communication system to perform both carrier recovery and timing recovery in the digital domain. In particular, we submit that such a method and apparatus should provide performance generally comparable to the best prior art techniques but more efficiently than known implementations of such prior art techniques.