Title:
RECEIVING FRAME PROCESSING APPARATUS
Document Type and Number:
WIPO Patent Application WO/2005/109214
Kind Code:
A1
Abstract:
For a frame of a different allowable delay time, the delay time is assured and the number of interruptions is reduced. Therefore, a receiving frame processing apparatus is provided with a receiving frame allowable delay time judging part, a waiting time measuring part and an interrupt generating part. The receiving frame allowable delay time judging part judges an allowable delay time of the frame by header information or payload information of the receiving frame, and when a waiting time reaches the allowable delay time, interruption is generated. Thus, when the allowable delay time of the receiving frame differ by frame, since an interrupt waiting time is measured for each allowable delay time of the frame, and an interrupt output is to be waited until the allowable delay time of the frame, interrupt frequency is reduced.
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Inventors:
MATSUURA TAKAO
SUZUKI HIROKI
INOSHITA AKESHI
SUZUKI HIROKI
INOSHITA AKESHI
Application Number:
PCT/JP2005/008281
Publication Date:
November 17, 2005
Filing Date:
May 02, 2005
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
MATSUURA TAKAO
SUZUKI HIROKI
INOSHITA AKESHI
MATSUURA TAKAO
SUZUKI HIROKI
INOSHITA AKESHI
International Classes:
G06F13/00; G06F13/24; G06F13/38; (IPC1-7): G06F13/00
Foreign References:
| JPH06236334A | 1994-08-23 | |||
| JP2003524312A | 2003-08-12 | |||
| JPH10207822A | 1998-08-07 | |||
| JPH09223091A | 1997-08-26 | |||
| JP2001014243A | 2001-01-19 | |||
| JPH10105487A | 1998-04-24 |
Attorney, Agent or Firm:
Zogo, Masahiro (7 Kojimachi 5-chome, Chiyoda-k, Tokyo 83, JP)
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