Title:
RECEIVING UNIT
Document Type and Number:
WIPO Patent Application WO/2015/166753
Kind Code:
A1
Abstract:
A high-frequency processing unit converts, to a demodulated baseband signal, a signal that includes a plurality of frames comprising a preamble field including a frame synchronization flag and a data field following the preamble field. The demodulated signal is inputted to a plurality of AD converters. Each of a plurality of clock generation circuits applies a sampling clock to the corresponding one of the plurality of AD converters. An oscillation unit applies, to the plurality of clock generation circuits, a high-frequency signal that is the basis of a fundamental frequency needed for generating the sampling clock. A demodulation unit performs a demodulation on the basis of a digital signal outputted from each of the plurality of AD converters, and outputs the demodulation result. Even when there is a discrepancy in clock frequency between the transmission and receiving sides, it is possible to suppress a rise in the sampling rate and an increase in the memory amount, and to perform stable reception.
Inventors:
TANAKA NOBUNARI (JP)
Application Number:
PCT/JP2015/059908
Publication Date:
November 05, 2015
Filing Date:
March 30, 2015
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H04L7/10; H04L7/04
Foreign References:
| JP2001177587A | 2001-06-29 | |||
| JPH07221810A | 1995-08-18 |
Attorney, Agent or Firm:
KITAYAMA, Mikio et al. (JP)
Mikio Kiyama (JP)
Mikio Kiyama (JP)
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