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Title:
RECEPTION CIRCUIT HAVING CLOCK SIGNAL RECONSTRUCTOR FOR MULTI-LAYER SIGNAL
Document Type and Number:
WIPO Patent Application WO/2018/034495
Kind Code:
A1
Abstract:
The present invention relates to a technology for enabling a stable operation of a reception circuit having a clock signal reconstructor which can be used in a C-PHY specification of a mobile industry process interface (MIPI), and freeing the reception circuit from requiring a separate control of a bias level. The present invention is characterized in that a plurality of received data skews prevent occurrence of a malfunction of a clock signal reconstructor when a clock signal for sampling of reception data is reconstructed through a clock reconstructor. Further, the present invention comprises a bias voltage generator (130) for generating a first bias voltage and a second bias voltage on the basis of a clock signal and providing the generated first bias voltage and second bias voltage to a first data receiver to a third data receiver (110A-110C), wherein levels of the first bias voltage and the second bias voltage are controlled to enable the first to third data receivers (110A-110C) to output multiple pieces of data having a duty cycle ratio of 50%.

Inventors:
JANG, Young Chan (110-1403 Hyunjinevervill Empire A.P.T, 69, Okgyebuk-ro,Gumi-si, Gyeongsangbuk-do, 37183, KR)
HAN, Jin Wook (Na-203 Jeonghan A.P.T, 38, Doryeongbuk-gil,Jeju-si, Jeju-do, 63126, KR)
Application Number:
KR2017/008918
Publication Date:
February 22, 2018
Filing Date:
August 17, 2017
Export Citation:
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Assignee:
KUMOH NATIONAL INSTITUTE OF TECHNOLOGY INDUSTRY-ACADEMIC COOPERATION FOUNDATION (61 Daehak-ro, Gumi-si, Gyeongsangbuk-do, 39177, KR)
International Classes:
H04L7/00
Domestic Patent References:
2015-11-26
Foreign References:
KR100218737B11999-10-01
KR20100135180A2010-12-24
US20040198297A12004-10-07
Other References:
JANG, YOUNG-CHAN ET AL.: "A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II : EXPRESS BRIEFS, vol. 53, no. 10, October 2006 (2006-10-01), pages 1063 - 1067, XP011142492
HAN, JIN-UK ET AL.: "Receiving Circuit for 3Gbps/lane 3-level Clock-embedded differential signal", 2016 SOC CONFERENCE, 27 May 2016 (2016-05-27), pages 1 - 3
Attorney, Agent or Firm:
LEE, Cheol Hee (8 Samsung-ro 100gil, Gangnam-gu, Seoul, 06167, KR)
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