Title:
RECONFIGURABLE CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/281652
Kind Code:
A1
Abstract:
A reconfigurable circuit device (10) is provided with a first circuit (20) and a second circuit (30) that allow for partial reconfiguration of an arithmetic circuit. The first circuit (20) comprises: a plurality of first partial circuits (21) arrayed spaced apart along the Y-direction; and first wiring (22) for connecting the plurality of first partial circuits (21) so that adjacent first partial circuits (21) are mutually connected. The second circuit (30) comprises a plurality of second partial circuits (31) arrayed spaced apart along the Y-direction, and second wiring (32) for connecting the plurality of second partial circuits (31) so that adjacent second partial circuits (31) are mutually connected. The plurality of first partial circuits (21) and the plurality of second partial circuits (31) are arrayed alternately along the Y-direction. The first wiring (22) directly connects adjacent first partial circuits (21) together. The second wiring (32) directly connects adjacent second partial circuits (31) together. Due to this configuration, it is possible to load bitstreams of the same format with less processing load.
Inventors:
TAKEYA TSUTOMU (JP)
SAKAMOTO TAKESHI (JP)
ARIKAWA YUKI (JP)
ITO TSUYOSHI (JP)
TANAKA KENJI (JP)
SAKAMOTO TAKESHI (JP)
ARIKAWA YUKI (JP)
ITO TSUYOSHI (JP)
TANAKA KENJI (JP)
Application Number:
PCT/JP2021/025598
Publication Date:
January 12, 2023
Filing Date:
July 07, 2021
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H01L21/82
Domestic Patent References:
| WO2000051183A1 | 2000-08-31 |
Foreign References:
| JP2014143680A | 2014-08-07 | |||
| JPH11260928A | 1999-09-24 | |||
| JP2007527613A | 2007-09-27 | |||
| US6766505B1 | 2004-07-20 | |||
| JP2005500625A | 2005-01-06 |
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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