Title:
RECONFIGURABLE CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/095347
Kind Code:
A1
Abstract:
A semiconductor apparatus with a reconfigurable circuit is disclosed. The reconfigurable circuit comprises: a carry skip circuit; two or more logic elements, each of which includes: a first programmable circuit which can implement any 2-input logic function or a 3-input full-adder sum function; a second programmable circuit which can implement any 2-input logic function or a 3-input full-adder carry function; a third programmable circuit which can implement any 2-input logic function, wherein the carry skip circuit receives propagation control signals, each output from each of the logic elements, to select, as a carry out signal, either a carry in signal supplied to a first logic element, or a carry out signal output from last logic element, based on the propagation control signals.
Inventors:
BAI XU (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
NEBASHI RYUSUKE (JP)
TADA AYUKA (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
NEBASHI RYUSUKE (JP)
TADA AYUKA (JP)
Application Number:
PCT/JP2018/041043
Publication Date:
May 14, 2020
Filing Date:
November 05, 2018
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H03K19/177
Domestic Patent References:
| WO2011162116A1 | 2011-12-29 |
Foreign References:
| US7663400B1 | 2010-02-16 | |||
| JP2017538347A | 2017-12-21 |
Other References:
BAI, XU ET AL.: "Area-efficient nonvolatile carry chain based on pass-transistor/atom-switch hybrid logic", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 55, 1 March 2016 (2016-03-01), pages 1 - 5, XP055704822, ISSN: 0021-4922, DOI: 10.7567/JJAP.55.04EF01
Attorney, Agent or Firm:
KATO, Asamichi (JP)
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