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Title:
RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD
Document Type and Number:
WIPO Patent Application WO/2015/025682
Kind Code:
A1
Abstract:
A delay circuit (10) containing a first inverting circuit, which contains a pull-up circuit (2) and a pull-down circuit (3), and a second inverting circuit, which contains a pull-up circuit (4) and a pull-down circuit (5). The delay circuit also contains: a first pass transistor (6) connected in series to the pull-up circuit of the first inverting circuit between a power supply potential and an output node; a second pass transistor (7) connected in series to the pull-down circuit (2) of the first inverting circuit between a ground potential and the output node (Out); a third pass transistor (8) inserted in series between an input node (In) and the pull-up circuit of the second inverting circuit; and a fourth pass transistor (9) inserted in series between the input node and the pull-down circuit of the second inverting circuit. The delay characteristic of the delay circuit is changed by a combination of control signals (C1-C4) applied to the gates of the first - fourth pass transistors.

Inventors:
ONODERA, Hidetoshi (36-1 Yoshida-honmachi, Sakyo-ku, Kyoto-sh, Kyoto 01, 〒6068501, JP)
A.K.M MAHFUZUL, Islam (36-1 Yoshida-honmachi, Sakyo-ku, Kyoto-sh, Kyoto 01, 〒6068501, JP)
Application Number:
JP2014/069976
Publication Date:
February 26, 2015
Filing Date:
July 29, 2014
Export Citation:
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Assignee:
JAPAN SCIENCE AND TECHNOLOGY AGENCY (1-8 Honcho 4-chome, Kawaguchi-shi Saitama, 12, 〒3320012, JP)
International Classes:
H03K5/134; G01R31/28; H03K3/03; H03K5/04
Domestic Patent References:
WO1999012263A11999-03-11
Foreign References:
JPH09167927A1997-06-24
JPH0514149A1993-01-22
JP2006211064A2006-08-10
JP2010087968A2010-04-15
JP2001044369A2001-02-16
Other References:
See also references of EP 3038257A4
ISLAM A.K.M. MAHFUZUL; AKIRA TSUCHIYA; KAZUTOSHI KOBAYASHI; HIDETOSHI ONODERA: "Variation-sensitive Monitor Circuits for Estimation of Global Process Parameter Variation", IEEE TRANS. SEMICONDUCTOR MANUFACTURING, vol. 25, no. 4, December 2012 (2012-12-01), pages 571 - 580, XP011471174, DOI: doi:10.1109/TSM.2012.2198677
SHUICHI FUJIMOTO; TAKASHI MATSUMOTO; HIDETOSHI ONODERA: "Inhomogeneous Ring Oscillator for WID Variability and RTN Characterization", PROC. 25TH IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, March 2012 (2012-03-01), pages 25 - 30, XP032171655, DOI: doi:10.1109/ICMTS.2012.6190607
Attorney, Agent or Firm:
SAMEJIMA, Mutsumi et al. (AOYAMA & PARTNERS, Umeda Hankyu Bldg. Office Tower 8-1, Kakuda-cho, Kita-ku, Osaka-sh, Osaka 17, 〒5300017, JP)
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