Title:
RECONFIGURABLE LOGICAL DEVICE
Document Type and Number:
WIPO Patent Application WO/2015/037413
Kind Code:
A1
Abstract:
[Problem] To provide a small-area reconfigurable logical device.
[Solution] Provided is a logical device provided with a plurality of memory cell units each storing configuration information and configured as a logical element and/or a connection element, wherein each of the plurality of memory cell units comprises a pair of bit lines for logic disposed to correspond to columns of memory cells, word lines for logic, and an inverter unit connected to the pair of bit lines for logic, and the inverter unit comprises a first CMOS that receives an input signal from one of the pair of bit lines for logic and has a first MOS and a second MOS, and a second CMOS that receives an input signal from the other of the pair of bit lines for logic and has a third MOS and a fourth MOS, and outputs, as a data signal for logic, a first differential signal that is a set of output signals of the first MOS and the third MOS, and a second differential signal that is a set of output signals of the second MOS and the fourth MOS.
Inventors:
SATOU MASAYUKI (JP)
SHIMIZU ISAO (JP)
SHIMIZU ISAO (JP)
Application Number:
PCT/JP2014/071958
Publication Date:
March 19, 2015
Filing Date:
August 22, 2014
Export Citation:
Assignee:
TAIYO YUDEN KK (JP)
International Classes:
H03K19/177
Foreign References:
| US5761483A | 1998-06-02 | |||
| US20120187979A1 | 2012-07-26 | |||
| JP2008278216A | 2008-11-13 | |||
| JP2005109960A | 2005-04-21 |
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