FABRICATION

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, related to reduced area spin orbit torque (SOT) memory devices and their methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely on innovative devices such as spin orbit torque (SOT) memory devices including a spin orbit torque electrode coupled with an MTJ device and a switch to overcome the requirements imposed by scaling.

Non-volatile embedded memory with SOT memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a material layer stack to form functional SOT memory devices with scaling of transistors present formidable roadblocks to commercialization of this technology today. Specifically, minimizing the number of transistors to fabricate functional SOT memory devices is an important area of process development.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional view of a spin orbit torque (SOT) memory device coupled with a magnetic tunnel junction and a switch, in accordance with an embodiment of the present disclosure.

Figures IB illustrates a cross-sectional view of individual layers of a synthetic antiferromagnetic structure, in accordance with an embodiment of the present disclosure.

Figure 2 illustrates a plan view of a magnetic tunnel junction (MTJ) device and an insulator to metal transition selector disposed on a spin orbit torque electrode, in accordance with an embodiment of the present disclosure.

Figure 3 A illustrates an SOT memory device in a high resistance state.

Figure 3B illustrates an SOT memory device switched to a low resistance state after the application of a spin hall current and a spin torque transfer current.

Figure 3C illustrates an SOT memory device switched to a high resistance state after the application of a spin hall current and a spin torque transfer current.

Figure 3D illustrates a read operation performed on an SOT memory device.

Figures 4A- 4L illustrate cross-sectional views representing various operations in a method of fabricating an SOT memory device in accordance with embodiments of the present disclosure.

Figure 4A illustrates a cross-sectional view of the formation of a spin orbit torque layer on a conductive interconnect formed above a substrate, in accordance with embodiments of the present disclosure.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of a lithographically patterned resist layer to subsequently pattern the spin orbit torque layer.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following patterning of the spin orbit torque layer to form a spin orbit torque electrode.

Figure 4D illustrate cross-sectional and plan views of the structure in Figure 4C following the deposition of a dielectric layer on the spin orbit torque electrode and planarization of the dielectric layer and an uppermost portion of the spin orbit torque electrode.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following the formation of a free magnetic layer, tunnel barrier layer, a fixed magnetic layer, and a top electrode to form a material layer stack for magnetic tunnel junction memory device.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the process of etching the material layer stack to form a magnetic tunnel junction memory device and following the formation of a dielectric spacer adjacent to the magnetic tunnel junction memory device.

Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following the formation of a third dielectric layer and a planarization of the third dielectric layer and an uppermost portion of the MTJ memory device.

Figure 4H illustrates a cross-sectional view of the structure in Figure 4G following the formation of a SOT contact on the SOT electrode.

Figure 41 illustrates a cross-sectional view of the structure in Figure 4H following the formation of a first electrode layer, an insulator to metal transition (EVIT) oxide layer, and a second electrode layer on the EVIT oxide layer.

Figure 4J illustrates a cross-sectional view of the structure in Figure 41 following the process of etching the material layer stack to form an EVIT oxide selector device on the SOT contact.

Figure 4K illustrates a cross-sectional view of the structure in Figure 4J following the formation of a fourth dielectric layer on the FMT oxide selector device and on the MTJ memory device.

Figure 4L illustrates a cross-sectional view of the structure in Figure 4K following the formation of a selector contact on the JJVIT oxide selector device and an MTJ contact on the MTJ memory device.

Figure 5 illustrates a cross-sectional view of a SOT memory device coupled to a first transistor and a bit line.

Figure 6 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 7 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Reduced Area Spin orbit torque (SOT) memory devices and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

In an embodiment, an SOT memory device includes a magnetic tunnel junction (MTJ) memory device formed on a spin orbit torque electrode. The MTJ memory device functions as a memory device where the resistance of the MTJ memory device switches between a high resistance state and a low resistance state. The resistance state of a MTJ memory device is defined by the relative orientation of magnetization of two magnetic layers (fixed and free) that are separated by a tunnel barrier. When the magnetization of the two magnetic layers have orientations that are in the same direction the MTJ memory device is said to be in a low resistance state. Conversely, when the magnetization of the two magnetic layers have orientations that are in opposite directions the MTJ memory device is said to be in a high resistance state.

In an embodiment, in an absence of a spin orbit torque electrode, resistance switching in an MTJ memory device is brought about by passing a critical amount of spin polarized current through the MTJ memory device so as to influence the orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. The act of influencing the magnetization is brought about by a phenomenon known as spin torque transfer, where the torque from a spin polarized current is imparted to the magnetization of the free magnetic layer. By changing the direction of the spin polarized current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need a constant source of spin polarized current to maintain a magnetization direction, the resistance state of the MTJ memory device is retained even when there is no current flowing through the MTJ memory device. For this reason, the MTJ memory device belongs to a class of memory known as non-volatile memory.

As an MTJ memory device is scaled down in size, the amount of critical spin current density required to switch the device increases. It then becomes advantageous to have an additional source of switching torque to avoid simply increasing the spin current. By implementing an MTJ memory device on a spin orbit torque electrode, the magnetization in the free magnetic layer gets an additional switching torque from a second source. In an

embodiment, the additional torque comes from a spin diffusion current, induced by passing an electrical current in a transverse direction, through the spin orbit torque electrode.

In an embodiment, integrating a non-volatile memory device such as an SOT memory device onto access transistors enables the formation of a memory cell. In one embodiment, a large collection of memory cells enables the formation of embedded memory for system on chip (SOC) applications. However, approaches to integrate an SOT memory device onto access transistors presents challenges that have become far more formidable with scaling. In an embodiment, an SOT memory device requires a first access transistor to select a memory cell to be read, and a second access transistor to program (write/erase) the memory cell. In an embodiment, two transistors have to be accommodated into a given memory cell footprint, increasing the cell size to approximately twice that of a normal MTJ memory cell that requires a single transistor.

In an embodiment, by forming a two terminal selector element on the spin orbit torque electrode of the SOT memory device, the programing transistor can be replaced. In an embodiment, the two terminal selector element is laterally separated from the MTJ memory device. In an embodiment, a conductive electrode electrically couples a second terminal of the selector element (a terminal away from the spin orbit torque electrode) with a second terminal (a terminal away from the spin orbit torque electrode) of the MTJ memory device. In an

embodiment, by applying a voltage above a threshold, VT , on a single conductive electrode the state of the selector can be changed from a non-conductive (insulating) state to a conductive state. In one embodiment, by increasing the voltage above VT , the resistance state of MTJ memory device can be switched and the SOT memory device can be programmed without the need for a second transistor. In an embodiment, by removing the second transistor, the cell size can be shrunk providing more valuable real estate for other components such as a periphery sensing circuitry for SOC applications.

In accordance with embodiments of the present disclosure, a spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque (SOT) memory device further includes a selector element such as an insulator-metal transition (FMT) oxide selector coupled to the spin orbit torque electrode and laterally spaced apart from the MTJ memory device. For SOT

functionality, the spin orbit torque electrode has a width that is similar or approximately similar to a width of an MTJ memory device. In an embodiment, the MTJ memory device includes a free magnetic layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO or AI2O3 disposed on the free magnetic layer and a fixed magnetic layer disposed on the tunnel barrier. The SOT memory device further includes a conductive interconnect structure disposed above and coupled with the FMT oxide selector and the MTJ memory device. In an embodiment, the conductive interconnect structure coupling the EVIT oxide selector and the MTJ memory device enables the FMT oxide selector and the MTJ memory device to be voltage biased by a single electrode. In an embodiment, a conductive interconnect is disposed below and coupled to the spin orbit torque electrode and provides a pathway for connection to a transistor drain terminal. In an embodiment, the conductive interconnect is distant from the FMT oxide selector and the MTJ memory device. In an embodiment, the MTJ memory device is disposed laterally between the FMT oxide selector and the conductive interconnect to benefit from a torque provided by a spin diffusion current induced in the spin orbit torque electrode. In an

embodiment, the FMT oxide selector is disposed at a level above the MTJ memory device. In another embodiment, the FMT oxide selector can also be disposed directly on the spin orbit torque electrode. In an embodiment, an SOT memory device includes an in-plane MTJ (iMTJ) memory device. In an embodiment, an SOT memory device that includes an iMTJ device is, herein, referred to as an in-plane SOT memory device or a iSOT memory device. In an embodiment, an SOT memory device includes a perpendicular MTJ (pMTJ) memory device. In an embodiment, an SOT memory device that includes a pMTJ device is, herein, referred to as a perpendicular SOT memory device or a pSOT memory device.

Figure 1A is an illustration of a cross-sectional view of a SOT memory device 100 in accordance with an embodiment of the present disclosure. The SOT memory device 100 includes a spin orbit torque electrode 101 disposed in a dielectric layer 102, a magnetic tunnel junction (MTJ) memory device 104, disposed on the spin orbit torque electrode 101 and an insulator-metal transition (FMT) oxide selector 106 coupled to the spin orbit torque electrode 101 and laterally spaced apart from the MTJ memory device 104. The SOT memory device 100 further includes a conductive interconnect structure 108 disposed above and coupled with the FMT oxide selector 106 and the MTJ memory device 104, and a conductive interconnect 110 disposed below and coupled to the spin orbit torque electrode 101. In an embodiment, the conductive interconnect 110 is distant from the FMT oxide selector 106. In an embodiment, the MTJ memory device 104 is disposed laterally between the FMT oxide selector 106 and the conductive interconnect 110. In an embodiment, the FMT oxide selector 106 is disposed at a level above the MTJ memory device 104 as illustrated in Figure 1 A. In an embodiment, an SOT memory device 100 includes a pMTJ device. In an embodiment, an SOT memory device 100 that includes a pMTJ device is, herein, referred to as a perpendicular SOT memory device or a pSOT memory device.

The spin orbit torque electrode 101 includes a metal with high degree of spin orbit coupling. A metal with a high degree of spin-orbit coupling has an ability to inject a large spin polarized current in to the free magnet 112. A large spin polarized current can exert a large amount of torque and influence the magnetization of the free magnet 112 to switch faster. In an embodiment, the spin orbit torque electrode 101 includes a metal such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, the spin orbit torque electrode 101 includes a metal or metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, spin orbit torque electrode 101 includes a beta phase tantalum or beta phase tungsten. A spin orbit torque electrode 101 including a beta phase tantalum or beta phase tungsten has a high spin hall efficiency. A high spin hall efficiency denotes that the spin orbit torque electrode 101 can generate a large spin hall current for a given charge current that is passed through the spin orbit torque electrode 101. In an embodiment, the spin orbit torque electrode 101 includes a multilayer stack including one or more layers of metals such as but not limited to tantalum, tungsten, platinum or gadolinium. In an embodiment, when the spin orbit torque electrode 101 includes a multilayer stack, the layer with the highest degree of spin-orbit coupling is disposed directly adjacent to the MTJ device. In an embodiment, the spin orbit torque electrode 101 has thickness of between 2nm-10nm.

Referring again to Figure 1 A, the MTJ memory device 104 includes a free magnet 112, a tunnel barrier 114 such as an MgO or AI2O3, disposed on the free magnet 112, a fixed magnet 116 disposed on the tunnel barrier 114 and a top electrode 120 disposed on the fixed magnet 116. In an embodiment, a dielectric spacer 132 is disposed on a portion of the spin orbit torque electrode 101 and laterally surrounds the MTJ memory device 104.

In an embodiment, the free magnet 112 includes a magnetic material such as Co, Ni, Fe or alloys of these materials. In an embodiment, the free magnet 112 includes a magnetic material such as FeB, CoFe and CoFeB. In an embodiment, the free magnet 112 includes a Coioo-x- _y Fe _x By, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnet 112 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy.

Referring again to Figure 1 A, in an embodiment, the tunnel barrier 114 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 114, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 114. Thus, the tunnel barrier 114 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 114 includes a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In an embodiment, the tunnel barrier 114 including MgO has a crystal orientation that is (001) and is lattice matched to the free magnet 112 as well as to the fixed magnet 116. In one embodiment, the tunnel barrier 114 is MgO and has a thickness of approximately lnm to 2 nm.

Referring again to Figure 1 A, in an embodiment, the fixed magnet 116 includes a material and has a thickness sufficient for maintaining a fixed magnetization. In an embodiment, the fixed magnet 116 of the MTJ memory device 104 includes an alloy such as CoFe and CoFeB. In an embodiment, the fixed magnet 116 comprises a Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 116 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy.

In an embodiment the fixed magnet 116 has a thickness that is between lnm- 2.5 nm. In an embodiment, the fixed magnet 116 has a thin uppermost portion that is insufficient to maintain magnetization and is said to be magnetically dead. In an embodiment, the magnetically dead uppermost portion of the fixed magnet 116 has a thickness between 0.2nm-0.5nm. In one such embodiment, in spite of having a magnetically dead uppermost portion, the fixed magnet 116 has a remaining magnetic portion having a thickness that is sufficient for maintaining a fixed magnetization.

Referring again to Figure 1 A, the MTJ memory device 104 further includes a top electrode 120 disposed on the fixed magnet 116. In an embodiment, the top electrode 120 includes a material such as W, Ta, TaN or TiN. In an embodiment, the top electrode 120 has a thickness between 20nm-70nm.

In an embodiment, a synthetic antiferromagnetic (SAF) structure such as a SAF structure 118 illustrated in Figure IB can be disposed between the top electrode 120 and the fixed magnet 116 in order to fix a magnetization of the fixed magnet 116. In an embodiment, the SAF structure 118 includes a non-magnetic layer 118B disposed between a first pinning layer 118A and a second pinning layer 118C as depicted in Figure ID. The first pinning layer 118A and the second pinning layer 118C are antiferromagnetically coupled to each other. In an embodiment, the first pinning layer 118A includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe. In an embodiment, the first pinning layer 118A includes one or more bilayers of a magnetic/non-magnetic metal such as but not limited to Co/Pd or a Co/Pt. In an embodiment, total number of bilayers can range from 2- 20. In an embodiment, the non-magnetic layer 118B includes a ruthenium or an iridium layer. In an embodiment, the second pinning layer 118C includes a layer of a magnetic metal such as Co, Ni, Fe, alloys such as CoFe, CoFeB, or alloys of magnetic metals such as Co, Ni, Fe. In an embodiment, the second pinning layer 118C includes one or more bilayers of a magnetic/non- magnetic metal such as but not limited to Co/Pd or a Co/Pt. In an embodiment, total number of bilayers can range from 2-20. In an embodiment, a ruthenium based non-magnetic layer 118B has a thickness between 4-9 Angstroms to ensure that the coupling between the first pinning layer 118A and the second pinning layer 118C is antiferromagnetic in nature.

It is to be appreciated that an additional layer of non-magnetic spacer material may be disposed on the fixed magnet 116, below the SAF structure 118. A non-magnetic spacer layer enables coupling between the SAF structure 118 and the fixed magnet 116. In an embodiment, a non-magnetic spacer layer may include a metal such as Ta, Ru or Ir.

Referring again to Figure 1 A, the EVIT oxide selector 106 includes an insulator-metal transition (EVIT) oxide 124 disposed on a first selector electrode 122, and a second selector electrode 126 disposed on the EVIT oxide 124. In an embodiment, the EVIT oxide selector 106 is disposed on a spin orbit torque electrode contact 128 and on a portion of a second dielectric layer 130. In an embodiment, spin orbit torque electrode contact 128 is disposed in the second dielectric layer 130 and on a portion of the spin orbit torque electrode 101. In an embodiment, the EVIT oxide selector 106 is non-coplanar with the MTJ memory device 104. In one embodiment, the EVIT oxide selector 106 is on disposed the spin orbit torque electrode 101.

In an embodiment, the EVIT oxide 124 includes a material consisting of an oxide of an element selected from the group consisting of niobium, vanadium and tantalum, hi an embodiment, the EVIT oxide 124 includes an oxide such as vanadium (IV) oxide, V0 ₂ and vanadium (V) oxide, V2O5, niobium (V) oxide, Nb ₂ 05 and Ta (V) oxide, Ta ₂ 0 ₅ . Ei an embodiment, the EVIT oxide 124 includes complex oxides such as but not limited to LaSrCuO, AsTeGeSiN or Cu-HfO. In one embodiment, the EVIT oxide 124 includes a material that exhibits filamentary conduction. In an embodiment, the EVIT oxide 124 is amorphous and has a columnar grain boundary. In another embodiment, the EVIT oxide 124 is crystalline. In an embodiment, the EVIT oxide 124 is crystalline after an electroforming process. In an

embodiment, the EVIT oxide 124 includes a material such as Hf0 ₂ , Zr0 ₂ , S13N4 or S1O2. In an embodiment, the EVIT oxide 124 which includes a material such as Hf0 ₂ , Zr0 ₂ , S13N4 or S1O2 further includes a dopant selected from the group consisting of silver, copper and gold. In an embodiment, the dopant concentration is between 0.1%-10% of the total composition of the EVIT oxide 124. hi an embodiment, a dopant concentration between 0.1-10% facilitates filament conduction. In an embodiment, the EVIT oxide 124 has a thickness between lOnm and 50nm for a stable memory device operation at or above 1.5 V. hi an embodiment, reducing the thickness of the EVIT oxide 124 decreases the amount of applied voltage needed for conduction.

In an embodiment, the first selector electrode 122 includes a material such as but not limited to W, TiN, Ta, Cu, Ag and Pt. hi an embodiment, the first selector electrode 122 has a thickness between 5nm-10nm. In an embodiment, the second selector electrode 126 includes a material such a but not limited to W, TiN, Ta, Cu, Ag and Pt. In an embodiment, the second selector electrode 126 has a thickness between 5nm-10nm. Ei an embodiment, the first selector electrode 122, and a second selector electrode 126 includes a same material such as TiN.

In an embodiment, the conductive interconnect structure 108 includes a first conductive via 108 A disposed on the EVIT oxide selector 106 and a second conductive via 108B disposed on the MTJ memory device 104. Ei an embodiment, the conductive interconnect structure 108 further includes a lateral interconnect 108C disposed above and connecting the first conductive via 108 A and the second conductive via 108B. In an embodiment, the conductive interconnect structure 108 is disposed in a third dielectric layer 134. In an embodiment, the conductive interconnect structure 108 includes a barrier layer, such as tantalum, tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the conductive interconnect 110 includes a barrier layer, such as tantalum, tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the spin orbit torque electrode contact 128 includes a barrier layer, such as tantalum, tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium.

In an embodiment, the second dielectric layer 130 is disposed on a portion of the spin orbit torque electrode 101, on the dielectric layer 102 and laterally surrounds a dielectric spacer 132 disposed on sidewalls of the MTJ memory device 104. In an embodiment, the third dielectric layer 134 is disposed on the FMT oxide selector 106, on the second dielectric layer 130, on the dielectric spacer 132 and on an uppermost surface of the MTJ memory device 104. In an embodiment, the dielectric layer 102, the second dielectric layer 130 and the third dielectric layer 134 each include a dielectric layer such as but not limited to silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or

polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant. In an embodiment, the dielectric layer 102, the second dielectric layer 130 and the third dielectric layer 134 are formed by CVD, PVD, PECVD or by other deposition methods.

In an embodiment, the SOT memory device 100 is disposed above a substrate 150. In an embodiment, substrate 150 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 150 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 150. Logic devices such as access transistors may be integrated with memory devices such as SOT memory device 100 to form embedded memory. Embedded memory including one or more SOT memory device 100 and logic MOSFET transistors can be combined to form functional integrated circuits such as a system on chip (SOC) or a microprocessor.

Figure 2 illustrates a plan view depicting relative spacing between the FMT oxide selector 106, the MTJ memory device 104, the conductive interconnect 110, in accordance with an embodiment of the present disclosure. In an embodiment, the spin orbit torque electrode 101 has a length, LSOT, between 100nm-500nm. In an embodiment, the spin orbit torque electrode 101 has a width, WSOT, between 10nm-50nm. In an embodiment, the MTJ memory device 104 has a broadest cross sectional width, WMTJ, that is the same or substantially the same as the width, WSOT. In an embodiment, the MTJ memory device 104 has a broadest cross sectional width, WMTJ, that is between 10nm-50nm.

In an embodiment, the relative spacing between the EVIT oxide selector 106 and the conductive interconnect 110 controls the magnitude of a spin diffusion current. In an embodiment, the spin diffusion current assists an MTJ memory device 104 in switching a magnetization of the free magnet 112. In an embodiment, the spin diffusion current has a flow direction and magnitude that is dependent on a polarity of a voltage bias applied between the EVIT oxide selector 106 and the conductive interconnect 110 (described in Figures 3B and 3C).

In an embodiment, a center of the conductive interconnect 110 is located at a point A, proximate to one edge of the spin orbit torque electrode 101 as illustrated in Figure IB. In an embodiment, a center of the EVIT oxide selector 106 is located a distance, L, away from the center of the conductive interconnect 110. In an embodiment, the MTJ memory device 104 is location at a point B, a distance Li away from the conductive interconnect 110 and a distance L ₂ away from the EVIT oxide selector 106. In an embodiment, the distance Li and L ₂ are

approximately equal. In another embodiment, Li and L ₂ are unequal. In an embodiment, when the spin orbit torque electrode 101 has a LSOT that is approximately lOOnm, Li i _S 10 nm and L ₂ is 70 nm. In another embodiment, when the spin orbit torque electrode 101 has a LSOT that is approximately lOOnm, Li is 0 nm and L ₂ is 80 nm. In one embodiment, Li is 20 nm and L ₂ is 60 nm. In an embodiment, Li < L ₂ . In an embodiment, L ₂ is > Li. In an embodiment, Li = 0. In an embodiment, when , Li = 0, the MTJ device 104 is above the conductive interconnect 110.

In an embodiment, the spin orbit torque electrode 101 has a rectangular plan view profile and the MTJ memory device 104 has a circular plan view profile as illustrated in Figure IB. In another embodiment, an MTJ memory device 104, such as an in-plane MTJ, has a plan view profile that is elliptical. In another embodiment, the MTJ memory device 104 has a plan view profile that is rectangular.

Figures 3A-3C illustrate a mechanism for switching a SOT memory device such as the

SOT memory device 100.

Figure 3 A illustrates an SOT memory device in a high resistance state.

In an embodiment, the free magnet 112 of the MTJ memory device 104 has a

magnetization 154 in the positive z-direction and the fixed magnet 116 of the MTJ memory device 104 has a magnetization 156 in the negative z-direction (anti-parallel to magnetization 154). In an embodiment, when the free magnet 112 of the MTJ memory device 104 has a magnetization 154 that is anti-parallel to a magnetization 156 in the fixed magnet 116, the MTJ memory device 104 is said to be in a high resistance state.

In an embodiment, the voltage bias between the conductive interconnect structure 135 (terminal A) and the conductive electrode 140 (terminal B) is 0 V. In one embodiment, the EVIT selector 170 is in a non-conductive state, when the voltage bias between the conductive interconnect structure 135 (terminal A) and the conductive electrode 140 (terminal B) is 0 V.

Figure 3B illustrates a spin orbit torque (SOT) memory device switched to a high resistance state after the application of a spin hall current and a spin torque transfer current. In an embodiment, a reversal in the magnetization 154 of the free magnet 112 in Figure 3B compared to the magnetization 154 of the free magnet 112 in Figure 3 A is brought about by (a) inducing a spin diffusion current 168 in the spin orbit torque electrode 101 in the y-direction, and (b) by applying an ISTTM current 170. In an embodiment, the spin diffusion current 168 flows through the spin orbit torque electrode 101 when there is current conduction through the FMT oxide selector 130. Spin diffusion current 168 herein, refers to a spin diffusion "electron" current.

In an embodiment, a positive voltage bias is applied to the conductive interconnect 190 and the conductive interconnect structure 135 is at ground potential. In an embodiment, when the applied bias voltage exceeds a threshold voltage, VT, the FMT oxide selector 130 turns on. Current 160 begins to flow through the FMT oxide selector 130. In response to the current 160, an electron current 162 flows in the positive y-direction. The electron current 162 includes electrons with two opposing spin orientations, a type I electron 166, having a spin oriented in the negative x-direction and a type II electron 164 having a spin oriented in the positive x-direction. In an embodiment, electrons constituting the electron current 162 experience a spin dependent scattering phenomenon in the spin orbit torque electrode 101. The spin dependent scattering phenomenon is brought about by a spin-orbit interaction between the nucleus of the atoms in the spin orbit torque electrode 101 and the electrons in the electron current 162. The spin dependent scattering phenomenon causes type I electrons 166, whose spins are oriented in the negative x- direction, to be deflected upwards towards an uppermost portion of the spin orbit torque electrode 101 and type II electrons 164 whose spins are oriented in the positive x-direction to be deflected downwards towards a lowermost portion of the spin orbit torque electrode 101. The separation between the type I electrons 166 and the type II electrons 164 induces a polarized spin diffusion current 168 in the spin orbit torque electrode 101. In an embodiment, the polarized spin diffusion current 168 is directed upwards toward the free magnet 112 of the MTJ memory device 104 as depicted in Figure 3B. The polarized spin diffusion current 168 induces a spin hall torque on the magnetization 154 of the free magnet 112. The spin hall torque rotates the magnetization 154 to a temporary state pointing in the negative x-direction. In an embodiment, to complete the magnetization reversal process an additional torque is applied.

In an embodiment, by application of a voltage V > VT, at terminal B, an ISTTM current 170 flows through the MTJ memory device 104. In an embodiment, a spin polarized electron current 171 flows through the tunnel barrier 1 14 and into the free magnet 1 12. In an embodiment, the spin polarized electron current 171 exerts an additional torque on the magnetization 154 of the free magnet 1 12. The additional torque exerted by the spin polarized electron current 171 causes the magnetization to rotate to the negative z-direction. The combination of spin hall torque and spin transfer torque causes flipping of magnetization 154 in the free magnet 1 12 from the positive z-direction illustrated in Figure 3 A to a negative z-direction illustrated in Figure 3B.

Figure 3C illustrates an SOT memory device switched to a high resistance state after the application of a spin hall current and a spin torque transfer current. Figure 3C illustrates a spin orbit torque (SOT) memory device switched to a low resistance state. In an embodiment, a reversal in the direction of magnetization 154 of the free magnet 1 12 in Figure 3C compared to the direction of magnetization 154 of the free magnet 1 12 in Figure 3B is brought about by (a) reversing the direction of the spin diffusion current 168 in the spin orbit torque electrode 101 and (b) by reversing the direction of the ISTTM current 170. Spin diffusion current 168 herein, refers to a spin diffusion "electron" current.

In an embodiment, by applying a positive bias above V _T on terminal A and connecting terminal B to ground potential, current 160 flows through the FMT oxide selector 130 in the direction illustrated in Figure 3C. The electron current 162 now flows in the negative y-direction and induces a spin diffusion torque on the free magnet 160 in a manner described above. In an embodiment, the spin diffusion torque causes the magnetization 154 in the free magnet 1 12 to temporarily orient in the positive x-direction. In an embodiment, the spin polarized electron current 171 exerts an additional torque on the magnetization 154 of the free magnet 1 12. The additional torque exerted by the spin polarized electron current 171 causes the magnetization to rotate towards the positive z-direction. The combination of spin hall torque and spin transfer torque causes flipping of magnetization 154 in the free magnet 1 12 from the negative z-direction illustrated in Figure 3B back to a positive z-direction illustrated in Figure 3 C.

Figure 3D illustrates a read operation performed on an SOT memory device. In an embodiment, when the applied voltage on terminal A is less than VT, the FMT oxide is in a non- conductive state. In an embodiment, the magnitude of the applied voltage for a read operation is approximately 0.1 -0.25V. In an embodiment, when the MTJ memory device 104 is in a high resistance state, the current 170 through the MTJ memory device 104 is lower compared to the current flowing through the MTJ memory device 104 during an on-state of the device. In an embodiment, when the MTJ memory device 104 is in a low resistance state, current 170 will flow through the MTJ memory device 104. In an embodiment, the current 170 is inversely proportionate to the resistance of the MTJ memory device 104.

Figures 4A- 4L illustrate cross-sectional views representing various operations in a method of fabricating an SOT memory device in accordance with embodiments of the present disclosure.

Figure 4A illustrates a cross-sectional view of the formation of a spin orbit torque electrode layer 401 on a conductive interconnect 400 surrounded by a dielectric layer 404 and formed above a substrate 403, in an accordance with embodiments of the present disclosure. In an embodiment, the conductive interconnect 400 is formed in a dielectric layer 404 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 400 includes a barrier layer, such as titanium nitride, ruthenium, tantalum, tantalum nitride, and a fill metal, such as copper, tungsten. In an embodiment, the conductive interconnect 400 is fabricated using a subtractive etch process when materials other than copper are utilized. In one such embodiment, the conductive interconnect 400 includes a material such as but not limited to titanium nitride, ruthenium, tantalum, tantalum nitride. In an embodiment, the dielectric layer 404 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 404 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 400. In an embodiment, the dielectric layer 404 has a total thickness between 70nm-300nm. In an embodiment, conductive interconnect 400 is electrically connected to a circuit element such as a drain of an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.

In an embodiment, the substrate 403 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 403 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

A spin orbit torque electrode layer 401 is formed on the dielectric layer 404 and on the conductive interconnect 400. In an embodiment, the spin orbit torque electrode layer 401 is a material that is substantially similar to the spin orbit torque electrode 101. In an embodiment, the spin orbit torque electrode layer 401 includes a metal such as Pt, beta-tungsten and beta- tantalum. In an embodiment, the spin orbit torque electrode layer 401 is deposited using a physical vapor deposition process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the spin orbit torque electrode layer 401 has a thickness that is between 2nm-10nm.

In an embodiment, the spin orbit torque electrode layer 401 includes a multilayer stack of metals consisting of two or more layers of metals that can induce spin diffusion currents. In an embodiment, an uppermost layer of metal has a higher spin hall effect angle than a spin hall effect angle of a lowermost layer of metal. In one such embodiment, the multilayer stack of metals includes a layer of platinum deposited on the dielectric layer 404, a layer of beta-tungsten deposited on the layer of platinum and a layer of beta-tantalum deposited on the layer of beta- tungsten. In an embodiment, the combined total thickness of the multilayer stack of metals is between 4nm-10nm.

Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of a photoresist mask 406 on the spin orbit torque electrode layer 401. In an embodiment, the photoresist mask 406 is formed by a lithographic process that is well known in the art. The photoresist mask 406 defines a size of a spin orbit torque electrode that will subsequently be formed. In an embodiment, the photoresist mask 406 has a rectangular shape as is depicted in the plan view illustration of Figure IB. In another embodiment, the photoresist mask 406 has a square shape.

Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the patterning of the spin orbit torque electrode layer 401 to form a spin orbit torque electrode 402. In an embodiment, the spin orbit torque electrode layer 401 is patterned by a plasma etch process selectively to the photoresist mask 406. Upon completion of the etch process, any remaining photoresist mask is subsequently removed.

Figure 4D illustrates a cross-sectional view of the structure in Figure 4C following the deposition of a second dielectric layer 408 and a planarization process. In an embodiment, the second dielectric layer 408 is deposited on the spin orbit torque electrode 402 and on the dielectric layer 404. In an embodiment, the second dielectric layer 408 is substantially the same material as the material of the third dielectric layer 420.

A planarization process is carried out to remove the second dielectric layer 408 above the spin orbit torque electrode 402 and an upper portion of the spin orbit torque electrode 402. In an embodiment, the spin orbit torque electrode 402 and the second dielectric layer 408 surrounding the spin orbit torque electrode 402 have uppermost surfaces that are substantially co-planar following the planarization process. In an embodiment, the planarization process is a chemical mechanical polish process. In an embodiment the planarization process forms a spin orbit torque electrode 402 having a topographically smooth uppermost surface with a surface roughness that is less than lnm. In an embodiment, the spin orbit torque electrode 402 has a resultant thickness between 2nm-10nm after the planarization process.

The plan view Figure 4D (Α-Α'), illustrates the size and shape of the spin orbit torque electrode 402. The spin orbit torque electrode 402 has a length LSOT and a width WSOT. In an embodiment, the spin orbit torque electrode 402 has a length, LSOT, that is between 50nm to 500nm. In an embodiment, the spin orbit torque electrode 402 has a width, WSOT, between 20nm to 40nm.

Figure 4E illustrates a cross-sectional view of the structure in Figure 4D following the formation of a material layer stack 450 for form a magnetic tunnel junction (MTJ) memory device. In an embodiment, formation of the material layer stack 450 includes deposition of a free magnetic layer 409 on the spin orbit torque electrode 402, deposition of a tunnel barrier layer 411 on the free magnetic layer 409, deposition of a fixed magnetic layer 413 on the tunnel barrier layer 411 and deposition of a top electrode layer 415 on the fixed magnetic layer 413.

In an embodiment, the free magnetic layer 409 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, the free magnetic layer 409 includes an alloy such as but not limited to CoFe, CoFeB and FeB. In an embodiment, free magnetic layer 409 includes a layer of Coioo-x- _y Fe _x B _y , where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the layer of Coioo-x-yFe _x B _y , is amorphous as deposited. In an embodiment, the layer of Coioo-x- _y Fe _x B _y , is deposited with a boron content of 10-20% to ensure an amorphous layer is formed. In an embodiment, the free magnetic layer 409 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment, free magnetic layer 409 is deposited to a thickness between 1.0nm-2.5nm. Exemplary thickness of the free magnetic layer 409 is between 1.3nm - 2.3nm.

A tunnel barrier layer 411 is then blanket deposited on the free magnetic layer 409. In an embodiment, the tunnel barrier layer 411 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 411 is a layer of MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room

temperature. In an embodiment, reactive sputter process is carried out at elevated temperatures between 200-400C. In an embodiment, tunnel barrier layer 411 is a layer of MgO and is RF sputtered from a MgO target. In an embodiment, tunnel barrier layer 411 is a layer of MgO and is formed by a reactive oxidation of DC sputtered Mg films.

A fixed magnetic layer 413 is deposited on the tunnel barrier layer 411. In an

embodiment, the fixed magnetic layer 413 is blanket deposited using a physical vapor deposition (PVD) process. In an embodiment, a fixed magnetic layer 413 deposited by a PVD process is amorphous in nature. In an embodiment, the fixed magnetic layer 413 includes an alloy such as but not limited to CoFe, CoFeB and FeB. In an embodiment, fixed magnetic layer 413 includes a Coi-x-yFe _x By, where X and Y each represent atomic percent. In an embodiment, X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnetic layer 413 is blanket deposited to a thickness between lnm-2.5nm. The PVD deposition process ensures that the fixed magnetic layer 413 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate.

In an embodiment, a top electrode layer 415 is blanket deposited on the surface of the fixed magnetic layer 413. In an embodiment, the top electrode layer 415 includes a material that is suitable to act as a hardmask during a subsequent etching of the MTJ material layer stack 450 to form an MTJ device. In an embodiment, the top electrode layer 415 includes a material such as TiN, Ta or TaN. In an embodiment, the thickness of the top electrode layer ranges from 30nm-70nm. The thickness of the top electrode layer 415 is chosen to accommodate patterning requirements of the various sizes of the MTJ devices that will subsequently be fabricated. In an embodiment, a SAF structure similar to the SAF structure 118 is deposited (but not shown) on the fixed magnetic layer 413 prior to depositing the top electrode layer 415.

In an embodiment, the process of depositing the top electrode layer 415 causes in a small uppermost fraction of the fixed magnetic layer 413 to become magnetically dead. In an embodiment, the fixed magnetic layer 413 has magnetically dead portion that is less than 5% of the total thickness of the fixed magnetic layer 413. In an embodiment, the fixed magnetic layer 413 has magnetically dead portion that is between 5%-20% of the total thickness of the fixed magnetic layer 413. In an embodiment, magnetically dead portion of the fixed magnetic layer 413 is not continuous throughout the structure of the fixed magnetic layer 413. By depositing the fixed magnetic layer 413 to a thickness of at least 2.5nm, the fixed magnetic layer 413 can function as a fixed magnet.

In an embodiment, after all the layers in the MTJ material layer stack 450 are deposited, an anneal is performed under conditions well known in the art. In an embodiment, the anneal process enables formation of a crystalline MgO - tunnel barrier layer 411 to be formed. In an embodiment, the anneal is performed immediately post deposition but before patterning of the MTJ material layer stack 450. A post-deposition anneal of the MTJ material layer stack 450 is carried out in a furnace at a temperature between 300-400 degrees Celsius in a forming gas environment. In an embodiment, the forming gas includes a mixture of H ₂ and N ₂ gas. In an embodiment, the annealing process promotes solid phase epitaxy of the free magnetic layer 409 to follow a crystalline template of the tunnel barrier layer 411 (e.g., MgO) that is directly above the free magnetic layer 409. In an embodiment, the anneal also promotes solid phase epitaxy of the fixed magnetic layer 413 to follow a crystalline template of the tunnel barrier layer 411 (e.g., MgO) that is directly below the fixed magnetic layer 413. Lattice matching between the tunnel barrier layer 411 and the free magnetic layer 409 and lattice matching between the tunnel barrier layer 411 and the fixed magnetic layer 413 enables a higher TMR ratio to be obtained in the MTJ material layer stack 450.

In an embodiment, when the free magnetic layer 409 includes boron, the annealing process enables boron to diffuse away from an interface 441 between the free magnetic layer 409 and the tunnel barrier layer 411. The process of diffusing boron away from the interface 431 enables lattice matching between the free magnetic layer 409 and the tunnel barrier layer 411. In an embodiment, when the fixed magnetic layer 413 includes boron, the annealing process enables boron to diffuse away from an interface 441 between the fixed magnetic layer 413 and the tunnel barrier layer 411.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 413, the free magnetic layer 409. In an embodiment, an applied magnetic field that is directed parallel to a vertical axis of the MTJ material layer stack 450, during the annealing process, enables a perpendicular anisotropy to be set in the fixed magnetic layer 413, in the free magnetic layer 409. In an embodiment, the annealing process initially aligns a magnetization of the fixed magnetic layer 413, magnetization of the free magnetic layer 409 to be parallel to each other.

Figure 4F illustrates a cross-sectional view of the structure in Figure 4E following the process of etching the MTJ material layer stack 450 to form a magnetic tunnel junction memory device 460 and following the formation of a dielectric spacer adjacent to the magnetic tunnel junction memory device.

In an embodiment, the patterning process includes lithographically patterning a layer of resist formed (not shown) over the MTJ material layer stack 450. The lithography process defines the shape and size of a MTJ device and a location where the MTJ device is to be subsequently formed with respect the spin orbit torque electrode 402. In an embodiment, the MTJ memory device 460 is formed closer to the conductive interconnect 110. In an

embodiment, the MTJ memory device 460 is formed halfway along the length, LSOT, of the spin orbit torque electrode 402.

In an embodiment, the patterning process includes etching the top electrode layer 415 by a plasma etch process to form a top electrode 416. In an embodiment, plasma etch process possesses sufficient ion energy and chemical reactivity to render vertical etched profiles of the top electrode 416. In an embodiment, the remaining layer of resist above the top electrode 416 is then removed by a plasma ash process.

In an embodiment, the plasma etch process is then continued to pattern the remaining layers of the MTJ material layer stack 450 to form a MTJ memory device 460. The MTJ memory device 460 has a fixed magnet 414, a tunnel barrier 412, and a free magnet 410. The plasma etch process also exposes the spin orbit torque electrode 402 and the underlying second dielectric layer 408. In an embodiment, the plasma etch process is very selective to the material of the spin orbit torque electrode 402.

In an embodiment, a dielectric spacer layer is deposited on the MTJ memory device 460 and on the uppermost surface of the spin orbit torque electrode 402 and on the second dielectric layer 408. In an embodiment, the dielectric spacer layer is deposited without a vacuum break following the plasma etch process. In an embodiment, the dielectric spacer layer includes a material such as but not limited silicon nitride, carbon doped silicon nitride or silicon carbide. In an embodiment, the dielectric spacer layer includes an insulator layer that does not have any oxygen content to prevent oxidation of magnetic layers. In an embodiment, the dielectric spacer layer is etched by a plasma etch process to form a dielectric spacer 418 on sidewalls of the MTJ memory device 460. In an embodiment, the etch process may cause an uppermost portion of the second dielectric layer 408 to become partially recessed leading to partial exposure (not shown) of sidewalls of the spin orbit torque electrode 402.

Figure 4G illustrates a cross-sectional view of the structure in Figure 4F following the formation of a third dielectric layer 420 and a planarization of the third dielectric layer 420 and an uppermost portion of the MTJ memory device 460 and the dielectric spacer 418. In an embodiment, the third dielectric layer 420 is deposited on the spin orbit torque electrode 402 and on the dielectric layer 404. A planarization process is carried out to remove the third dielectric layer 420 above the MTJ memory device 460 and an upper portion of the dielectric spacer 418. In an embodiment, the MTJ memory device 460, the dielectric spacer 418 and the third dielectric layer 420 surrounding the MTJ memory device 460 and the dielectric spacer 418 have uppermost surfaces that are substantially co-planar following the planarization process. In an embodiment, the planarization process is a chemical mechanical polish process.

Figure 4H illustrates a cross-sectional view of the structure in Figure 4G following the formation of a spin orbit torque electrode (SOT) contact 424 on the spin orbit torque electrode 402. In an embodiment, an opening 422 is formed in the third dielectric layer 420. In an embodiment, the opening 422 is filled with a conductive metal such as W, TiN, TaN, or Cu. In an embodiment, the fill metal is also deposited on the uppermost surface of the third dielectric layer 420, on the top electrode 416 and on the dielectric spacer 418. In an embodiment, the fill metal is subsequently planarized. In an embodiment, the SOT contact 424, the top electrode 416, the dielectric spacer 418 and the third dielectric layer 420 surrounding the MTJ memory device 460 and dielectric spacer 418 have uppermost surfaces that are substantially co-planar following the planarization process. In an embodiment, a CMP process is utilized to planarize the fill metal.

In an embodiment, the SOT contact 424 is formed laterally distant from the location of the MTJ memory device 450. In an embodiment, the distance, DSCM, between the SOT contact 424 and the MTJ memory device 450 is maximized to enable a high degree of spin diffusion current to penetrate into the free magnet 410. In one embodiment, the distance, DSCM, is up to 80% of the length LSOT, of the spin orbit torque electrode 402.

Figure 41 illustrates a cross-sectional view of the structure in Figure 4H following the formation of a first electrode layer 425, an insulator to metal transition (EVIT) oxide layer 427, and a second electrode layer 429 on the EVIT oxide layer 427. In an embodiment, the first electrode layer 425 is blanket deposited on uppermost surfaces of the SOT contact 424, the top electrode 416, the dielectric spacer 418 and the third dielectric layer 420. In an embodiment, first electrode layer 425 is deposited to provide a residue free surface for the formation of the EVIT oxide layer 427. In an embodiment, the first selector electrode layer 426 is deposited to protect the MTJ device from any potential damage during a subsequent deposition and etch of the EVIT oxide layer 427. In an embodiment, the first electrode layer 425 is blanket deposited using a PVD or an ALD process. In an embodiment, the first electrode layer 425 includes a metal such as Ta, RU, W, Ti or an alloy such as TiN, TaN, WN. In an embodiment, the first electrode layer 425 is blanket deposited to a thickness of 10-20nm.

The EVIT oxide layer 427 is then deposited on the first electrode layer 425. In an embodiment, depending on the choice of material, the EVIT oxide layer 427 is blanket deposited using a reactive sputtering, magnetron sputtering or an atomic layer deposition process. In an embodiment, the EVIT oxide layer 427 includes a material consisting of an oxide of an element selected from the group consisting of niobium, vanadium and tantalum. In an embodiment, the EVIT oxide layer 427 includes an oxide such as vanadium (IV) oxide, V0 ₂ and vanadium (V) oxide, V2O5, niobium (V) oxide, Nb ₂ 05 and Ta (V) oxide, Ta ₂ 0 ₅ . In an embodiment, the EVIT oxide layer 427 is amorphous as deposited and has a columnar grain boundary. In another embodiment, the EVIT oxide layer 427 is crystalline as deposited. In an embodiment, the EVIT oxide layer 427 is crystalline after an electroforming process as will be described further below. In an embodiment, the IMT oxide layer 427 is in a monoclinic phase (insulating) or in a rutile phase (metallic) after an electroforming process. In an embodiment, the EVIT oxide layer 427 is deposited to a thickness between lOnm and 50nm.

In an embodiment, the second electrode layer 429 is blanket deposited on uppermost surfaces of the EVIT oxide layer 427. In an embodiment, the second electrode layer 429 includes a metal such as Ta, RU, W, Ti or an alloy such as TiN, TaN, WN. In an embodiment, the second electrode layer 429 is blanket deposited using a PVD or an ALD process. In an embodiment, the second electrode layer 429 is blanket deposited to a thickness of 10-20nm.

Figure 4J illustrates a cross-sectional view of the structure in Figure 41 following the process of patterning the material layer stack to form an EVIT oxide selector 432 on the SOT contact. In an embodiment, the patterning process includes lithographically patterning a layer of resist formed (not shown) over the second electrode layer 429. The lithography process defines the shape and size of EVIT oxide selector device 432 and a location where the EVIT oxide selector device 432 is to be subsequently formed with respect the spin orbit torque electrode 402 and with respect to the MTJ memory device 450.

In an embodiment, the patterning process includes etching the second electrode layer 429 by a plasma etch process to form a second selector electrode 430. In an embodiment, the plasma etch process is continued to pattern the EVIT oxide layer 427 to form an EVIT oxide 428 and pattern the first electrode layer 425 to form a first selector electrode 426. In an embodiment, the plasma etch process recesses a portion of the third dielectric layer 420. In an embodiment, the plasma etch process exposes the top electrode 416 and the uppermost portion of the dielectric spacer 418. In an embodiment, the remaining layer of resist above the top electrode 416 is then removed by a plasma ash process. In an embodiment, the EVIT oxide selector 432 has a width, Ws, that is greater than a width, Wsc, of the sot contact 424.

Figure 4K illustrates a cross-sectional view of the structure in Figure 4J following the formation of a fourth dielectric layer 434 on the EVIT oxide selector device and on the MTJ memory device and followed by a process of planarization. In an embodiment, the fourth dielectric layer 434 is blanket deposited on the EVIT selector 432, on the second third dielectric layer 420, on the dielectric spacer 418 and on the top electrode 416. In an embodiment, the fourth dielectric layer 434 is substantially the same material as the material of the third dielectric layer 420. In an embodiment, the fourth dielectric layer 434 is deposited to a thickness of 100nm-200nm. In an embodiment, the fourth dielectric layer 434 is subsequently planarized to provide a planar surface for forming contact electrodes to contact the MTJ memory device 450 and the EVIT oxide selector 432.

Figure 4L illustrates a cross-sectional view of the structure in Figure 4K following the formation of a selector contact on the EVIT oxide selector device and an MTJ contact on the MTJ memory device. In an embodiment, an opening 435 is formed in the fourth dielectric layer 434 and a selector contact 436 is formed in the opening 435. In an embodiment, an opening 437 is formed above the MTJ memory device 450 and an MTJ contact 438 is formed in the opening

437. In an embodiment, selector contact 436 includes a material that is substantially the same as the material of SOT contact 424. In an embodiment, the MTJ contact 438 includes a material such as but not limited to TiN, W, TaN, Ru. The MTJ contact 438 and the selector contact 436 are subsequently connected by a bridge contact 440. In an embodiment, bridge contact 440 includes a material that is the same or substantially same as the material of the SOT contact 424. In an embodiment, bridge contact 440 includes a material that is the same or substantially same as the material of the selector contact 436. In an embodiment, the selector contact 436 is formed before the MTJ contact 438. In an embodiment, the selector contact 436 is formed after the MTJ contact 438. In an embodiment, the selector contact 436 is formed at the same time as the MTJ contact 438.

Figure 5 illustrates a spin orbit torque (SOT) memory device, such as the spin orbit torque memory device 100 coupled with a transistor 500. In an embodiment, the transistor 500 is disposed on a substrate 501.

In an embodiment, the transistor 500 has a source region 502, a drain region 504 and a gate 506. The transistor 500 further includes a gate contact 514 disposed above and electrically coupled to the gate 506, a source contact 516 disposed above and electrically coupled to the source region 502, and a drain contact 518 disposed above and electrically coupled to the drain region 504 as is illustrated in Figure 5. In an embodiment, an SOT memory device such as a SOT memory device 100 described in association with Figure 1 A is disposed above the transistor 500. In an embodiment, the SOT memory device 100 includes a spin orbit torque electrode, such as spin orbit torque electrode 101 , a magnetic tunnel junction memory device such as MTJ memory device 104 disposed on the spin orbit torque electrode 101 , an FMT oxide selector such as FMT oxide selector 106 disposed on the spin orbit torque electrode 101 and laterally spaced apart from the MTJ memory device 104, and a conductive interconnect structure such as conductive interconnect structure 108 disposed on and coupled to the FMT oxide selector 106 and to the MTJ memory device 104. In an embodiment, the spin orbit torque electrode 101 is disposed on the drain contact 518 of the transistor 500.

In an embodiment, the MTJ memory device 104 includes individual functional layers that are described in association with Figure 1 A. In an embodiment, the FMT oxide selector 106 has individual functional layers that are described in association with Figure 1 A. In an embodiment, the spin orbit torque electrode 101 has a length, LSOT, that is less than a distance of separation, L _D S between the drain contact 518 and the source contact 516. In an embodiment, a portion of the spin orbit torque electrode 101 extends above the gate electrode 512 and the gate contact 514. In an embodiment, a portion of the spin orbit torque electrode 101 extends over the gate electrode 512. In an embodiment, the spin orbit torque electrode 101 is in a first y-z plane as illustrated in Figure 5. In an embodiment, the gate contact 514 is directly below the spin orbit torque electrode 101. In an embodiment, a wordline contact is disposed onto the gate contact 514 on a second y-z plane behind (into the page) the first y-z plane of the spin orbit torque electrode 101. The spin orbit torque electrode 101 does not contact the wordline contact is disposed on the gate electrode 512. In an embodiment, the MTJ device 104 is laterally spaced from the drain contact 518 by a distance A. In an embodiment, the MTJ device 104 is laterally spaced from the EVIT oxide selector 106 by a distance B. In an embodiment, distance A = 0. In an embodiment, both B and A are non zero. In an embodiment, the MTJ memory device 104 is laterally halfway between the EVIT oxide selector 106 and the drain contact 518, i.e. A = B. In an embodiment, when A= 0, the MTJ device 104 is above the drain contact 518. In an embodiment, the MTJ memory device is laterally closer to EVIT oxide selector 106 than to the drain contact 518 (B > A). In an embodiment, the MTJ memory device is laterally closer to the drain contact 518 than to the EVIT oxide selector 106 (B < A). In an embodiment, shifting the location of the MTJ memory device 104 does not alter the spin transfer torque current through the MTJ memory device 104. In an embodiment, the voltage polarity the magnitude of the spin diffusion current is affected by shifting the location of the MTJ memory device 104.

In an embodiment, the transistor 500 associated with substrate 501 is a metal-oxide- semiconductor field-effect transistor (MOSFET or simply MOS transistors), fabricated on the substrate 501. In various implementations of the present disclosure, the transistor 500 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. In an embodiment, the transistor 500 is a tri-gate transistor.

In an embodiment, a voltage VDS is applied between the bitline 530 and the sourceline

540 and a wordline 550 is energized above a threshold voltage, VTH on the transistor 500. In an embodiment, when the applied voltage VDS exceeds a threshold turn on voltage VTS, the EVIT oxide selector 106 undergoes a filamentary conduction process. In an embodiment, the filamentary conduction process allows charge current to flow through the EVIT oxide selector 106. In an embodiment, an electron current (spin hall current) flows through the spin orbit torque electrode 101 and causes a spin diffusion current to flow toward the MTJ memory device 104. The spin diffusion current will exert a torque on the magnetization of the free magnet 112 of the MTJ memory device 104. In an embodiment, by applying a voltage VDS between bitline 530 and sourceline 540, current can flow through the MTJ memory device 104. In an embodiment, a voltage VDS that is equal to or greater than the threshold voltage VTS is enough to generate spin polarized current through the MTJ memory device 104. In one embodiment, the spin transfer torque current flowing through the MTJ memory device 104 also imparts torque to the free magnet 112 adding to the torque from the spin diffusion current. In an embodiment, the combined effect of the spin transfer torque and the spin diffusion torque can switch the magnetization of the free magnet 112. In an embodiment, by reversing the polarity of the voltage VDS, and applying a voltage that meets or exceeds a threshold voltage, -VTS, the direction of magnetization of the free magnet 112 is switched back to a previous configuration.

In an embodiment, by applying a voltage between a bitline 530 and sourceline 530, and by applying a voltage above a threshold voltage, VTH on the wordline 550 of the transistor 500, the MTJ memory device 104 can undergo magnetization switching without the need for an additional voltage source (e.g. a second transistor). In an embodiment, implementing an SOT memory device 100 above a transistor can increase the number of SOT memory devices 100 in a given area of a die by at least a factor of two.

Referring again to Figure 5, in an embodiment, the underlying substrate 501 represents a surface used to manufacture integrated circuits. In an embodiment, the substrate 501 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, the substrate 501 includes other semiconductor materials such as germanium, silicon germanium, or a suitable group III-V or group III-N compound. The substrate 501 may also include semiconductor materials, metals, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the transistor 500 includes a gate stack formed of at least two layers, a gate dielectric layer 510 and a gate electrode layer 512. The gate dielectric layer 510 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 510 to improve its quality when a high-k material is used.

The gate electrode layer 512 of the transistor 500 is formed on the gate dielectric layer 510 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 512 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 512 with a workfunction that is between about 4.9 eV and about 5.2 eV. For an MOS transistor, metals that may be used for the gate electrode layer 512 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 512 with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode layer 512 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 512 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode layer 512 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 512 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the present disclosure, a pair of gate dielectric layer 510 may be formed on opposing sides of the gate stack that bracket the gate stack. The gate dielectric layer 510 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 502 and drain region 504 are formed within the substrate adjacent to the gate stack of the transistor 500. The source region 502 and drain region 504 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 502 and drain region 504. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 502 and drain region 504. In some implementations, the source region 502 and drain region 504 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in-situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 502 and drain region 504 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 502 and drain region 504.

In an embodiment, the gate contact 514 and drain contact 518 of the transistor 500 are disposed in a first dielectric layer 520 disposed above the substrate 501. In an embodiment, the spin orbit torque electrode 101 is disposed in a second dielectric layer 522 disposed on the first dielectric layer 520. In an embodiment, a third dielectric layer 524 is disposed on the second dielectric layer 522. In an embodiment, a fourth dielectric layer 526 is disposed on the third dielectric layer 524. In an embodiment, a source contact 516 is partially disposed in the fourth dielectric layer 526, partially disposed in the third dielectric layer 524, partially disposed in the second dielectric layer 522 and partially disposed on the first dielectric layer 520. In an embodiment, the spin orbit torque electrode contact 128 is disposed in the third dielectric layer 524 on the spin orbit torque electrode 101. In an embodiment, the conductive interconnect structure such as conductive interconnect structure 108 disposed in the fourth dielectric layer 526.

In an embodiment, the third dielectric layer 524, and the fourth dielectric layer 526 are the same or substantially the same as the first dielectric layer 102 and the second dielectric layer 130, and the third dielectric layer 134, respectively.

Figure 6 illustrates a computing device 600 in accordance with one embodiment of the disclosure. The computing device 600 houses a motherboard 602. The motherboard 602 may include a number of components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the motherboard 602. In some implementations the at least one communication chip 606 is also physically and electrically coupled to the motherboard 602. In further implementations, the communication chip 606 is part of the processsor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 606 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 6G, and beyond. The computing device 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as a spin orbit torque (SOT) memory device 100, fabricated using methods described in association with Figure 4A-4L, in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes a magnetic tunnel junction based memory device elements such as SOT memory device 100 integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 600 may contain a stand-alone integrated circuit memory die that includes one or more memory elements such as SOT memory device 100, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

Figure 7 illustrates an integrated circuit (IC) structure 700 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 700 is an intervening structure used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The memory module may include one or more memory devices such as a SOT memory device 100. Generally, the purpose of an integrated circuit (IC) structure 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the integrated circuit (IC) structure 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the integrated circuit (IC) structure 700. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 700.

The integrated circuit (IC) structure 700 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 700 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure 700 may include metal interconnects 708 and via

710, including but not limited to through-silicon vias (TSVs) 710. The integrated circuit (IC) structure 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, memory device such as SOT memory device 100, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 700. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 700.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a SOT memory device 100. A large array of consisting of SOT memory device 100 may be used in an embedded non- volatile memory application.

Thus, embodiments of the present disclosure include reduced area spin orbit torque (SOT) memory devices and methods to form the same.

Specific embodiments are described herein with respect to spin orbit torque devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices such as in-plane STTM or perpendicular STTM devices.

Example 1 : A memory device includes a spin orbit torque electrode. A magnetic tunnel Junction (MTJ) device is disposed above the spin orbit torque electrode. An insulator-metal transition (IMT) oxide selector is disposed above and coupled to the spin orbit torque electrode and laterally spaced apart from the MTJ memory device. A conductive interconnect structure is coupled to the EVIT oxide selector and to the MTJ memory device and a spin orbit torque electrode contact is coupled to the spin orbit torque electrode, distant from the insulator-metal transition (EVIT) oxide selector.

Example 2: The memory device of example 1, wherein the MTJ memory device further includes, a free magnet, a tunnel barrier above the free magnet, a fixed magnet above the tunnel barrier, and a top electrode above the fixed magnet.

Example 3 : The memory device of example 1 or 2, wherein the EVIT oxide selector is non-coplanar with the MTJ memory device.

Example 4: The memory device of example 1, wherein the EVIT oxide selector includes a material that exhibits filamentary conduction.

Example 5: The memory device of example 1 or 4, wherein the EVIT oxide selector includes an oxide of an element selected from the group consisting of niobium, vanadium and tantalum.

Example 6: The memory device of example 5, wherein the EVIT oxide selector includes a dopant selected from the group consisting of silver, copper and gold.

Example 7: The memory device of example 6, wherein the dopant concentration is less than or equal to 10 atomic percent of the total composition of the EVIT oxide selector layer.

Example 8: The memory device of example 1, or 4, wherein the EVIT oxide selector has a thickness between lOnm and 50nm. Example 9: The memory device of example 1, wherein the EVIT oxide selector has a resistivity that is between O. lmOhm-cm and lOhm-cm when measured at a voltage of approximately 0.1V.

Example 10: The memory device of example 1, wherein the conductive interconnect structure further includes a first via on and coupled to the EVIT oxide selector and a second via on and coupled with the MTJ memory device.

Example 11 : The memory device of example 1, wherein the spin orbit torque electrode includes a metal selected from the group consisting of tantalum, tungsten and platinum.

Example 12: An apparatus includes a transistor above a substrate. The transistor includes a gate, a source and a drain, a drain contact on the drain, a source contact on the source, and a gate contact on the gate. A spin orbit torque electrode is disposed above the drain contact. A magnetic tunnel junction (MTJ) memory device is disposed on the spin orbit torque electrode and an insulator-metal transition (EVIT) oxide selector is disposed above and coupled to the spin orbit torque electrode and laterally spaced apart from the MTJ memory device. The apparatus further includes a conductive interconnect structure coupled to the EVIT oxide selector and to the MTJ memory device.

Example 13 : The apparatus of example 12, wherein the MTJ memory device further includes a free magnet, a tunnel barrier above the free magnet, a fixed magnet above the tunnel barrier, and a top electrode above the fixed magnet.

Example 14: The apparatus of example 12 or 13, wherein the MTJ memory device is laterally between the EVIT oxide selector and the drain contact.

Example 15: The apparatus of example 12, wherein the MTJ memory device is above the drain contact.

Example 16: The apparatus of example 12, wherein a portion of the spin orbit torque electrode extends over the gate.

Example 17: The apparatus of example 12 or 15, wherein the spin orbit torque electrode has a length, L, that is less than a separation between the drain contact and the source contact.

Example 18: The apparatus of example 12 or 17, wherein the EVIT oxide selector includes an oxide of an element selected from the group consisting of niobium, vanadium and tantalum.

Example 19: The apparatus of example 12, wherein the EVIT oxide selector has a resistivity that is between O. lmOhm-cm and lOhm-cm when measured at a voltage of approximately 0.1V.

Example 20: The apparatus of example 12, wherein the conductive interconnect structure further includes a first via on and coupled to the EVIT oxide selector and a second via on and coupled with the MTJ memory device.

Example 21 : The apparatus of example 12, 15 or 16, wherein the spin orbit torque electrode includes a metal selected from the group consisting of tantalum, tungsten and platinum

Example 22: A method to fabricate a memory device includes fabricating a spin orbit torque (SOT) electrode above a substrate. The method further includes depositing a spin orbit toque electrode layer and patterning the spin orbit torque electrode layer to form a spin orbit torque electrode having an uppermost surface. The method further includes forming a material layer stack for a magnetic tunnel junction (MTJ) memory device on the uppermost surface of the spin orbit torque electrode and etching the material layer stack to form an MTJ memory device over a portion of the spin orbit torque electrode. The method further includes forming a selector electrode on the spin orbit torque electrode, distant from the MTJ memory device. The method further includes forming an insulator-metal transition (JJVIT) oxide layer above the selector electrode, patterning the JJVIT oxide selector layer to form an JJVIT oxide selector, depositing a dielectric layer over the JJVIT oxide selector and the MTJ memory device, planarizing the dielectric layer. The method further includes forming openings in the dielectric layer to form an JJVIT oxide selector contact and to form an MTJ memory device contact. The method further includes forming a conductive bridge to connect the JJVIT oxide selector contact and the MTJ memory device contact.

Example 23 : The method of example 22, wherein forming the JJVIT oxide selector layer further includes doping with one or more elements selected from the group consisting of silver, copper and gold wherein the total amount of the one or more elements is less than or equal to 10 atomic percent of the total composition of the JJVIT oxide selector layer.

Example 24: The method of example 22, wherein forming the material layer stack for a MTJ memory device includes forming a free magnetic layer on the spin orbit torque electrode, forming a tunnel barrier layer above the free magnetic layer, and forming a fixed magnetic layer on the tunnel barrier layer.

Example 25: The method of example 22, wherein forming the memory device includes annealing the material layer stack for the magnetic tunnel junction (MTJ) memory device at a temperature between 350-400 degrees Celsius prior to etching the material layer stack.