Title:
REFERENCE FREQUENCY GENERATING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS
Document Type and Number:
WIPO Patent Application WO/2012/001846
Kind Code:
A1
Abstract:
Disclosed is a reference frequency generating circuit wherein an oscillation circuit (11) increases/reduces the signal levels of oscillation signals (OCSa, OSCb) in a complementary manner, corresponding to transition of the signal levels of the reference clocks (CKa, CKb). An oscillation control circuit (12) compares the signal levels of the oscillation signals (OSCa, OSCb) with a comparison voltage (VR), and the signal levels of the reference clocks (CKa, CKb) are made to transit, corresponding to the comparison results. A reference control circuit (14) increases/reduces the comparison voltage (VR) such that a difference between the signal levels of intermediate signals (Sp), which are proportional to respective amplitudes of the oscillation signals (OCSa, OSCb), and the reference voltage (Vref) is reduced. A reference voltage control circuit (13) increases/reduces the reference voltage (Vref) corresponding to a difference between the frequency of the reference clock (CKref) and that of the reference clock (CKa).
Inventors:
TOKUNAGA YUSUKE
SAKIYAMA SHIRO
SAKIYAMA SHIRO
Application Number:
PCT/JP2011/001786
Publication Date:
January 05, 2012
Filing Date:
March 25, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
TOKUNAGA YUSUKE
SAKIYAMA SHIRO
TOKUNAGA YUSUKE
SAKIYAMA SHIRO
International Classes:
H03B5/20; H03K3/0231; H03L7/08
Foreign References:
JPS61107810A | 1986-05-26 | |||
JP2002135086A | 2002-05-10 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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