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Title:
REFERENCE VOLTAGE GENERATOR
Document Type and Number:
WIPO Patent Application WO/2018/125675
Kind Code:
A1
Abstract:
A reference voltage generation circuit includes (a) a native MOS transistor coupled to between a power supply voltage source, and the output terminal of the reference voltage generation circuit; (b) an enhancement mode MOS transistor coupled between the output terminal and ground; and (c) a filter circuit that are coupled to the gate terminals of both the native MOS transistor, the enhancement mode transistor and the output terminal of the reference voltage generation circuit, in which the filter circuit has a transfer function including one or more zeroes at predetermined noise frequencies.

Inventors:
QIAN, Wei (6664 Clifford Court, Cupertino, California, 95014, US)
LU, Teh-Shang (1102 Jamestown Drive, Sunnyvale, California, 94087, US)
Application Number:
US2017/067315
Publication Date:
July 05, 2018
Filing Date:
December 19, 2017
Export Citation:
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Assignee:
AUCMOS TECHNOLOGIES USA, INC. (2901 Tasman Drive, Suite 109Santa Clara, California, 95054, US)
International Classes:
G05F3/24; H03H7/01
Foreign References:
US5359327A1994-10-25
US20030143796A12003-07-31
US7426146B22008-09-16
US20090195302A12009-08-06
US20100327842A12010-12-30
Attorney, Agent or Firm:
KWOK, Edward et al. (555 Bryant Street, Suite 820Palo Alto, California, 94301, US)
Download PDF:
Claims:
CLAIMS

We claim:

1. A reference voltage generation circuit connected between a power supply voltage source and ground, providing a reference voltage at an output terminal, comprising: a native MOS transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal being coupled to the power supply voltage source, and the source terminal being coupled to the output terminal to provide the reference voltage; an enhancement mode MOS transistor having a gate terminal, a drain terminal and a source terminal, the drain terminal being coupled to the output terminal, and the source terminal being coupled to ground; and a filter circuit coupled to the gate terminal of the native MOS transistor, the gate terminal of the enhancement mode transistor and the output terminal, the filter circuit having a transfer function including one or more zeroes.

2. The reference voltage generation circuit of Claim 1, wherein the filter circuit comprises two or more of: resistors, capacitors and inductors.

3. The reference voltage generation circuit of Claim 1, wherein the drain terminal of the native MOS transistor is coupled to the power supply voltage source by one or more diode-connected additional MOS native transistor that are connected in series.

4. The reference voltage generation circuit of Claim 3, further comprising a switch circuit which, when conducting, allows a current to flow between the power supply voltage source and the additional native MOS transistors.

5. The reference voltage generation circuit of Claim 1, wherein one of the zeroes is provided at 217 Hz.

Description:
REFERENCE VOLTAGE GENERATOR BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to circuit designs. Specifically, the present invention relates to reference voltage generation circuits in an integrated circuit.

2. Discussion of the Related Art

Figure 1 shows conventional reference voltage generation circuit 100. As shown in Figure 1, reference voltage generation circuit 100 includes one or more gate-source connected transistors ("diode-connected transistors") 101, depletion mode transistors 102 and enhancement mode transistor 103, serially connected as shown between power supply voltage VDD and ground. Reference voltage VREF is taken from common terminal 104 shared between enhancement mode transistor 103 and depletion mode transistor 102. (In some instances, depletion mode transistor 102 may be substituted by an enhancement mode transistor, as is understood by those of ordinary skill in the art). Reference voltage VREF at terminal 104 is fed back to the gate terminals of depletion mode transistor 102 and enhancement mode transistor 103. Reference voltage VREF is given by the equation:

VREF = - f k {V T2 ) + V T where Vti and Vn are the threshold voltages of transistors 102 and 103, respectively, Va being a negative value and Vti is a positive value, and ki and are values that depend on the sizes of transistors 102 and 103, respectively. In most MOS transistor designs, many designers use the ratio of its channel width to its channel length to represent the size of a transistor, as is known to those of ordinary skill in the art. ki and are proportional to the capacitance of the MOS capacitor (Cox), and the channel width to channel length ratio (W/L) of their respective transistor. Therefore, if transistors 102 and 103 are sized identically, VREF would equal the sum of their threshold voltages:

In reference voltage generation circuit 100, voltage Vx at terminal 105 satisfies by the following inequality:

Vx > VREF + V DSAT (2) where VDSAT is the voltage drop across the drain terminal and the source terminal of enhancement mode transistor 103 at saturation current. Therefore, voltage Vx is typically biased larger than (VREF + VDSAT), which can be achieved using a replica biasing scheme known to those of ordinary skill in the art.

Typical threshold voltages for depletion mode transistor 102 and enhancement mode transistor 103 are -0.5 volts and 0.7 volts respectively. A typical value for voltage VDSSAT is approximately 0.3 volts. The number of diode-connected transistors 101 is determined by the voltage difference ("headroom") between power supply voltage VDD and voltage Vx.

Reference voltage generation circuit 100 has the disadvantage that it does not operate under a low power supply voltage conditions (e.g., when voltage VDD is lower than 1.8 volts), such may occur in mobile applications. Furthermore, reference voltage generation circuit 100 is also susceptible to noise in mobile applications.

SUMMARY

According to one embodiment of the present invention, a reference voltage generation circuit providing a reference voltage at an output terminal. The reference voltage generation circuit includes (a) a native MOS transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal being coupled to a power supply voltage source, and the source terminal being coupled to the output terminal to provide the reference voltage; (b) an enhancement mode MOS transistor having a gate terminal, a drain terminal and a source terminal, the drain terminal being coupled to the output terminal, and the source terminal being coupled to ground; and a filter circuit coupled to the gate terminal of the native MOS transistor, the gate terminal of the enhancement mode transistor and the output terminal, the filter circuit having a transfer function including one or more zeroes. One of the zeroes may be provided, for example, at 217 Hz. The filter circuit may include two or more of: resistors, capacitors and inductors. The reference voltage generation circuit may further include one or more diode-connected additional MOS native transistor that are connected in series. According to one embodiment, of the present invention, the reference voltage generation circuit may further include a switch circuit which, when conducting, allows a current to flow between the power supply voltage source and the additional native MOS transistors.

The present invention is better understood upon consideration of the detailed description below in conjunction with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows convention reference voltage generation circuit 100. Figure 2 is a schematic diagram showing reference voltage generation circuit 200, according one embodiment of the present invention.

Figure 3 shows filter circuit 250, which may be used to implement filter circuit 208 of reference voltage generation circuit 200 of Figure 2, in accordance with one embodiment of the present invention.

Figure 4 shows filter circuit 280, which may be used to implement filter circuit 208 of reference voltage generation circuit 200 of Figure 2, in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Figure 2 is a schematic diagram showing reference voltage generation circuit 200, according to one embodiment of the present invention. As shown in Figure 2, reference voltage generation circuit 100 includes switch 207, one or more diode-connected native MOS transistors 201 , native MOS transistors 202 and enhancement mode transistor 203, serially connected as shown between power supply voltage VDD and ground. In addition, output terminals 205 and 206 of filter circuit 208 controls the gate terminals of native transistor 202 and enhancement mode transistor 203, respectively. As explained in further detail below, filter circuit 208 provides noise immunity to reference voltage generation circuit 200.

Reference voltage VREF is taken from common terminal 204, which is fed back to filter circuit 208. Filter circuit 208 drives both the gate terminals 210 and 21 1 of native MOS transistor 202 and enhancement mode transistor 203, respectively, and receives reference voltage VREF at terminal 204, Switch 207 may be any transistor provided, when conducting, to allow a current to flow in diode-connected native MOS transistors 201 , native MOS transistors 202 and enhancement mode transistor 203. The design consideration for voltage Vx at terminal 205 is substantially the same as that for voltage Vx at terminal 105 of Figure 1. Unlike depletion mode transistor 102 of Figure 1 - which has a negative threshold voltage of approximately -0.5 volts ~ a native transistor have a near-zero threshold voltage. Accordingly, reference voltage generation circuit 200 may operate even at low power supply voltage conditions.

Filter circuit 208 may be implemented by a RC circuit having zeroes to attenuate noise at one or more selected frequencies. For example, in a mobile telephone, a

conventional ringtone is provided at 217 Hz. If the RC circuit in filter circuit 208 has a transfer function which includes a zero at 217 Hz, reference voltage generation circuit 200 would be provided noise immunity from the ringtone. (As is known to those of ordinary skill in the art, a "zero" in a transfer function is a frequency at which the numerator of the transfer function becomes zero; conversely, a "pole" in a transfer function is a frequency at which the denominator of the transfer function becomes zero). Figure 3 shows filter circuit 250, which may be used to implement filter circuit 208 of reference voltage generation circuit 200 of Figure 2, in accordance with one embodiment of the present invention. As shown in Figure 3, filter circuit 250 includes a resistor connected between As shown in Figure 3, filter circuit 208 includes a resistor of value R and a capacitor of value C. Filter circuit 250 has a transfer function of—^ , where ω is frequency. If the values R and C are selected such that - equals 217 Hz, reference voltage generation circuit 200 would have noise immunity at the 217 Hz.

Figure 4 shows filter circuit 280, which may be used to implement filter circuit 208 of reference voltage generation circuit 200 of Figure 2, in accordance with one embodiment of the present invention. As shown in Figure 4, filter circuit 280 includes resistors of values Ri, R2 and R3 and capacitors of values Ci, C2, and C3. If the values Ri and R3 are selected to be equal, and the values C2 and C3 are selected to be equal, the transfer function will have zeroes at R1C2, R2C2 and R1C1. These zeroes can be used to attenuate noise from specific sources.

The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.