Title:
REFERENCE VOLTAGE STABILIZATION CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2012/157155
Kind Code:
A1
Abstract:
The objective of the present invention is to maintain a reference voltage in a stable manner with respect to disturbance noises and self-noise of an internal circuit. This reference voltage stabilization circuit (10) which stabilizes a reference voltage that is supplied through a first signal line and/or a second signal line (L1 and/or L2) is provided with a pre-stage circuit (1) which has a capacitive path (11) connected between the first signal line (L1) and the second signal line (L2), and a post-stage circuit (2) which has a resistive path (21) which is connected between the first signal line (L1) and the second signal line (L2) and a resistor circuit (22H, 22L) which is inserted into the signal line which supplies the reference voltage among the first and second signal lines (L1, L2) in between the capacitive path (11) and the resistive path (21).
Inventors:
MORIE TAKASHI
SAKIYAMA SHIRO
YANAGISAWA NAOSHI
OZEKI TOSHIAKI
MIKI TAKUJI
SAKIYAMA SHIRO
YANAGISAWA NAOSHI
OZEKI TOSHIAKI
MIKI TAKUJI
Application Number:
PCT/JP2012/001385
Publication Date:
November 22, 2012
Filing Date:
February 29, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
MORIE TAKASHI
SAKIYAMA SHIRO
YANAGISAWA NAOSHI
OZEKI TOSHIAKI
MIKI TAKUJI
MORIE TAKASHI
SAKIYAMA SHIRO
YANAGISAWA NAOSHI
OZEKI TOSHIAKI
MIKI TAKUJI
International Classes:
H03H7/06; H03H11/04; H03M1/08; H03M1/10
Foreign References:
| JP2009089360A | 2009-04-23 | |||
| JPS60142525U | 1985-09-20 | |||
| JP2001142548A | 2001-05-25 | |||
| JP2005244771A | 2005-09-08 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
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