Title:
REGULATOR CIRCUIT, VOLTAGE STABILIZING CIRCUIT, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/207969
Kind Code:
A1
Abstract:
A regulator circuit (10) is provided with: an operation amplifier (11) which receives a reference voltage (VREF) on one input terminal; an output terminal (VO), which has a load circuit (30) connected thereto, and which is feedback-connected to the other input terminal of the operation amplifier (11); an output transistor (12), which receives output signals of the operation amplifier (11) on a gate, and which is connected between a first power supply (VDD) and the output terminal (VO); and a first resistor (14) and a first capacitor (15), which are connected in series between the output terminal (VO) and a second power supply (VSS).
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Inventors:
NOMASAKI DAISUKE
MORIE TAKASHI
YANAGISAWA NAOSHI
MORIE TAKASHI
YANAGISAWA NAOSHI
Application Number:
PCT/JP2014/001713
Publication Date:
December 31, 2014
Filing Date:
March 25, 2014
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H03M1/38; G05F1/56
Foreign References:
| JP2005160013A | 2005-06-16 | |||
| JP2005316788A | 2005-11-10 | |||
| JPH04252313A | 1992-09-08 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
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