RELAXATION^OSCILLATOR^WITH^AN^OFFSET^RESISTOR TECHNICAL FIELD Various example embodiments relate to relaxation oscillators. BACKGROUND A relaxation oscillator is a non-linear electronic oscillator circuit for generating a non-sinusoidal (e.g., a square wave) periodic output signal. The oper- ation of relaxation oscillator is based on periodic charging and discharging of a ca- pacitor. For most relaxation oscillator applications, it is desirable to have zero or at least low temperature coefficient meaning that the output of the relaxation oscilla- tor is not temperature-dependent or is only slightly temperature dependent. While the capacitor of the relaxation oscillator has typically negligible (i.e., close-to-zero) temperature coefficient, the temperature coefficient of the sheet resistance of the relaxation oscillator often has considerably larger positive value. To overcome this issue, a mix of resistors with positive and negative temperature coefficient may be used in the relaxation oscillator to obtain clock with flat temperature coefficient. However, typical Complementary Metal Oxide Semiconductor (CMOS) manufactur- ing processes do not offer resistors with negative temperature coefficients. Even if such resistors are offered in the CMOS manufacturing process, the inclusion of such resistors is costly and considerably complicates the manufacturing process as ad- ditional masks need to be applied during the manufacturing process. BRIEF DESCRIPTION According to a first aspect, there is provided a relaxation oscillator com- prising: first and second current sources; a comparator having a first input connected to the first current source, a second input connected to the second current source and an output, wherein one of the first and second inputs is an inverting input and other one of the first and second inputs is a non-inverting input; a resistive circuit connected between the first input of the comparator and the ground, wherein the resistive circuit comprises at least a first resistor; and a capacitor charging circuit connected between the second input of the comparator and the ground, wherein the capacitor charging circuit comprises a ca- pacitor, a second resistor connected in series with the capacitor and a switch con- nected in parallel with the capacitor, the switch being configured to be controlled based on the output of the comparator. According to a second aspect, there is provided a differential relaxation oscillator comprising: first, second and third current sources; a first comparator having a first input connected to the first current source, a second input connected to the third current source and an output, wherein one of the first and second inputs of the first comparator is an inverting input and other one of the first and second inputs of the first comparator is a non- inverting input; a second comparator having a first input connected to the first current source, a second input connected to the second current source and an output, wherein one of the first and second inputs of the second comparator is an inverting input and other one of the first and second inputs of the second comparator is a non-inverting input, the first input of the second comparator being of the same type as the first input of the first comparator; a resistive circuit connected between the first input of the first compar- ator and the ground, wherein the resistive circuit comprises at least a first resistor; a first capacitor charging circuit connected between the second input of the first comparator and the ground, wherein the first capacitor charging circuit comprises a first capacitor, a second resistor connected in series with the first ca- pacitor and a first switch connected in parallel with the first capacitor; a second capacitor charging circuit connected between the second input of the second comparator and the ground, wherein the second capacitor charging circuit comprises a second capacitor, a third resistor connected in series with the second capacitor and a second switch connected in parallel with the second capac- itor; a third switch connected between the second current source and the first capacitor charging circuit; a fourth switch connected between the third current source and the sec- ond capacitor charging circuit; and a resetting circuit configured to control the first, second, third and fourth switches based on the outputs of the first and second comparators for ena- bling alternating charging of the first and second capacitors and periodic resetting of a charge of the first and second capacitors. The first and second aspects provide the technical effect that a relaxa- tion oscillator or a differential relaxation oscillator for generating a non-sinusoidal periodic output signal is implemented. The first and second aspects provide the following advantages. Due to the inclusion of at least one offset resistor (i.e., the second resistor for the single- ended relaxation oscillator or the second and third resistors for the differential re- laxation oscillator), the temperature-dependency of the implemented relaxation oscillator or differential relaxation oscillator is minimized in a simple but effective manner with a minimal number of required electrical components. Notably, no spe- cial resistor type (namely, resistor types enabling implementation of a negative temperature coefficient) need to be employed to flatten the temperature gradient of the relaxation oscillator or the differential relaxation oscillator. Embodiments are defined in the dependent claims. The scope of protec- tion sought for various embodiments is set out by the independent claims. The embodiments and features, if any, described in this specification that do not fall under the scope of the independent claims are to be interpreted as examples useful for understanding various embodiments of the invention. BRIEF DESCRIPTION OF DRAWINGS In the following, example embodiments will be described in greater de- tail with reference to the attached drawings, in which Figure 1 illustrates a relaxation oscillator according to embodiments; Figure 2A and 2B illustrate, respectively, an implementation of the fall- ing edge delay circuit according to an embodiment and exemplary input and output signals of the falling edge delay circuit; Figures 3A and 3B illustrate exemplary operation of the relaxation os- cillator according to an embodiment Figure 4 illustrates a differential relaxation oscillator according to em- bodiments; Figure 5 illustrates a process carried out by a resetting circuit of a dif- ferential relaxation oscillator according to an embodiment; and Figures 6 illustrates exemplary operation of the differential relaxation oscillator according to an embodiment. DETAILED DESCRIPTION OF SOME EMBODIMENTS The following embodiments are only presented as examples. Although the specification may refer to “an”, “one”, or “some” embodiment(s) and/or exam- ple(s) in several locations of the text, this does not necessarily mean that each ref- erence is made to the same embodiment(s) or example(s), or that a particular fea- ture only applies to a single embodiment and/or example. Single features of differ- ent embodiments and/or examples may also be combined to provide other embod- iments and/or examples. Figure 1 illustrates a relaxation oscillator 100 (or specifically an RC re- laxation oscillator) according to an embodiment for providing a flat frequency re- sponse. The relaxation oscillator 100 may be specifically an integrated relaxation oscillator (i.e., a relaxation oscillator implemented on at least one integrated cir- cuit). For example, the relaxation oscillator 100 may be a CMOS-based integrated relaxation oscillator. The relaxation oscillator 100 comprises a first current source 101 and a second current source 102. The first current source 101 may be configured to output a first current I ₁ , and the second current source may be configured to output a second current I ₂ . In some embodiments, the first and second currents may be (substantially) equal (i.e., I ₁ = I ₂ ). The relaxation oscillator 100 further comprises a comparator 103 hav- ing an inverting input connected to the first current source 101, a non-inverting input connected to the second current source 102 and an output 109 (correspond- ing to an output voltage V _out ). The output 109 of the comparator 103 may also cor- respond to an output of the relaxation oscillator 100. The output 109 of the comparator 103 may correspond to a (binary) digital output. Specifically, the output of the comparator 103 may (at least ideally) have the following logical form: In practice, the logical ‘1’ may be associated with a first voltage (a HIGH voltage) and the logical ‘0’ may be associated with a second voltage (a LOW voltage) which is typically smaller than the first voltage. The comparator 103 may be of any conventional type or model. The comparator 103 may be implemented, e.g., using a (high-gain) differential amplifier (e.g., an operational amplifier or a dedicated comparator chip). The gain of the dif- ferential amplifier is preferably high enough that even a very small difference be- tween the input voltages will saturate the output and thus the output voltage will correspond to either the LOW logic voltage or the HIGH logic voltage, as described above in connection with (1). The relaxation oscillator 100 further comprises a resistive (or resistor) circuit 110 connected between the inverting input of the comparator 103 and the ground (or equally between the output of the first current source 101 and the ground). The resistive circuit 110 comprises at least (or consists of) a first resistor 104 (or a first resistive element), as shown in Figure 1. The first resistor 104 has a first resistance R and a first (positive) temperature coefficient α. The voltage at the node between the first current source 101 and the resistive circuit 110 (or equally between the inverting input of the comparator 103 and the resistive circuit 110) is denoted as V _R . The relaxation oscillator 100 further comprises a capacitor charging cir- cuit 111 connected between the non-inverting input of the comparator 103 and the ground (or equally between the output of the second current source 102 and the ground). The capacitor charging circuit 111 comprises (or, as shown in Figure 1, consists of) a capacitor 105, a second resistor 107 (equally called an offset resistor) connected in series with the capacitor 105 and a switch 106 connected in parallel with the capacitor 105. The capacitor 105 has a capacitance C, the second resistor 107 has a second resistance R ₀ and a second (positive) temperature coefficient α ₀ and the voltage at the node between the second current source 102 and the capac- itor 105 (or equally between the non-inverting input of the comparator 103 and the capacitor 105) is denoted as V _C . The capacitor 105 may also be associated with a third temperature coefficient though typically said third temperature coefficient has a value close to zero (and thus has negligible effect on the temperature coeffi- cient of the relaxation oscillator 100 as a whole). The switch 106 may be an active HIGH switch (i.e., being open when in- put voltage is HIGH). When the switch 106 is open, the capacitor 105 is being charged. Closing the switch 106 enables bypassing the capacitor 105 which causes the capacitor 105 to discharge. It should be noted that while the voltage V _R remains constant during the operation of the relaxation oscillator 100, the voltage V _C is con- stantly rising due to the charging of the capacitor when the switch is open. This charging/discharging operation is discussed in further detail in connection with Figures 3A and 3B. The second resistor 107 R ₀ may be used, in embodiments, specifically to compensate for the positive or negative temperature coefficient of first (sheet) re- sistance R. It should be noted that, without the second resistor R ₀ , the temperature coefficient of relaxation oscillator 100 as a whole would be highly dependent on said temperature coefficient of the first resistor 104 (R). In other words, the second resistor R ₀ (i.e., the offset resistor) is included in the capacitor charging circuit 111 to offset the temperature coefficient of the first resistor R from the (adjacent) re- sistive circuit 110 so as to flatten the temperature gradient of the relaxation oscil- lator 100 as a whole. The first and/or second resistors 104, 107 may be, for example, resis- tors of any of the following types (or a combination of one or more types): diffusion, well, pinched well poly and metal. In general, the first and/or second resistors 104, 107 may correspond to any elements providing resistance. In an embodiment, the first resistor (R) 104 is a poly resistor and/or the second resistor (R ₀ ) 107 is a diffusion resistor. In some embodiments, the resistance R of the first resistor 104 may be larger than the resistance R ₀ of the second resistor 107 or even larger than the re- sistance R ₀ of the second resistor 107 multiplied by 2, 3, 4, 5, 6, 7 or 8. The capacitor 105 may correspond to any element providing capaci- tance. Exemplary values for the capacitance C of the capacitor 105 and re- sistances R & R ₀ of the first and second resistors 104, 107 may be, e.g., C = 2.2 pF, R = 6 MΩ and R ₀ = 0.7 MΩ. The relaxation oscillator 100 further comprises a clock divider 108. The clock divider 108 is connected to the output of the comparator 103 and provides an output clock (voltage) signal V _out 109. The clock divider 108 is configured so as to ensure that output clock duty cycle is substantially 50%. In other words, the clock divider 108 is configured to output an output clock signal V _out 109 having a high value substantially 50% of the time and a low value substantially 50% of the time. In some embodiments, the clock divider 108 may be omitted from the relaxation oscillator 100 of Figure 1. For example, it may be provided as a separate element from the relaxation oscillator 100. If the response delay of the comparator 103 is very small, the switch 106 may be closed for too short a time to ensure complete discharge of the capaci- tor C 105. To avoid this, the relaxation oscillator 100 comprises a falling edge delay circuit 113. The falling edge delay circuit 113 is connected between the output of the comparator 103 and the switch 106 for enabling switching of the switch 106 based on the output of the comparator 103 in a delayed manner. Namely, the falling edge delay circuit 113 is configured so as to ensure that the capacitor 105 is com- pletely discharged following the closing of the switch 106. In other words, the fall- ing edge delay circuit 113 ensures that the input of the switch 106 stays HIGH (i.e., “1”) a bit longer than the output of the comparator 103 and Vc completely dis- charges to V _R0 potential. The falling edge delay circuit 113 is discussed in more de- tail below. The switching operation of the relaxation oscillator 100 may work as described in the following. When the output of the comparator 103 indicates that the voltage V _C of the non-inverting input fails to exceed a voltage of the inverting input V _R (e.g., cor- responding to binary output of 0 or LOW value), the switch 106 remains in an open position. In response to the output of the comparator 103 corresponding to a logi- cal one (being indicative of the voltage V _C of the non-inverting input exceeding a voltage of the inverting input V _R ), the switch 106 is closed, leading to discharge of the capacitor 105. This causes the voltage V _C to reset to V _R0 . When the output of the comparator 103 again indicates that the voltage V _C of the non-inverting input fails to exceed a voltage of the inverting input V _R , the switch 106 is returned to the open position which again causes charging of the capacitor 105. Due to the falling edge delay circuit 113, the opening of the switch 106 is delayed in this case, as will be described in detail in connection with Figures 2A and 2B. In some embodiments, the falling edge delay circuit 113 of Figure 1 may be omitted (i.e., the output of the comparator 103 may be connected directly to the switch 106). This may be done especially if the propagation delay resulting from the comparator 103 itself is greater than the duration associated with the discharg- ing process or cycle of the capacitor 105 or if not being able to fully discharge the capacitor 105 can be tolerated. In some alternative embodiments, the order of the inverting and non- inverting inputs of the comparator 103 may be reversed. Thus, the comparator 103 may have a first input connected to the first current source 101, a second input connected to the second current source 102, where one of the first and second in- puts is an inverting input and the other is a non-inverting input. The resistive cir- cuit 110 may be connected between the first input of the comparator and the ground while the capacitor charging circuit 111 may be connected between the second input of the comparator 103 and the ground. If the order of the inverting and non-inverting inputs of the comparator 103 is reversed (compared to the order shown in Figure 1), the output of the comparator 103 may be inverted or alterna- tively the switch 106 may be configured to be an active low switch (i.e., being closed when input voltage is LOW). Figure 2A illustrates an implementation of a falling edge delay circuit 210 according to an embodiment. The falling edge delay circuit 210 of Figure 2A may correspond to the falling edge delay circuit 113 of Figure 1. Referring to Figure 2A, the falling edge delay circuit 210 has an input 211 and an output 214. The falling edge delay circuit comprises a delay element 212 connected to the input 211 and an OR gate 213 having a first input connected to the delay element 212 and a second input connected to the input 211 of the fall- ing edge delay circuit 210 and an output connected to the output 214 of the falling edge delay circuit 210. The falling edge delay circuit 210 works as follows. When the input 211 is equal to 0 (and has been equal to 0 for some time), the delayed signal has the same value of 0 and thus output 214 of the falling edge delay circuit 210 is also equal to 0. When the value of the input 211 of the falling edge delay circuit 210 switches from 0 to 1, the output of the OR gate 213 (and thus the output 214 of the falling edge delay circuit 210) switches also from 0 to 1 while the output 214 of the delay element 212 remains 0 for a pre-defined amount of time until also eventually switching from 0 to 1. When the value of the input 211 of the falling edge delay circuit 210 switches to 0, the output 214 of the falling edge delay circuit 210 re- mains 1 for a pre-defined length of time defined by the delay element 212 equiva- lent to falling edge delay between the input 211 and the output 214. Figure 2B illustrates exemplary input and output signals of the falling edge delay circuit 210 of Figure 2A. Specifically, the input signal 211 is shown on the top half of the figure while the output signal 214 is shown on the bottom half of the figure. Figure 2B clearly illustrates the delay operation described in the previ- ous paragraph, that is, the falling edge of the output signal 214 is delayed by a pre- defined length of time relative to the falling edge of the input signal 211 to ensure (more) complete discharging of the capacitor of the relaxation oscillator. In some embodiments of the relaxation oscillator described in connec- tion with Figure 1 (and Figures 2A and/or 2B), the first and second resistances R and R ₀ and the first and second temperature coefficients α and α ₀ may be selected so as to implement a substantially flat temperature response for the relaxation os- cillator 100 as a whole. In order to keep the temperature gradient of the relaxation oscillator 100 at zero, the following equation for the rate of change of a voltage over R (^ _^ ) with temperature and a rate of change of voltage over R ₀ (^ _^^ ) with temper- ature must hold: ^^ _^ ^^ = _^^ . (2) ^^ ^^ By multiplying each side of (2) with dT and applying Ohm’s law based on Figure 1, the equation may be written as ^(^ · ^) = ^(^ · ^ _^ ). (3) It should be noted that here it assumed the first and second current source provide equal currents (^ _^ = ^ _^ = ^). By applying the differential to the resistance terms (the current I is assumed to be constant) and using the basic definition of the tem- perature coefficient (^^/ ^ = ^ · ^^), equation (3) may be written as Finally, equation (4) may be reordered to give the ratio of the first and second re- sistances R and R0 as: Thus, the first and second resistances R and R0 and the associated first and second temperature coefficients α and α0 may be selected so as to satisfy the equation (5), at least approximately. In practice, the design process for the circuit elements of the relaxation oscillator may be proceed, for example, as follows. First, values for R, C, I1 and I2 may be selected to achieve a desired nominal frequency of the relaxation oscillator and a desired nominal power consumption. Then, value of R0 may be selected based on (5) knowing the value of R and its temperature coeffi- cient ^. In order to ensure as large as possible headroom for the capacitor voltage VC to charge and discharge, the resistor R0 with the highest available temperature coefficient ^ _^ may be selected from the available devices of the CMOS process. As shown in (5), the higher the value of the temperature coefficient ^ _^ is, lower the absolute value required for the sheet resistance R0, and hence the biggest head- room for the capacitor C is achieved. Figure 3A and 3B illustrate exemplary operation of the relaxation oscil- lator of Figure 1. Namely, Figure 3A plots voltages VC (top subfigure) and VR (bot- tom subfigure) against time while Figure 3B plots voltages VR (top subfigure) and VR0 (bottom subfigure) against temperature. As shown in Figure 1 and discussed above, the voltage VC is the voltage at the node between the second current source and the capacitor (or equally between the non-inverting input of the comparator and the capacitor), the voltage VR is the voltage at the node between the first cur- rent source and the first resistor (or equally between the inverting input of the comparator and the first resistor) and the voltage V _R0 is a voltage over the (offset) resistor R ₀ . The horizontal axes of the subfigures of Figures 3A and 3B are aligned with each other. Referring to Figure 3A, the switch is assumed initially to just have been opened. As a result, V _C is initially at zero, but the capacitor of the relaxation oscilla- tor is charging and thus V _C is increasing. On the other hand, V _R remains constant during the operation of the relaxation oscillator (irrespective of the position of the switch). The vertical dashed line in Figure 3A indicates time at which the switch is closed. This causes the capacitor to discharge and thus V _C to drop to zero (while V _R is not changed). When value of the voltage V _C exceeds V _R , the output of the compar- ator 103 changes from low “0” state to high “1” state. This leads to closing of switch 106 in Figure 1, and discharge of the capacitor C 105. Immediately following the closing of the switch, the switch is again opened and thus the capacitor is again charged (as indicated by the rising V _C ). The length of the time that the switch 106 remains closed depends on propagation delay of the comparator 103, discharge rate of capacitor C 105 and additional delay caused by the falling edge delay circuit 113. The voltage level of V _C at which the switch is closed is given by V _C = V _R = RI. In other words, the switch is closed when it is detected that V _C > V _R ,^ i.e., when the output of the comparator has a value (e.g., a value corresponding to a logical one) indicating that V _C > V _R . To ensure complete discharge of the capacitor C 105 when the switch is closed, the falling edge delay circuit 113 causes the switch 106 to stay closed for a bit longer compared to a case where the input 112 would be connected directly to the switch 106. Note that capacitor C 105 discharges to V _R0 potential, which is a product of second current source and R ₀ , namely V _R0 =I ₂ R _0. Referring to Figure 3B, it is evident based on the two subfigures for V _R and V _R0 that V _R and V _R0 depend on the temperature in the same manner. Specifically, the slope (i.e., the temperature derivative) of the two curves in the two subfigures of Figure 3B is equal. In other words, the term ^^ _^ /^^ is equal to ^^ _^^ /^^, as indi- cated in Figure 3B. This corresponds to the condition of (2) discussed above. While above specifically single-ended (i.e., non-differential) relaxation oscillators according to embodiments were described in detail, in other embodi- ments, a differential relaxation oscillator with two offset resistors may be provided. Figure 4 illustrates a differential relaxation oscillator 400 (or specifically a differ- ential RC relaxation oscillator) according to an embodiment for providing a flat fre- quency response. The differential relaxation oscillator 400 may be specifically an integrated relaxation oscillator (i.e., a relaxation oscillator implemented on at least one integrated circuit). For example, the differential relaxation oscillator 400 may be a CMOS-based integrated relaxation oscillator. The operation of the differential relaxation oscillator 400 is, in many ways, similar to the operation of the single-ended relaxation oscillator 100. In gen- eral, both relaxation oscillators are based on the use of offset resistor(s) arranged in series with capacitor(s). Any of the definitions provided in connection with any of Figures 1, 2A, 2B, 3A and 3B for the single-ended relaxation oscillator may apply, mutatis^mutandis, for the differential relaxation oscillator 400 (namely, after taking into account the differential nature of the circuit 400 of Figure 4). In general, it should be noted that the architecture of the differential re- laxation oscillator 400 closely resembles the architecture of the single-ended rela- tion oscillator 100 of Figure 1. The obvious difference between the two architec- tures is that the differential relaxation oscillator 400 comprises the two differential branches defined by elements 402’, 403’, 405’ to 407’, 411’, 420’ and elements 402, 403, 405 to 407, 411, 420, respectively. Each of said branches are, apart from the addition of the third and fourth switches 420’, 420, fully analogous with the circuit defined by elements 102, 103, 105 to 107, 111 of Figure 1. Notably, elements 401, 403, 410 may correspond fully to elements 101, 103, 110 of Figure 1. It should be noted that the falling edge delay circuit 113 and the clock delay circuit 108 as used in the single-ended relaxation oscillator 100 of Figure 1 are not necessary for operation of the differential relaxation oscillator 400 of Fig- ure 4. This is due to the fundamental nature of differential relaxation oscillators. Namely, as capacitors C and C’ (elements 405 and 405’) of the differential relaxation oscillator 400 of Figure 4 are charged and discharged alternately (as opposed to at the same time), the resetting circuit 408 works in a similar manner as the falling edge circuit 113 and the clock delay circuit 108. The differential relaxation oscillator 400 comprises a first current source 401, a second current source 402’ and a third current source 402. The first current source 401 may be configured to output a first current I ₁ , the second cur- rent source may be configured to output a second current I ₂ and the third current source may be configured to output a third current I ₃ . In some embodiments, the first, second and third currents may be (substantially) equal (i.e., I ₁ = I ₂ = I ₃ ). The relaxation oscillator 400 further comprises a first comparator 403’ having an inverting input connected to the first current source 401, a non-inverting input connected to the second current source 402’ and an output. Moreover, the relaxation oscillator 400 comprises a second comparator 403 having an inverting input connected to the first current source 401, a non-inverting input connected to the third current source 402 and an output. The outputs of the first and second comparators 403’, 403 may also correspond to outputs of the relaxation oscillator 400. The first and second comparators 403’, 403 may be defined as discussed above for the comparator 103 of Figure 1. Similar to the relaxation oscillator 100 of Figure 1, the differential relaxa- tion oscillator 400 comprises a resistive (or resistor) circuit 410 connected be- tween the inverting input of the first comparator 403’ (or equal of the second com- parator 403) and the ground. The resistive circuit 410 comprises at least (or, as in Figure 4, exclusively) a first resistor 404. The first resistor 404 has a first resistance R and a first temperature coefficient α. The first resistor 404 may defined as de- scribed for the first resistor 104 of Figure 1. The voltage at the node between the first current source 401 and the resistive circuit 410 (or equally between the in- verting input of the first or second comparator 403’, 403 and the resistive circuit 410) is denoted as V _R , similar to Figure 1. The relaxation oscillator 400 further comprises a first capacitor charg- ing circuit 411’ connected between the non-inverting input of the first comparator 403’ and the ground (or equally between the output of the second current source 402’ and the ground). The first capacitor charging circuit 411’ comprises (or, as shown in Figure 4, consists of) a first capacitor 405’, a second resistor 407’ (equally called a first offset resistor) connected in series with the first capacitor 405’ and a first switch 406’ connected in parallel with the first capacitor 405’. The first capac- itor 405’ has a first capacitance C’, the second resistor 407’ has a second resistance R ₀ ‘ and a second temperature coefficient α ₀ ‘ and the voltage at the node between the second current source 402’ and the first capacitor 405’ (or equally between the non-inverting input of the first comparator 403’ and the first capacitor 405’) is de- noted as V _C1 . Moreover, the relaxation oscillator 400 further comprises a second ca- pacitor charging circuit 411 defined in a similar manner as the first capacitor charg- ing circuit 411’. Namely, the second capacitor charging circuit 411 is connected be- tween the non-inverting input of the second comparator 403 and the ground (or equally between the output of the third current source 402 and the ground). The second capacitor charging circuit 411 comprises (or, as shown in Figure 4, consists of) a second capacitor 405, a third resistor 407 (equally called a second offset re- sistor) connected in series with the second capacitor 405 and a second switch 406 connected in parallel with the second capacitor 405. The second capacitor 405 has a second capacitance C, the third resistor 407 has a third resistance R ₀ and a third temperature coefficient α ₀ and the voltage at the node between the third current source 402 and the second capacitor 405 (or equally between the non-inverting input of the second comparator 403 and the second capacitor 405) is denoted as V _C2 . The first and second capacitors 405’, 405 may also be associated with a fourth and fifth temperature coefficients though typically said fourth and fifth tem- perature coefficients have a value close to zero (and thus have negligible effect on the temperature coefficient of the relaxation oscillator 400 as a whole). In contrast to the relaxation oscillator 100 of Figure 1, the differential relaxation oscillator 400 further comprises third and fourth switches 420’, 420 ar- ranged between the second current source 402’ and the first capacitor charging circuit 411’ and between the third current source 402 and the second capacitor charging circuit 411, respectively. Finally, the differential relaxation oscillator 400 comprises a resetting cir- cuit 408 (e.g., a latch) configured to control the first, second, third and fourth switches 406’, 406, 420’, 420 based on the outputs of the first and second compar- ators 403’, 403 for enabling alternating charging of the first and second capacitors 405’, 405 and periodic resetting of a charge of the first and second capacitors 405’, 405 (while the other one of the first and second capacitors 405’, 405 is charging), as will be discussed in detail in connection with Figures 5A and 5B. The resetting circuit 408 may be configured to control the first, second, third and fourth switches 406’, 406, 420’, 420 so that, at any given time, the state (i.e., open/close state) of the third switch 420’ matches the state of the second switch 406 and the state of the fourth switch 420 matches the state of the first switch 406’. Thus, at any given time, only two of the first, second, third and fourth switches 406’, 406, 420’, 420 are closed (or open). In Figure 4, the resetting circuit 408 corresponds specifically to an SR (set- reset) latch (or flip-flop). The SR latch 408 has a reset (R) input connected to an output of the first comparator 403 and a set (S) input connected to an output of the second comparator 403’. Moreover, the SR latch has a Q output (equally called a second output or a Q2 output) connected to (and controlling) the first and fourth switches 406’, 420 and a Q output (equally called a first output or a Q1 output) connected to (and controlling) the second and third switches 406, 420’. Both input and outputs are logical (binary) inputs, and both outputs are logical (binary) out- puts. The first, second, third and fourth switches 406’, 406, 420’, 420 may be con- figured to be open when a logical zero is received and closed when a logical one is received. The SR latch 408 may have the following truth table: Here, the logical ‘1’ of Q1 may be associated with a first voltage (a HIGH voltage) and the logical ‘0’ of Q2 may be associated with a second voltage (a LOW voltage) which is typically smaller than the first voltage. Similarly, the logical ‘1’ of Q2 may be associated with a third voltage (a HIGH voltage) and the logical ‘0’ of Q2 may be associated with a fourth voltage (a LOW voltage) which is typically smaller than the third voltage. The first and third voltages may or may not be equal. The second and fourth voltages may or may not be equal. It should be noted that the cases R = S = 0 & R = 1 = 1 are not possible under normal operating conditions of the differential relaxation oscillator 400 (i.e., unless there is a fault in the operation of the differential relaxation oscillator 400). In some embodiments, the second resistance R ₀ ‘ may be equal to the third resistance R ₀ . Additionally or alternatively, the first capacitance C’ may be equal to the second capacitance C. In some embodiments, the first, second and third temperature coefficients α, α ₀ ’ and α ₀ are either all positive or all negative. In some embodiments of the differential relaxation oscillator of Figure 4 (and Figure 5), the first, second and third resistances R, R ₀ ’and R ₀ and the first, sec- ond and third temperature coefficients α, α ₀ ‘ and α ₀ may be selected so as to imple- ment a substantially flat temperature response for the differential relaxation oscil- lator 100 as a whole. The equations (2)-(5) written for R and R ₀ of Figure 1 apply, mutatis^mutandis, separately for both R and R ₀ of Figure 4 and R and R ₀ ‘ of Figure 4. Similar to as described for the single-ended relaxation oscillator 100 of Figure 1, the order of the inverting and non-inverting inputs of the first and second comparators 403, 403’ may be reversed. Thus, the first comparator 403 may have a first input connected to the first current source 401, a second input connected to the third current source 402, where one of the first and second inputs of the first comparator 403 is an inverting input and other one of the first and second inputs of the first comparator 403 is a non-inverting input. Furthermore, the second com- parator 403’ may have a first input connected to the first current source 401, a sec- ond input connected to the second current source 402’, where one of the first and second inputs of the second comparator 403’ is an inverting input and other one of the first and second inputs of the second comparator 403’ is a non-inverting input. The first input of the second comparator 403’ may be assumed to be of the same type (i.e., inverting or non-inverting type) as the first input of the first comparator 403. If the order of the inverting and non-inverting inputs of the first and second comparators 403, 403’ is reversed (compared to the order shown in Figure 4), the outputs of the first and second comparators 403, 403’ may be inverted or alterna- tively the first and second switches 406, 406’ may be configured to be an active low switch (i.e., being closed when input voltage is LOW). Figure 5 illustrates a process carried out by a resetting circuit of a dif- ferential relaxation oscillator according to an embodiment. The resetting circuit carrying out the illustrated process may correspond to the resetting circuit 408 of the differential relaxation oscillator 400 of Figure 4. Said process may be per- formed by the resetting circuit in software (i.e., using computer software main- tained in at least one memory of the resetting circuit and defining steps to be exe- cuted by at least one processor of the resetting circuit) or in hardware (i.e., using hardware circuitry such as a latch) or using a combination of hardware and soft- ware. It is assumed, in the following discussion, that that the first and fourth switches (elements 406’ and 420) are initially open and the second and third switches (elements 406 and 420’) are initially closed. This is called in the following a first switching state. The first switching state may correspond logical outputs Q1 = 1 & Q2 = 0. An opposite switching state, i.e., the case where the first and fourth switches (elements 406’ and 420) are closed and the second and third switches (elements 406 and 420’) are open is called in the following a second switching state. The second switching state may correspond logical outputs Q1 = 0 & Q2 = 1. The first and second switching states are mutually exclusive (i.e., only one of them may be active at any given time). The resetting circuit monitors, in block 501, an output of the first com- parator (element 403’) and an output of the second comparator (element 403) or specifically the output voltages thereof. The resetting circuit checks, in block 502, whether the output of the first comparator indicates that a voltage V _C1 of the non- inverting input of the first comparator exceeds a voltage of the inverting input V _R . This may correspond, for example, to checking whether the output of the first com- parator is equal to a logical one (indicating that V _C > V _R ) or equal to a logical zero (indicating that V _C ≤ V _R .). It should be noted that while the voltage V _R remains con- stant during the operation of the differential relaxation oscillator, the voltage V _C1 is constantly rising due to the charging of the first capacitor when the first switch (element 406’) is open and the third switch (element 420’) is closed (i.e., when the first switching state is activated). In response to the output of the comparator indicating that the voltage V _C1 of the non-inverting input of the first comparator fails to exceed a voltage of the inverting input V _R in block 502 (e.g., corresponding to a logical output of 0), the resetting circuit maintains, in block 506, the first, second, third and fourth switches in the first switching state. In response to the output of the first comparator corresponding to a log- ical one (being indicative of the voltage V _C of the non-inverting input exceeding a voltage of the inverting input V _R in block 502), the resetting circuit causes, in block 503, activation of the second switching state so as to discharge the first capacitor. This causes the voltage V _C1 to drop to zero. The resetting circuit also carries out, in block 504, 505, 507, a corre- sponding process based on the output of the second comparator (element 403). Namely, the resetting circuit checks, in block 504, whether the output of the second comparator indicates that a voltage V _C2 of the non-inverting input of the second comparator exceeds a voltage of the inverting input V _R . This may correspond, for example, to checking whether the output of the second comparator is equal to a logical one (indicating that V _C > V _R ) or equal to a logical zero (indicating that V _C ≤ V _R .). It should be noted that the voltage V _C2 is constantly rising due to the charging of the second capacitor when the second switch (element 406) is open and the fourth switch (element 420) is closed (i.e., when the second switching state is acti- vated). In response to the output of the second comparator indicating that the voltage V _C2 of the non-inverting input of the second comparator fails to exceed a voltage of the inverting input V _R in block 506 (e.g., corresponding to a logical output of 0), the resetting circuit maintains, in block 507, the first, second, third and fourth switches in the second switching state. In response to the output of the second comparator corresponding to a logical one (being indicative of the voltage V _C of the non-inverting input exceeds a voltage of the inverting input V _R in block 504), the resetting circuit causes, in block 505, activation of the first switching state so as to discharge the second capacitor. This causes the voltage V _C2 to drop to zero. Following execution of block 505 or 507, the process proceeds back to block 501. In other words, the process is repeated. Thus, as may be observed from Figure 5, the resetting circuit is config- ured to activate in turns the first and second switching states so that the first and second capacitors may be charged and discharged periodically. It should be noted that only one of the first and second capacitor is charging at any given time. While one of the first and second capacitors is charging, the other of the first and second capacitors (and the associated differential branch) is in a discharged state. Figure 6 illustrates exemplary operation of the differential relaxation oscillator of Figure 4. Namely, Figure 6 plots voltages V _C1 , V _C2 , V _R , Q1 and Q2 against time. As shown in Figure 4 and discussed above, the voltage V _C1 is the voltage at the node between the second current source 402’ and the first capacitor 405’ (or equally between the non-inverting input of the first comparator 403’ and the first capacitor 405’), the voltage V _C2 is the voltage at the node between the third current source 402 and the second capacitor 405 (or equally between the non-inverting input of the second comparator 403 and the second capacitor 405), the voltage V _R is the voltage at the node between the first current source 401 and the first resistor 404 (or equally between the inverting input of the first/second comparator and the first resistor 404). The subfigures of Figure 6 share the same horizontal axis. Referring to Figure 6, the first and fourth switches 406’, 420 are initially closed while the second and third switches 406, 420’ are open (i.e., the second switching state is active). As a result, V _C1 is initially at zero while V _C2 is non-zero and rising (i.e., the second capacitor is charging). This corresponds to a case where Q1 has a LOW value (corresponding to a logical zero) and Q2 has a HIGH value (cor- responding to a logical one). On the other hand, V _R remains constant during the operation of the differential relaxation oscillator (irrespective of the position of the first, second, third and fourth switches), similar to Figure 3A. When V _C2 exceeds V _R (= RI), the first switching state is activated (and thus the second switching state is deactivated) which, in turn, causes charging of the first capacitor (as evidenced by rising V _C1 ) and discharging of the second capac- itor (as evidenced by V _C2 going to zero). This corresponds to a case where Q1 has a HIGH value (corresponding to a logical one) and Q2 has a LOW value (correspond- ing to a logical zero). Similarly, when V _C1 exceeds V _R (= RI), the second switching state is again activated (and thus the first switching state is deactivated) which, in turn, causes again charging of the second capacitor (as evidenced by rising V _C2 ) and discharging of the first capacitor (as evidenced by V _C1 going to zero). This corresponds to a case where Q1 has a LOW value (corresponding to a logical zero) and Q2 has a HIGH value (corresponding to a logical one). The operation described above is then re- peated. While Figure 3B was discussed above in relation to the single-ended re- laxation oscillator 100 of Figure 1, Figure 3B may equally be seen to depict the behavior of the differential relaxation oscillator 400 of Figure 4. Further, the volt- age V _R0 ’ shown in Figure 4 may exhibit the same temperature-dependent behavior as depicted for V _R0 in Figure 3B. The embodiments provide at least the following advantages. Simplicity^and^low^cost:^The inclusion of an offset resistor R ₀ in the relaxation oscillator enables overcoming the aforementioned problem relating to the positive temperature coefficient of the sheet resistance of the relaxation oscil- lator in a simple and cost-effective manner. For example, no special resistor type (namely, resistor types enabling implementation of a negative temperature coeffi- cient) need to be employed to flatten the temperature gradient of the relaxation oscillator. A typical CMOS process does not offer resistors with negative tempera- ture coefficients. In some CMOS processes, such resistors may be available though they require additional masks to be applied during production in the CMOS process which makes the manufacturing process more complex and expensive. Moreover, making the first and second current sources identical (i.e., setting ^ _^ = ^ _^ = ^) for the single-ended relaxation oscillator or making the first, second and third current sources equal (i.e., setting ^ _^ = ^ _^ = ^ _^ = ^) for the differential relaxation oscillator enables obtaining a better duty cycle and a more reliable clock. Temperature com- pensation by inclusion of an offset resistor R ₀ is simpler, and requires fewer elec- trical components to implement than other compensation techniques. Reliability: The first and second resistors R and R ₀ for the single-ended relaxation oscillator or all of the first, second and third resistors R,^R ₀ ’ and R ₀ for the differential relaxation oscillator can be placed close to each other to obtain good matching. Similar or same resistor types may be chosen to obtain process cor- relation. Embodiments described herein are applicable to systems defined above but also to other systems. The specifications of the systems and their elements de- velop rapidly. Such development may require extra changes to the described em- bodiments. Therefore, all words and expressions should be interpreted broadly and they are intended to illustrate, not to restrict, the embodiment. It will be obvi- ous to a person skilled in the art that, as technology advances, the inventive con- cept can be implemented in various ways. Embodiments are not limited to the ex- amples described above but may vary within the scope of the claims.