BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), to name a few examples. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. Some FETs have a fourth terminal called, the body or substrate, which can be used to bias the transistor. A metal-oxide- semiconductor FET (MOSFET) is configured with an insulator between the gate and the body of the transistor, and MOSFETs are commonly used for amplifying or switching electronic signals. In some cases, MOSFETs include side-wall or so-called gate spacers on either side of the gate that can help determine the channel length and can help with replacement gate processes, for example. Complementary MOS (CMOS) structures typically use a combination of p-type MOSFETs (p- MOS) and n-type MOSFETs (n-MOS) to implement logic gates and other digital circuits.

A finFET is a transistor built around a thin strip of semiconductor material (generally referred to as a fin). The transistor includes the standard FET nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a finFET design is sometimes referred to as a tri-gate transistor. Tri-gate transistors are one example of non-planar transistor configurations, and other types of non-planar configurations are also available, such as so-called double-gate transistor configurations, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). Another non-planar transistor configuration is a gate-all-around configuration, which is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires (or nanoribbons) are used and the gate material generally surrounds each nanowire. BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1A-1H illustrate example perspective views of integrated circuit structures resulting from a method configured to form non-planar transistors including at least one group IV semiconductor material released channel body, in accordance with some embodiments of the present disclosure.

Figures 2A-2D illustrate example cross-section views of integrated circuit structures resulting from a method configured to form non-planar transistors including at least one group IV semiconductor material released channel body, in accordance with some embodiments of the present disclosure. Note that Figures 2A-2D are cross-sectional views taken along plane A of Figure 1H.

Figure 3 illustrates an example perspective view of an integrated circuit including a gate- all-around transistor configuration including a released channel body having a group IV material nanowire, in accordance with some embodiments of the present disclosure.

Figure 4 illustrates a methodology for forming an integrated circuit that includes a non- planar transistor having a group IV semiconductor material released channel body, in accordance with an example embodiment of the present disclosure.

Figures 5A-E each illustrates an example cross-sectional view of an integrated circuit structure configured with a transistor including a group IV semiconductor material released channel body, in accordance with an embodiment of the present disclosure. The cross-section is taken perpendicular to the fin and through the channel region.

Figure 6 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with some embodiments of this disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes, In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for forming transistor structures including a first group IV semiconductor channel body grown on and then released from a second group IV semiconductor sub-fin material layer. The release process is carried out during a replace metal gate (RMG) process, wherein a selective etch is used to remove at least a portion of the underlying sub-fin without removing (or otherwise only minimally removing) the channel material. An insulator material is then grown between the sub-fin and channel materials. In some example cases, a fin comprised of a first group IV semiconductor material, such as Si, is formed on a substrate, shallow trench isolation (STI) material is formed on either side of the fin, and a portion of each fin is then recessed. A second group IV semiconductor material cap layer, such as Ge or silicon germanium (SiGe), or carbon doped equivalents with up to 3% carbon, is grown directly on the recessed fin. The cap layer is generally referred to herein as the channel body (or simply channel, for brevity), and the recessed fin is generally referred to as the sub-fin or sub-channel. Thereafter, a portion of the STI material is removed to expose the fin structure including both the cap (channel) and at least a portion of the underlying sub-fin. A dummy gate structure is then added, along with source/drain regions as well isolation material to provide structural support for the subsequent channel release and RMG processes. In more detail, after the source/drain regions have been provided, and the isolation material is provided and planarized, the dummy gate structure is removed to reveal the channel and a portion of the underlying sub-fin. A selective etch is then carried out so that a portion of the sub-fin is removed to release the channel body, thereby providing a gap between the channel and the underlying sub -fin. Note that the release process tends to cure or otherwise reduce defects (due to lattice mismatch between cap and sub-fin materials) at an interface between the sub-fin and the cap layer. In some cases, an insulator fill material is formed within the gap between the sub-fin and the cap layer, followed by a standard high-k gate dielectric and metal gate processing to cover the other three sides of the exposed channel body, thereby effectively providing a tri-gate configuration. The insulator fill material can be any suitable insulator material but in some embodiments is, for example, a standard oxide (e.g., such as silicon dioxide) or a low-k oxide (e.g., porous silicon dioxide). Other embodiments may use the high-k gate dielectric and gate metal process to not only provide the gate dielectric and electrode materials but to also fill the gap, thereby effectively providing a gate-all-around configuration. Still other embodiments may use any number of other insulator materials, as will be appreciated. Numerous configurations and variations will be apparent in light of this disclosure.

General Overview

Controlling the quality of and the interface between the sub-fin structure and the channel region is a challenge. This is particularly challenging for transistors including an interface between group IV semiconductor materials having diverse lattice constants, such as the case with a silicon sub-fin and a germanium-rich cap layer. Techniques to address such interface issues include buffer systems including one or more buffer layers having a component that is graded in concentration from a lower level compatible with the sub -fin material to a higher level compatible with high mobility. An example such buffer structure is a SiGe buffer layer having a Ge concentration that is graded from around 10 atomic percent or less near the underlying silicon sub-fin to over 60 or 80 atomic percent near the above Ge-rich channel region. However, buffer system techniques can result in interface traps at the boundary of STI material and the buffer layer.

Thus, and in accordance with one or more embodiments of the present disclosure, techniques are provided for forming transistor structures including a channel body that is released from its underlying sub-fin. For example, a native fin of a first group IV semiconductor material is formed on a substrate. The fin is then recessed by an amount suitable for the desired channel body height (e.g., by about 20 nm to 60 nm, in accordance with some embodiments), and a cap layer of a second group IV semiconductor material is grown directly on the recessed fin. This cap and sub-fin arrangement is then exposed during a replace metal gate or so-called RMG process. However, prior to gate deposition, a selective etch is carried out to provide a released cap (channel). As will be appreciated, group IV semiconductor materials include at least one group IV element, such as Si, Ge, carbon (C), SiGe, silicon with carbon doping (Si:C), and so forth.

In some embodiments, the techniques may include forming silicon fins on a bulk silicon substrate, forming an STI material such as silicon dioxide on either side of each of the fins, and then recessing a portion of each fin to define a sub-fin. A Ge or SiGe cap layer is then deposited on the sub-fin. Note that any defects formed at the interface between the sub-fin and cap (e.g., due to lattice mismatch between silicon and germanium) need not be a concern, given the subsequent release process, as will be appreciated. Then, a portion of the STI material is recessed below a top surface of the cap layer. A dummy gate structure is deposited, and source/drain regions can be provided using standard processing. In some embodiments, the source/drain regions can be native fin material that is doped via ion-implantation to provide a desired polarity (e.g., Si fin doped with phosphorus to provide n-type source/drain regions, or boron to provide p-type source/drain regions). In other embodiments, the fin material in the source/drain regions is etched away and replaced with an epitaxial deposition of desired source/drain material that is doped to provide a desired polarity (e.g., epitaxial SiGe doped with boron to provide p-type source/drain regions).

Once the dummy gate structure and source/drain regions are in place, additional insulation material such as silicon dioxide or any other suitable insulator material is deposited and planarized. The dummy gate structure is then removed, revealing the channel body and at least a portion of the underlying sub-fin. Prior to any gate material deposition, at least a portion of the sub-fin is etched out or otherwise removed via an etch that is selective to the sub-fin so as to form a cavity between the cap layer and the remaining sub-fin thereby releasing the cap layer. In some such embodiments, a low-k oxide fill such as a porous silicon dioxide or even a regular-k oxide such as silicon oxide can be formed in the resulting cavity between the released cap layer and the sub-fin. As will be appreciated, releasing the cap layer from the sub-fin cures any defects that may have existed at an interface between the cap layer and the sub-fin. Moreover, in some such embodiments, the sub-fin leakage is eliminated or otherwise reduced. A high-k gate dielectric layer and gate electrode can thereafter be deposited to achieve a double-gate or tri-gate transistor structure. In other embodiments, the high-k gate dielectric and gate electrode materials can also be used to fill the cavity between the released cap layer and the sub -fin, so as to provide a gate-all-around transistor structure. In such cases, note that the channel and sub-fin are still electrically isolated but are more capacitively coupled (by virtue of a high-k fill between the sub- fin and channel, rather than a low-k or regular-k fill) which may or may not acceptable, depending on the desired performance parameters.

Numerous benefits will be apparent in light of this disclosure. For example, in some embodiments, the techniques reduce or completely eliminate source/drain leakage via sub-fin (or sub-channel). Further, in some embodiments, by growing a cap layer directly on the fin, and then releasing the cap layer, any lattice match based defects that may be present at the interface of the cap layer and the sub-fin are removed. In some embodiments, the techniques are beneficial due to the good etch selectivity between differing group IV materials. In some embodiments, for instance, etchants such as peroxide chemistry can be used to selectively remove group IV materials (such as Si) at a faster rate (e.g., at least 2 times faster) than the removal of another group IV material such as Ge or SiGe having a Ge concentration in the range of 20 to 99.9 atomic percent. In some embodiments, high mobility channel material is achieved and the quality of the released cap layer is improved.

Use of the techniques and structures provided herein may be detectable using tools such as scanning/transmission electron microscopy (SEM/TEM), composition mapping, x-ray crystallography or diffraction (XRD), secondary ion mass spectrometry (SIMS), time -of- flight SIMS (ToF-SIMS), atom probe imaging or tomography, local electrode atom probe (LEAP) techniques, 3D tomography, high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate a structure or device configured with at least one group IV semiconductor material channel body (such as a nanowire), and such at least one channel body may be located in the channel region of a transistor and isolated from the underlying but different group IV semiconductor sub-fin via an intervening insulator (e.g., Ge-based channel body isolated from an underlying Si sub-fin by a porous silicon dioxide or a silicon dioxide or hafnium oxide). Further note that, in some embodiments, the sub-fin may exhibit tapering or faceting proximate the release area, as seen in a cross-sectional profile taken perpendicular to the fin and through the channel region. Such tapering or faceting may result due to, in part, the selective etch chemistry employed to release the channel body by removal of sub-fin material. Further note that, in some embodiments, the upper sidewalls of the sub-fin may be covered with the intervening insulator material, as seen in a cross-sectional profile taken perpendicular to the fin and through the channel region. Numerous detectable structural configurations and variations will be apparent in light of this disclosure.

Methodology and Architecture

Figures 1A-2D illustrate example integrated circuit structures resulting from a method configured to form an integrated circuit having a group IV semiconductor material released channel body, in accordance with some embodiments of this disclosure. Note that Figures 1A- 1H are three-dimensional views and that Figures 2A-2D are cross-sectional views as taken along plane A of Figure 1H, in accordance with some embodiments. The techniques can be used to form p-type or n-type transistor devices, such as p-type MOSFET (p-MOS), n-type MOSFET (n- MOS), p-type tunnel FET (p-TFET), or n-type TFET (n-TFET), to name a few examples. Further, in some embodiments, the techniques may be used to benefit either or both of p-type and n-type transistors included in complementary MOS (CMOS) or complementary TFET (CTFET) devices, for example. Further yet, in some embodiments, the techniques may be used with devices of varying scales, such as transistor devices having critical dimensions in the micrometer range or in the nanometer range (e.g., transistors formed at the 32, 22, 14, 10, 7, or 5 nm process nodes, or beyond).

Figure 1 A illustrates an example structure including substrate 110 having two fins 120, 121 formed thereon, in accordance with an embodiment. The fins 120, 121 can be formed using any suitable technique, such as one or more patterning and etching processes, for example. In this example embodiment, fins 120 are native to the substrate 110, in that the fins 120 are formed on and from the substrate 110, with a trench 115 between fins. The fins 120, 101 may be formed by etching trenches 115 out of a bulk of substrate material 110 such as a bulk silicon substrate, for example. In other embodiments, the fins 120 are so-called replacement fins that are not native to the substrate 110, but instead are fins deposited onto the substrate 110 within relatively deep trenches previously occupied by placeholder fins native to the substrate, via an aspect ratio trapping process. Regardless of whether they are native to the substrate or not, the fins may be formed to have varying widths Fw and heights Fh. For example, the height to width ratio (h:w) of the fins is generally greater than 1, such as greater than 1.5, 2, or 3, or any other suitable minimum ratio. The length of the fins may of course also vary as well, but is typically longer than the widest width of the given fin. Note that while the fins are shown with relatively straight sides and a flat top, in reality the fins may have angled or tapered sidewalls such that the width Fw at the base of the fin is wider than the width Fw at the top of the fin. Likewise, the fin tops may actually be rounded or otherwise not perfectly flat. Numerous fin shapes and dimensions can be used in accordance with an embodiment of the present disclosure. Further note that although only two fins are shown in the example structure of Figure 1A for illustrative purposes, any number of fins may be formed, such as one, five, ten, hundreds, thousands, and so forth, depending on the end use or target application.

In some embodiments, substrate 110 may include: a bulk substrate including a group IV material or compound, such as silicon (Si), germanium (Ge), silicon carbide (SiC), or silicon germanium (SiGe); an X on insulator (XOI) structure where X is one of the aforementioned group IV materials and the insulator material is a native oxide material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned group IV materials. In a more general sense, any suitable substrate can be used, as will be appreciated.

Figure IB illustrates an example structure formed after shallow trench isolation (STI) 130 processing has been performed in trenches 115 of the structure of Figure 1A and structure has been planarized, in accordance with an embodiment. Any suitable deposition process may be used for the STI 130 deposition and the STI material may be selected based on the material of substrate 110 (e.g., to provide appropriate isolation and/or passivation), in some embodiments. For example, in the case of a Si substrate 1 10, STI material 110 may selected to be silicon dioxide (Si0 ₂ ) or silicon nitride (SiN), in accordance with an example embodiment of the present disclosure.

Figure 1C illustrates an example structure formed after a portion of the fins 120, 121 have been removed, leaving a sub-fin trench 131 over fin 120 and a sub-fin trench 132 over fin 121. The fins can be etched or otherwise removed to reveal the trenches 131, 132. For example, an etchant can be selected to remove a portion of the fin material (120, 121) without interacting with the STI material 130, to reveal the sub-fin trenches 131, 132. Note that the fins 120, 121 are now recessed to define the sub-fin trenches 131, 132. The depth of the recess can vary from one embodiment to the next, and largely depends on the desired effective gate length (not to be confused with the actually geometry of the semiconductor body that includes the channel). For instance, in a tri-gate channel configuration, the effective channel length includes the collective length of the channel body sides and top. Similarly, in a double-gate channel configuration, the effective channel length includes the collective length of the channel body sides only (and not the top). Similarly, in a gate-all-around channel configuration, the effective channel length includes the collective length of the channel body sides, top and bottom. To this end, the depth of the sub-fin trenches 131, 132 can be set as desired. In some cases, the depth is in the range of 2 nm to 60 nm or 20 nm to 60 nm, but in other embodiments may be in the range of 2 nm to 40 nm, or 5 nm to 35 nm, or 5 nm to 25 nm, or 5 nm to 20 nm, or 5 nm to 15 nm, or 5 nm to 10 nm, to name a few examples. As will be further appreciated, the width of the fins 120, 121 can similarly be set as desired, during the fin formation process.

Figure ID illustrates an example structure formed after a cap layer 150, 152 of a second group IV semiconductor material is grown, respectively, on the recessed fins 120, 121, according to an example embodiment of the present disclosure. Note the cap layer 150, 152 formed in the sub-fin trenches 131, 132 is relatively thin (e.g., 20 nm to 60 nm), compared to the overall original fin height, which may be in excess of 150 nm or 200 nm. In some example embodiments, the cap layers 150, 152 are nominally pure Germanium (Ge); however any appropriate group IV semiconductor material can be implemented in accordance with an example embodiment of the present disclosure. For example, the material of the cap layers 150, 152 can be SiGe having a Ge concentration in the range of 20 to 99 atomic percent, or Si:C having a carbon concentration in the range of 1 to 3 atomic percent. The cap layers 150, 152 can be grown in the trenches 131, 132 directly on the recessed fins 120, 121 by any technique in accordance with the present disclosure, for example any appropriate deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), to name a few examples. In some embodiments, the cap layer 150, 152

(channel body) material is epitaxial and therefore monocrystalline, but in other embodiments may be poly crystalline or amorphous, depending on the type of transistor being formed. In any such cases, the excess cap layer 150, 152 material that extends above the sub-fin trenches 131,

132 can be removed by, for example, a standard planarization process.

Figure IE illustrates an example structure formed after the cap layers of the structure of Figure ID has been planarized and the STI material 130 has been partially recessed, in accordance with an embodiment of the present disclosure. As will be appreciated, the cap layers 150, 152 have been planarized to the STI material so that the cap layers 150, 152 and the STI material 130 are co-planar. The STI material 130 is then recessed to a depth, such that at least a portion of the sub-fin is above the recessed plane of the STI material 130. Recessing the STI material 130 may be performed using any suitable technique, including wet and/or dry etches selective to the fin materials (i.e., the STI material 130 etches faster than the cap layer 150, 152 and sub-fin 120, 121 materials). In some other embodiments, a masking scheme is used to protect the cap layer 150, 152 and sub-fin 120, 121 materials while the STI material 130 is recessed. In this example embodiment, STI material 130 is recessed such that 1 nm to 20 nm of the sub-fins 120, 121 are exposed, in addition to the group IV cap layer 150, 152; however, in other embodiments, the STI material 130 may be recessed to a different depth. In a more general sense, the STI material 130 should be recessed enough to allow for a subsequent selective etch chemistry to reach and remove at least a top portion of the sub-fins 120, 121, so as to allow for release of the cap layer 150, 152. The desired gap size (specifically, gap height) to be formed in the release area can be used to further inform how deep the STI material 130 should be recessed, as will be appreciated in light of this disclosure.

Figure IF illustrates an example structure formed after a dummy gate stack has been formed on the structure of Figure IE, in accordance with an embodiment. In this example embodiment, gate dielectric 133 and gate electrode 134 are dummy materials (e.g., silicon dioxide for the gate dielectric 133 and poly-silicon for the gate electrode 134) used in a gate last process flow. As will be discussed with reference to Figure 1G, the dummy materials will be subsequently removed later in the process to allow for processing in the channel region of the structure to form one or more nanowires. Formation of the dummy gate stack may include depositing the dummy gate dielectric material 133, dummy gate electrode material 134, patterning the dummy gate stack (e.g., mask gate stack and etch excess dummy gate materials away), depositing gate spacer material 136 as well as a gate hardmask 138, and performing a spacer etch to form the structure shown in Figure IF, for example. The example structure in this embodiment includes hardmask 138 over the gate stack, which may be included to protect the dummy gate stack during subsequent processing, for example.

Figure 1G illustrates an example structure formed after a layer of insulator fill material 155 has been formed on the structure of Figure IF, in accordance with an embodiment. Note that the insulator material 155 is illustrated as transparent to allow for underlying features to be viewed. In some embodiments, the insulator material 155 may include a dielectric material, such as silicon dioxide, for example. In some embodiments, following deposition of the insulator material 155, a polish and/or planarization process may be performed to produce the example structure of Figure 1G.

Figure 1H illustrates an example structure formed after the dummy gate stack (including dummy gate dielectric 133 and dummy gate electrode 134) of Figure 1G have been removed to re-expose the channel region 160, in accordance with an embodiment. In some embodiments, removing the dummy gate stack may include first removing hardmask layer 138 and then removing the dummy gate stack (layers 134 and 133, in this example case) using any suitable technique, such as selective wet and/or dry etches, and any necessary masking to the extent that the desire etch selectivity cannot be achieved, for example. The A plane in Figure 1H is used to indicate the plane of viewing for the cross-sectional views of Figures 2A-2D, as will be described in more detail below.

It will be appreciated that the order of Figures 1A-1H is only one example sequential process for forming the structure of Figure 1H, and the process can be varied in accordance with the example embodiments disclosed herein.

Figure 2A illustrates a cross-sectional view taken along plane A of Figure 1H, in accordance with an embodiment. Figure 2 A is provided to illustrate the channel region 160 of the structure of Figure 1H. As shown, at least some of the sub-fins 120, 121 extend above the top of the STI 130 plane, in this example embodiment. The cap (channel) layer 150, 152 also extends above the top plane of the STI material 130 and into the channel region 160, in accordance with an embodiment. As can be further seen, the cap layer 150, 152 is a Ge- containing layer, having a Ge concentration that may range, for example, from about 20 to 100 atomic percent (e.g., Sii _-x Ge _x , where 0.2 < x < 1.0). Some such example embodiments may further include carbon up to 3%, or up to 20% in still other example embodiments. Other embodiments may employ other group IV materials for cap layer 150, 152, and the present disclosure is not intended to be limited to a Ge-containing cap layer 150, 152, as will be appreciated. Figure 2B illustrates an example structure resulting after a cavity 153, 154 is formed between the channel layers 150, 152 and their respective sub-fins 120, 121. The sub-fins 120, 121 can be selectively etched according to an appropriate etching technique to form the cavities 153, 154. For example, etchants are available (e.g., etchants including peroxide chemistry) that can selectively remove Si (e.g., sub-fin material 120, 121) at a faster rate than Ge-containing material (e.g., the channel layer material 150, 152), for example two times faster in some embodiments, depending on the concentration of Ge, which may range for example, from 20 to 100 atomic percent. Thus, Si of the underlying sub-fin 120, 121 can be selectively removed without interacting with the Ge-containing channel layer 150, 152. As shown, after the selective etch is carried out, the structure includes recessed sub-fins 140, 142 that are now fully below the top of the STI 130 plane, in this example embodiment. The cavities 153, 154 can also be at least partially formed by oxidizing a portion of the sub-fins 120, 121 and/or the channel bodies 150, 152, thereby providing an electrical barrier between the sub-fins 140, 142 and the channel bodies 150, 152. By forming the cavities 153, 154 between the sub-fins 140, 142 and the channel layers 150, 152, a released nanowire 150, 152 of group IV semiconductor material is provided in the channel region 160. Releasing the channel layer 150, 152 cures any defects that may exist at the interface between the channel layers 150, 152 and the sub-fins 120, 121, and thus a higher quality of material is provided, in addition to improved sub-fin control, in accordance with an example embodiment of the present disclosure.

Figure 2C illustrates an example structure formed after an intervening insulation layer 210,

212 is filled in at least a portion of the cavities (153, 154 of the structure of Figure 2B), in accordance with an example embodiment. In some embodiments, the intervening insulation layer can be an oxide fill, or can include an oxide fill in part, that is deposited or otherwise formed between the channel body 150, 152 and the sub-fin region 140, 142. The intervening insulation layer can, for example, include an insulator material, such as silicon dioxide or silicon nitride, or a porous version of such insulator materials to provide a low-k intervening insulation layer 210, 212. The intervening insulation layer 210, 212 can be formed by growing or otherwise depositing an appropriate oxide or nitride material under the channel bodies 150, 152 to at least partially fill in the remaining cavity while leaving the cap layer suspended in the channel region 160, according to some embodiments. In some embodiments, the intervening insulation layer 210, 212 completely fills the cavity so as to be in contact with a bottom of the channel bodies 150, 152. In other embodiments, the intervening insulation layer 210, 212 covers the top of the sub-fins 140, 142 and some of the lower cavity but is not contact with the bottom of the channel bodies 150, 152 thereby leaving room for at least one of the gate dielectric and gate electrode materials to fill the remaining portion of the cavity and be in contact with the bottom of the channel bodies 150, 152.

Figure 2D illustrates an example structure formed after gate processing has been performed on the structure of Figure 2C, in accordance with an embodiment of the present disclosure. After the group IV semiconductor material channel bodies 150, 152 have been fabricated and released, as shown in Figure 2C, gate stack processing can follow, such as a replacement metal gate (RMG) process flow, for example. In this example embodiment, the gate stack processing includes depositing a thin (e.g., 1-20 nm in thickness) gate dielectric layer 172 around each channel body 150, 152. As can be seen in this example embodiment, the gate dielectric material 172 is conformally deposited (e.g., via ALD or other suitable deposition process), such that it has a substantially similar thickness on all surfaces upon which it grows. Further, as can be seen in the example structure of Figure 2D, the thin gate dielectric material 172 also conformally grows on the base portion of the structure, such as on and over STI material 130 and the intervening insulation layers 210, 212 (if present). In some embodiments, the gate dielectric material 172 may include silicon dioxide and/or a high-k dielectric material, depending on the end use or target application. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 172 to improve its quality when a high-k material is used, for example. In some embodiments, gate dielectric layer 172 may include a multi-layer structure of two or more material layers (e.g., a first layer of silicon dioxide on the channel body, and a second layer of hafnium oxide on the first layer of silicon dioxide). In some embodiments, gate dielectric layer 172 may include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of the gate dielectric layer 172.

In this example embodiment of Figure 2D, the gate processing further includes depositing gate electrode material 174 (e.g., 10-100 nm in thickness) on the thin gate dielectric layer 172. As can be seen in this example embodiment, the gate electrode material 174 is conformally deposited (e.g., via ALD), such that it has a substantially similar thickness over the gate dielectric material 172 and tracks with the topography of gate dielectric material 172 upon which the gate electrode material grows. Further, as shown in the example structure of Figure 2D, gate electrode material 174 is also conformally grown over the thin gate dielectric layer 172 on the base portion of the structure, such as over STI material 130 and over the intervening insulation layers 210, 212 (if present). In addition, in this example, the gate processing included depositing gate contact material 176 on gate electrode material layer 174. In some embodiments, the material of gate electrode 174 and gate contact 176 may include any suitable material, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), niobium (Nb), titanium nitride (TiN), and/or tantalum nitride (TaN), to name some suitable materials. For example, in some embodiments, the gate electrode material 174 may be TiN and/or TaN and the gate contact material 176 may be W, Ta, or Nb to provide a few examples. Note that in some embodiments, one of the gate electrode 174 or gate contact 176 need not be present in the gate stack, such that only one other gate material layer is present and in contact with the gate dielectric layer 172. Further note that in some embodiments, the gate stack may include additional material layers, such as one or more material layers between layers 172 and 174, and/or between layers 174 and 176. In some such embodiments, work-function material layers may be included to, for example, increase the interface quality between layers 172, 174 and/or 176 and/or to improve the electrical properties between layers 172, 174 and/or 176. Figure 2D illustrates the gate dielectric 172 and the gate electrode material 174 on the channel bodies 150, 152, in accordance with an embodiment of the present disclosure.

The example structure of Figure 2D is one example where the gate dielectric material 172 and gate electrode material 174 are deposited on all sides of the channel bodies 150, 152, thus resulting in a gate-all-around (GAA) structure as shown. In some embodiments, the space between the channel bodies 150, 152 and the intervening insulator layers 210, 212 (if present) can be filled in with additional insulator material to completely fill that space up to and in contact with the bottom of the channel bodies 150, 152. In such cases, the remaining three sides of the channel bodies 150, 152 (sides and top) can be surrounded by the gate dielectric material and gate electrode material, as will be appreciated in light of the present disclosure. In still other cases, only the sides of the channel bodies 150, 152 (not the top) can have the gate dielectric material and gate electrode material deposited thereon. In still other cases, no intervening insulator layers 210, 212 are provided, and at least three sides of the channel bodies 150, 152 (sides and bottom, or sides, top, and bottom) have the gate dielectric material and gate electrode material deposited thereon, wherein at least one of the gate dielectric material and gate electrode material are further deposited to substantially (e.g., 90% or more filled) or completely fill the gap between the channel bodies 150, 152 and the underlying sub-fins 140, 142.

The example structure of Figure 2D provides a high mobility logic device architecture with sub-fin and source/drain junction control. Direct growth of germanium-rich semiconductor on silicon (or other appropriate group IV semiconductor material systems) via a trench-based deposition process provides high mobility and low-band gap material such as germanium to be with sub-fin control. Further, a lattice transition buffer system is not required on the silicon fin or in the source/drain regions, in accordance with the example embodiment. As will be further appreciated in light of this disclosure, in the source/drain regions, the quality of the germanium may be increased and the sub-fin leakage is further controlled by providing the example structure of Figure 2D (or the various alternative embodiments provided herein).

It will be appreciated that the order of Figures 2A-2D is only one example sequential process for forming the released group IV semiconductor material in the channel region, and the process can be varied in accordance with the example embodiments disclosed herein.

Figure 3 illustrates an integrated circuit including gate-all-around transistor configurations including group IV material nanowires, in accordance with some embodiments. As can be seen in the example structure of Figure 3, the channel region 160 of Figure 1H has been processed as described with reference to Figures 2A-2D, in this example embodiment. In addition, hardmask 178 has been formed on the gate stack, in this example case, to protect the gate stack during other processing, such as during the source/drain processing that occurs post-gate-formation, to form source/drain regions 161/162 and 163/164. As shown in Figure 3, source/drain regions 161/162 are adjacent to the released channel region 150 including one nanowire/nanoribbon (e.g., as shown in Figure 2D) and source/drain regions 163/164 are adjacent to the released channel region 152 including one nanowire/nanoribbon (e.g., as shown in Figure 2D). Note the source/drain regions may be native to the original fin, or epitaxially provided after fin material in the source/drain areas is etched away or otherwise removed. Further note that the shape of the source/drain regions may be wider and/or taller than the original fin geometry, depending on the source/drain forming processes used.

Any number of additional processes may be performed to complete the formation of one or more transistor devices, such as forming source/drain contacts and performing back-end-of line interconnections, for example. In some embodiments, the source/drain processing may include patterning and filling the source/drain regions with appropriately doped epitaxial materials. In some embodiments, the source/drain epitaxial regions may be grown after performing an etch- under-cut (EUC) process. In some such embodiments, the source/drain regions may extend under spacers 136 and/or under the gate stack, and such extended portions may be referred to as source/drain tips or extensions, for example. In some embodiments, the source/drain regions may be formed completely in the substrate, may include a portion of the substrate (e.g., including doping or otherwise altered), may be formed over the substrate, or any combination thereof or have any other suitable configuration. In some embodiments, source/drain regions 161/162 and

163/164 may include any suitable materials and, optionally, any suitable dopants, depending on the end use or target application. For example, in some embodiments, the source/drain regions may include one or more group IV materials, such as Si, or Ge, or SiC, or SiGe, to name a few example materials. Further, in some such embodiments, the source/drain region material may include n-type dopants and/or p-type dopants, depending on the end use or target application. For example, in the case of an n-MOS device, the source/drain regions may both be n-type doped with phosphorous. In another example case of a tunnel FET (TFET) device, the source and drain regions may be oppositely typed doped (e.g., one n-type doped and the other p-type doped). Further yet, in some embodiments, the source/drain regions may include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least one of the regions. Further still, in some embodiments, one or more of the layers included in the source/drain regions may be a multi-layer structure including at least two material layers, depending on the end use or target application. Once the source/drain regions are formed, a deposition of insulator material can be provided over the structure and planarized. A standard or custom source/drain contact formation process flow may proceed from there. In one example case, after forming the contact trenches in the insulator material and over the source/drain regions 161/162 and 163/164, a contact structure is provided therein, which in some example embodiments may include a resistance reducing metal and a contact plug metal, or just a contact plug. Example contact resistance reducing metals include silver, nickel, aluminum, titanium, gold, gold -germanium, nickel-platinum or nickel-aluminum, and/or other such resistance reducing metals or alloys. The contact plug metal may include, for instance, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy can be used, using conventional deposition processes. Other embodiments may further include additional layers, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.

In the example structure of Figure 3, the left transistor (including one nanowire channel body 150) may be a p-MOS device, in some embodiments, and source/drain regions 161/162 may both be doped with a p-type dopant (e.g., boron). In another example embodiment, the right transistor (including one nanowire channel body 152) may be an n-MOS device, and source/drain regions 163/164 may both be doped with an n-type dopant (e.g., phosphorus). Further, in embodiments where one of the transistors is a p-MOS device and the other is an n- MOS device, they may both be included in a CMOS device, for example. Note that in such a CMOS device, the transistors may be located farther apart than what is shown in Figure 3 and/or include additional isolation material between the two transistors, for example. Further note that the transistors in such a CMOS device configuration may not share the same gate stack, for example. In some embodiments, any suitable source/drain material and optional doping schemes may be used, depending on the end use or target application. For example, in TFET configurations, the source/drain regions may be oppositely type doped (e.g., source is p-type doped and drain is n-type doped, or vice versa), with the channel region being minimally doped or undoped (or intrinsic/i-type). The two different configurations including different channel geometries are both provided in the example structure of Figure 3 for ease of illustration. In some embodiments, a single integrated circuit may include transistors having all the same configuration (and optionally have varying n or p-type structures) or two or more different configurations (and optionally have varying n or p-type structures).

As will be appreciated in light of the present disclosure, in some embodiments, a transistor (or other integrated circuit layers, structures, features, or devices) formed using the techniques described herein may be formed at least one of above and on the substrate 100, as various portions of the transistor (or other integrated circuit layers, structures, features, or devices) may be formed on the substrate (e.g., the source/drain regions 161/162 and 163/164), various portions may be formed above the substrate (e.g., channel bodies 150 and 152), and various portions may be considered to be both on and above the substrate, for example. Although the example embodiments include the group IV semiconductor material extending along the fin in the source and drain regions, in some embodiments, the group IV semiconductor material may extend only in the channel region and be replaced with other appropriate semiconductor materials in the source and drain region.

Figure 4 illustrates a methodology for forming an integrated circuit, in accordance with an example embodiment of the present disclosure. At 410, one or more fins are formed on a substrate, in accordance with an example embodiment of the present disclosure. Refer, for example, to Figure 1A showing two fins on a substrate, in accordance with an example embodiment of the present disclosure. In some embodiments, the fins can be formed using any suitable technique, such as one or more patterning and etching processes, for example where the fins are etched out of a bulk substrate. In some cases, the process of forming a fin may be referred to as shallow trench recess, for example. In this example embodiment, fins are formed from the substrate, but in other embodiments, fins may be formed on the substrate, using any suitable deposition/growth and/or patterning technique. At 412, shallow trench isolation (STI) material is formed on either side of the fin in accordance with an example embodiment of the present disclosure. Refer, for example, to the structure shown in Figure IB for an example structure having the STI material deposited on either side of the fins. Any suitable deposition and planarization processes may be used for provisioning the STI deposition, and the STI material may be selected, for example, based on the material of substrate (e.g., to provide appropriate isolation and/or passivation), in some embodiments.

At 414, a portion of each fin is recessed to a desired depth to define sub-fin trenches, in accordance with an example embodiment of the present disclosure. The depth of the trenches may be, for example, in the range of 2 nm to 60 nm, or 20 nm to 60 nm, in some embodiments. Refer, for example, to Figure 1C showing a structure with the sub -fin trenches that remain after a first recessing of the fins. The recessing can be performed by selectively etching a portion of each of the fins, as will be appreciated in light of the present disclosure. Any suitable etch schemes can be used.

At 416, a cap layer of group IV semiconductor material is grown in the sub-fin trench, in accordance with an example embodiment of the present disclosure. An example resulting structure of the cap layer directly grown on the sub-fin is shown in Figure 1C. In this example structure, the cap layer is comprised of germanium (Ge), however any appropriate group IV semiconductor material can be implemented, such as SiGe with a Ge concentration in the range of 20 to 99 atomic percent. The cap layer can be grown directly on the sub-fin by any technique in accordance with the disclosure, for example any appropriate deposition technique. Excess cap material can be removed by a standard planarization and cleaning process.

At 418, a portion of the STI material between the fins is removed, for example by selective etching, or a mask patterning and etch scheme. Refer, for example, to Figure IE showing an example structure with a portion of the STI material removed. Note that the top plane of the STI material is now below the interface between the cap layer 150, 152 and the sub-fins 120, 121.

At 420, a dummy gate electrode and dummy gate are formed, in accordance with an example embodiment of the present disclosure. Refer, for example, to Figure IF showing an example structure with a dummy gate electrode and dummy gate formed therein. As will be appreciated, the gate stack can be formed by, for example, blanket depositing the gate dielectric and gate electrode materials, and then masking and etching to form the dummy gate stack. Gate spacers can then be formed on the side of the gate stack, as normally done. As will be further appreciated in light of the present disclosure, the dummy gate electrode and dummy gate are later removed in a gate last process, to form the transistor in accordance with an embodiment of the present disclosure.

At 422, additional insulation material is deposited (as shown in Figure 1G) and then the dummy gate electrode and dummy gate are removed (as shown in Figure 1H), in accordance with an embodiment of the present disclosure. Figure 1H shows an example structure after the insulation material has been deposited, and after the dummy gate electrode and dummy gate have been removed, in accordance with an embodiment of the present disclosure. Standard processing can be used at 422.

At 424, at least a portion of the sub -fin and/or cap material that is adjacent to the interface with the sub-fin/cap layer is etched out to define a cavity and release the cap layer (channel body) from the sub-fin, in accordance with an example embodiment. Figure 2B illustrates an example structure formed after a cavity is formed between the group IV channel layer and the underlying group IV fin, in accordance with an example embodiment of the present disclosure. The cavity can be formed, for example, using a selective wet etch or vapor phase etch, to remove a portion of the sub-fin, in accordance with an embodiment of the present disclosure. The portion of the sub-fin that is etched out is adjacent to the channel layer and thereby provides a released channel layer that is above and electrically decoupled from the sub- fin of the first group IV semiconductor material. The cavity can also be formed by oxidizing a portion of the sub-fin and/or cap layer, or by any appropriate technique as will be appreciated in light of this disclosure.

At 426, the cavity under the released channel layer is filled in with an intervening layer of insulation, such as an oxide or nitride, in some example embodiments. In some embodiments, providing the intervening layer of insulation can comprise converting at least a portion of the semiconductor material of the sub-fin and/or channel bodies into an oxide, as previously explained (which can be done simultaneously with 424, according to some embodiments). The first group IV semiconductor material of the sub-fin can include Si or another group IV semiconductor material, in accordance with an embodiment of the present disclosure. The second group IV semiconductor material of the channel layer can include Ge or SiGe, for example having a Ge concentration in the range of 20 to 99 atomic percent in some embodiments. Refer to Figure 2C for an example structure showing the intervening insulation layer (210, 212) under the channel bodies (150, 152). As previously explained, the intervening insulation layer provisioned at 426 may include a high-k dielectric such as the gate dielectric provisioned at 428. In other embodiments, the intervening insulation layer at 426 is a low-k dielectric, such as porous silicon dioxide, carbon-doped silicon dioxide, porous carbon-doped silicon dioxide, or other suitable low-k dielectric. In still other embodiments, the intervening insulation layer at 426 is a regular dielectric, such as silicon dioxide or silicon nitride.

Thereafter, at 428, gate processing occurs, which includes depositing a gate dielectric material, and at 430, the gate electrode is then added, in accordance with an example embodiment. Refer, for example, to Figure 2D showing an example structure after the gate dielectric layer and gate electrode have been added. It will be appreciated in light of the present disclosure that Figure 4 shows one example process for forming the structure of Figure 2D, however variations may be implemented, including additional or fewer processing techniques, or a combination of techniques into a single technique, to achieve the structure shown in Figure 2D.

Figures 5A-E each illustrates an example cross-sectional view of an integrated circuit structure configured with a transistor including a group IV semiconductor material released channel body, in accordance with an embodiment of the present disclosure. The cross-section is taken perpendicular to the fin and through the channel region. As will be appreciated, Figures 5A-E are drawn to more realistically depict real world semiconductor structures, but in no way are intended to limit the present disclosure to the various example geometries and shapes shown. As can be seen, each of the embodiments depicted generally includes gap distance or height (generally designated as GH) between the underlying sub-fin 520 and the channel body 510. In addition, some of the embodiments depicted (Figures 5 A, 5 A, 5B', 5C, and 5D') show the sub- fin 520 protruding from STI a certain distance or height (generally designated as P _H ), such that the intervening insulator material covers both the top and sidewalls of the protruding portion. Numerous other embodiments and variations, including different shapes and geometries, will be appreciated in light of this disclosure.

Figure 5A is an example cross-sectional view of an integrated circuit structure including a group IV semiconductor material released transistor channel, in accordance with an embodiment of the present disclosure. The channel body 510 is shown released above the underlying sub-fin 520 as a result of a selective etch that generally removes sub-fin 520 material but not the channel body 510 material, in accordance with an example embodiment. The channel body 510 has a conformal gate dielectric material 512 and gate electrode material 514 deposited on all sides thereof, thereby forming a GAA structure, in accordance with an example embodiment. Double- gate and tri-gate configurations can also be used, as previously explained. The sub-fin 520 likewise has a conformal gate dielectric material 512 deposited thereon, to electrically isolate the sub-fin 520 from the channel body 510. In addition, the gate electrode 514 material fills the remainder of the release gap between the sub-fin 520 from the channel body 510 formed during the release process. As will be appreciated, the STI is the STI that was recessed to expose the interface between the channel body 510 and the sub-fin 520, prior to the release etch. As can be further seen, the gate dielectric material 512 also conformally coats the STI exposed in the gate trench 160 (Figure 1H), and the gate electrode 514 is over that dielectric material. As will be further appreciated, the fill insulation is added as needed to completely fill the remainder of exposed gate trench 160 and for planarizing the structure, after the gate dielectric and electrode materials are provisioned. This additional fill insulation can be, for example, the same as the STI material provided in earlier processing of the fins, and in some embodiments is silicon dioxide or silicon nitride. Further note that, in this example embodiment, the selective etch process to release the channel body 510 from the sub-fin 520 causes a tapering of the upper portion of the sub-fin 520 that extends or otherwise protrudes above the STI by a distance or height of P¾ such that upper sidewalls of the sub-fin are angled and the width at the base of the sub-fin 520 (width just above or co-planer with the STI) is wider than the width near the top of the sub-fin 520. The degree of tapering can vary from one embodiment to the next, and may be less severe (where the width near the top is more than one-half of the base width) or more severe (where the width near the top is less than one-half of the base width), as will be appreciated. Note that this tapering is in addition to any natural fin tapering that may result during the formation process of the original fin. As can be further seen, the top of the sub-fin comes to a relatively severe point in this example embodiment, but in other cases the top may be flat or rounded, for instance, such as shown in the example embodiment depicted in Figure 5A. The thickness of gate dielectric 512 between the sub-fin 520 and the channel body 510 can vary from one embodiment to the next, but some example cases is in the range of about 4 nm to 25 nm. A similar thickness range applies to the gate electrode 514, although the gate electrode 514 is typically much thicker than the gate dielectric 512 (e.g., 20 nm to 75 nm). The unfilled gap (GH) between the sub-fin 520 and the channel body 510 (resulting from the release etch process) may be, for example, in the range of 2 nm to 50 nm. Likewise, the distance P _H can also vary from embodiment to the next, but in some cases is in the range of 2 nm to 50 nm, such 5-50 nm or 10-50 nm or 20-50 nm or 10-45 nm or 15-40 nm or 15-30 nm.

Figure 5B is an example cross-sectional view of an integrated circuit structure including a group IV semiconductor material released transistor channel, in accordance with another embodiment of the present disclosure. Like the example case in Figure 5 A and 5 A, the channel body 510 is shown released above the underlying sub-fin 520 as a result of a selective etch that generally removes sub-fin 520 material but not the channel body 510 material, in accordance with an example embodiment. In this example case, however, the sub -fin 520 does not taper as much due to the selective release etch. In addition, an intervening insulator material 523 (e.g., silicon dioxide, silicon nitride, or other suitable insulator material) is deposited to basically fill the gap that results from the release process. To this end, note that the insulator material 523 covers the bottom of the channel body 510 in addition to the top of the sub-fin 520, as shown in Figure 5B, where the upper surface of sub-fin 520 is substantially flush with the upper surface of the STL In the alternative embodiment depicted in Figure 5B', the sub-fin 520 extends above the upper surface of the STI by a distance P¾ such that in addition to covering the bottom of the channel body 510 and top of the sub-fin 520, the insulator material 523 further covers the upper sidewalls of the sub-fin 520 that are not covered by the STI. The remaining sides and top of the channel body 510 have a gate dielectric material 512 and gate electrode material 514 deposited thereon, thereby forming a tri-gate structure, in accordance with an example embodiment. A double-gate configuration can also be provided, for example, by covering the top of the channel body 510 with insulator 523 as well, such that the gate dielectric material 512 and gate electrode material 514 are deposited on only the two sides of the channel body 510. As previously explained, the STI is the STI that was recessed to expose the interface between the channel body 510 and the sub-fin 520, prior to the release etch. In addition, the insulator material 523 also conformally coats the STI exposed in the gate trench 160 (Figure 1H), and the gate dielectric 512 and gate electrode 514 are over that insulator material, as shown. Also, fill insulation is added as needed to completely fill the remainder of the exposed gate trench 160 and for planarizing the structure, after the gate dielectric and electrode materials are provisioned. The thickness of the intervening insulation material 523 between the sub-fin 520 and the channel body 510 can vary from one embodiment to the next, but some example cases is in the range of about 1 nm to 50 nm (e.g., 5 to 25 nm, or 5 to 10 nm). As will be appreciated, therefore, the unfilled gap (GH) between the sub-fin 520 and the channel body 510 (resulting from the release etch process) may be similarly in the range of 1 nm to 50 nm. The previous discussion with respect to the distance P _H is equally applicable here, and in a more general sense, the sub-fin may protrude from the STI any desired distance.

Figure 5C is an example cross-sectional view of an integrated circuit structure including a group IV semiconductor material released transistor channel, in accordance with another embodiment of the present disclosure. This example case is similar to the example shown in Figure 5B, except that the thickness of the intervening insulator material 523 is less than the distance G _H between the upper surface of the sub -fin and the lower surface of the channel body 510. As such, after the insulator material 523 is provided, the gate dielectric 512 deposition (e.g., via ALD) can actually fill the remaining gap between the channel body 510 and the sub-fin 520 and cover the lower surface of the channel body 510, as well as the sides and top surface of the channel body 510. In the alternative embodiment depicted in Figure 5C, the sub-fin 520 extends above the upper surface of the STI by a distance P _¾ such that in addition to covering the bottom of the channel body 510 and the top of the sub-fin 520, the insulator material 523 further covers the upper sidewalls of the sub-fin 520 that are not covered by the STI. The remaining sides and top of the channel body 510 have the gate dielectric material 512 and gate electrode material 514 deposited thereon, thereby forming a tri-gate structure, in accordance with an example embodiment. A double-gate configuration can also be provided, for example, by covering the top of the channel body 510 with insulator 523 as well, such that the gate dielectric material 512 and gate electrode material 514 are deposited on only the two sides of the channel body 510. Thus, the embodiments shown in Figures 5C and 5C are similar to those shown in Figures 5B and 5B', except that the distance G _H is shared by a first thickness of insulator material 523 and a second thickness of gate dielectric 512 material. Although these thicknesses can vary from one embodiment to the next, in some example cases each of the first and second thicknesses is in the range of 4 nm to 35 (e.g., 15 nm to 35 nm of insulator material 523, and 2 nm to 10 nm of gate dielectric 512). Other relevant discussion with respect to Figures 5B and 5B' is equally applicable here.

Figure 5D is an example cross-sectional view of an integrated circuit structure including a group IV semiconductor material released transistor channel, in accordance with another embodiment of the present disclosure. This example case is similar to the example shown in Figure 5C, except that the distance G _H is shared by a first thickness of insulator material 523, a second thickness of gate dielectric 512 material, and a third thickness of gate electrode 514 material. As such, after the insulator material 523 is provisioned, the gate dielectric 512 deposition (e.g., via ALD) conformally coat the underlying insulator material 523, as well as the sides, bottom, and top surface of the channel body 510. Note that a portion of the gap between the channel body 510 and the sub-fin 520 still remains after the gate dielectric 512 is deposited. The gate electrode 514 material is then provided over the gate dielectric 512, so as to fill the remaining gap between the channel body 510 and the sub-fin 520, as well as to cover the sides and top of the channel body 510. In the alternative embodiment depicted in Figure 5D', the sub- fin 520 extends above the upper surface of the STI by a distance P _¾ such that in addition to covering the top of the sub-fin 520, the insulator material 523 further covers the upper sidewalls of the sub-fin 520 that are not covered by the STI. So, in this example embodiment, the channel body 510 is completely surrounded by gate dielectric material 512 and gate electrode material 514, thereby forming a gate-all-around structure. Although the various layer thicknesses making up the overall thickness (distance G _H ) between the channel body 510 and the sub-fin 520 can vary from one embodiment to the next, in some example cases the thicknesses are as follows: 5 nm to 25 nm of insulator material 523; 2 nm to 10 nm of gate dielectric 512 material; and 5 nm to 25 nm of gate electrode 514 material. Other previous relevant discussion is equally applicable here.

Figure 5E is an example cross-sectional view of an integrated circuit structure including a group IV semiconductor material released transistor channel, in accordance with another embodiment of the present disclosure. The channel body 510 is shown released above the underlying sub-fin 520 as a result of an oxidation process that has converted at least one of a lower portion of the channel body 510 and an upper portion of the sub-fin 520 to an insulator 524 material, in accordance with an example embodiment. As will be appreciated, the oxidation may be more aggressive in the channel body 510 than the sub-fin 520, or vice-versa. For instance, in some example embodiments, and assuming the channel body is a Ge-based semiconductor (e.g., Sii _-x Ge _x , where 0.2 < x < 1.0) and the sub-fin 520 is silicon, an oxidation process will convert the Ge-rich channel body 510 at a relatively faster rate than the silicon sub- fin 520. In particular, the selective oxidation process to release the channel body 510 from the sub-fin 520 causes a thinning of the channel body 510 material (e.g., due to conversion of germanium to germanium dioxide, or SiGe to SiGe-oxide). In some cases, some of the Si sub- fin 520 will convert to silicon dioxide. The minimum thickness of the oxide 524 between the sub-fin 520 and the channel body 510 can vary from one embodiment to the next, but some example cases is in the range of about 2 nm to 50 nm. In addition, note that the oxidation may cause a horseshoe pattern in the group IV semiconductor material that oxidizes faster. For instance, in the example embodiment shown, the oxidation has progressed both across the channel body 510 (side to side) and also up the side portions of the channel body 510 (toward the top). The width of the remaining channel body 510 between the oxidized side portions is ultimately consumed as the oxidation process dwells. As such, depending on how long the oxidation process continues, a remaining channel body 510 as measured at line W-W may remain between oxidation fingers extending into the body. In other embodiments, the group IV semiconductor material of sub-fin 520 may oxidize faster than the group IV semiconductor material of the channel body 510, which may produce a similar horseshoe shape, but upside down.

Note that reference herein to structural features such as a top and a bottom may generally refer to top or bottom surfaces that undulate within a tolerance (e.g., such as a surface that has a distance between its highest and lowest points of 2 nm or less, but is not perfectly flat). To this end, such reference to top or bottom of a given structure is not intended to be limited to a true top or bottom that is some specific point along a top or bottom surface of the structure, but instead refers to an overall or macro top or bottom surface, as will be appreciated. In addition, a sidewall as used herein generally refers to a downward trending surface that is lower than or otherwise a suitable distance from a lowest point of a top surface. Similarly, a sidewall as used herein may also generally refer to an upward trending surface that is higher than or otherwise a suitable distance from a highest point of a bottom surface. So, for instance, if the top surface of a given structure is a point, then the sidewall of that structure is the downward trending surface extending downward from that point, or more specifically, the downward trending surface that is 1 nm or more lower than that point, for example. Likewise, if the top surface of a given structure is a flat but undulating surface, then the sidewall of that structure is the downward trending surface extending downward from that undulating surface, or more specifically, the downward trending surface that is 1 nm or more lower than the lowest point of that undulating surface, for example.

Further note that reference herein to structural features such as width and height may generally refer to dimensions that vary in value, depending on where they are measured on the given structure. For instance, if a top surface of a structure undulates between high and low points rather than being perfectly flat, the height of that structure may vary depending on where it is measure relative. Similarly, if a fin-like structure extending upward is tapered such that the width decreases from the base to the top of the fin. In any such cases, a width or height can be measured, for example, as an average value of multiple width or height measurements for a given surface, or a median value of multiple width or height measurements for a given surface, or some other statistically relevant representation of the height or width or other dimension of interest. In some cases, a width of a structure can be measured as an intermediate or midway point between the macro top and bottom surfaces of that structure. Likewise, a height of a structure can be measured as an intermediate or midway point between the sidewalls of that structure.

Any number of additional processes may be performed to complete the formation of one or more transistor devices, such as forming source/drain contacts and performing back-end-of line interconnections (e.g., metal layers Ml through M9), for example. A standard or custom source/drain contact formation process flow may be used. Some embodiments may include additional layers, such as resistance reducing layers, adhesion layers (e.g., titanium nitride), and/or liner or barrier layers (e.g., tantalum nitride), if so desired.

Example System

Figure 6 illustrates a computing system 1000 implemented with one or more integrated circuit structures or devices configured in accordance with some embodiments. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices configured with a released group IV channel as variously provided herein, in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices configured with a released group IV channel, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices configured with a released group IV channel as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices configured with a released group IV channel, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit comprising: a channel body including a first group IV semiconductor material; a sub-fin below the channel body and extending upward from an underlying substrate, the sub-fin including a second group IV semiconductor material different from the first group IV semiconductor material; an intervening layer of insulator material between the channel body and the sub-fin, the intervening layer in contact with at least the top of the sub-fin; and trench isolation in contact with lower sidewalls of the sub-fin.

Example 2 includes the subject matter of Example 1, wherein the intervening layer is also in contact with upper sidewalls of the sub-fin that are not in contact with the trench isolation.

Example 3 includes the subject matter of Example 1 or 2, wherein the first group IV semiconductor comprises germanium and the second group IV semiconductor material is silicon (Si) and the intervening layer is in direct contact with the Si.

Example 4 includes the subject matter of any of the preceding Examples, wherein the intervening layer includes an oxide or nitride material.

Example 5 includes the subject matter of any of the preceding Examples, and further includes a gate dielectric material on multiple surfaces of the channel body and on the intervening layer, the gate dielectric material being the same as the insulator material of the intervening layer.

Example 6 includes the subject matter of Example 5, wherein the gate dielectric material surrounds the channel body, and the integrated circuit further comprises a gate electrode material on the gate dielectric material and surrounding the channel body, so as to provide a gate-all- around structure, the gate dielectric and gate electrode materials collectively filling a gap between the channel body and the sub-fin.

Example 7 includes the subject matter of Example 5 or 6, wherein the insulator material of the intervening layer is a high-k dielectric.

Example 8 includes the subject matter of any of Examples 1 through 4, and further includes a gate dielectric material deposited on multiple surfaces of the channel body and on the intervening layer, the gate dielectric material being distinct from the insulator material of the intervening layer.

Example 9 includes the subject matter of Example 8, wherein the insulator material of the intervening layer is a low-k dielectric.

Example 10 includes the subject matter of Example 8, wherein the insulator material of the intervening layer is silicon dioxide.

Example 11 includes the subject matter of any of Examples 8 through 10, wherein the gate dielectric material is on at least sidewalls of the channel body, and the integrated circuit further comprises a gate electrode material on the gate dielectric material, so as to provide one of a double-gate or tri-gate structure, the insulator material filling a gap between the channel body

Example 12 includes the subject matter of any of Examples 8 through 10, wherein the gate dielectric material surrounds the channel body, and the integrated circuit further comprises a gate electrode material on the gate dielectric material and surrounding the channel body, so as to provide a gate-all-around structure, the insulator material, the gate dielectric material, and the gate electrode material collectively filling a gap between the channel body and the sub-fin.

Example 13 includes the subject matter of any of the preceding Examples, wherein the channel body is silicon germanium (Sii _-x Ge _x , where 0.2 < x < 1.0) and the sub-fin is silicon (Si). Note that the channel body can be pure germanium, when x = 1.0.

Example 14 includes the subject matter of any of the preceding Examples, wherein the first group IV semiconductor material includes germanium (Ge) at a concentration of at least 20 atomic percent.

Example 15 includes the subject matter of any of the preceding Examples, wherein the first group IV semiconductor material has a first band gap that is lower than a second band gap of the second group IV semiconductor material.

Example 16 includes the subject matter of any of the preceding Examples, wherein the substrate includes the second group IV semiconductor material.

Example 17 includes the subject matter of any of the preceding Examples, and further includes source and drain regions adjacent to the channel body, such that the channel body is between the source region and the drain region.

Example 18 includes the subject matter of any of the preceding Examples, wherein the integrated circuit is part of a mobile computing device.

Example 19 is an integrated circuit comprising: a channel body comprising germanium; a sub-fin below the channel body and extending upward from an underlying substrate, the sub-fin being silicon; an intervening layer of insulator material between the channel body and the sub- fin, the intervening layer in contact with at least the top of the sub -fin; and trench isolation in contact with lower sidewalls of the sub-fin.

Example 20 includes the subject matter of Example 19, wherein the intervening layer is also in contact with upper sidewalls of the sub -fin that are not in contact with the trench isolation. Example 21 includes the subject matter of Example 19 or 20, wherein the intervening layer includes an oxide or nitride material.

Example 22 includes the subject matter of any of Examples 19 through 21, and further includes a gate dielectric material on multiple surfaces of the channel body and on the intervening layer, the gate dielectric material being the same as the insulator material of the intervening layer.

Example 23 includes the subject matter of Example 22, wherein the gate dielectric material surrounds the channel body, and the integrated circuit further comprises a gate electrode material on the gate dielectric material and surrounding the channel body, the gate dielectric and gate electrode materials collectively filling a gap between the channel body and the sub-fin.

Example 24 includes the subject matter of Example 22 or 23, wherein the insulator material of the intervening layer is a high-k dielectric.

Example 25 includes the subject matter of any of Examples 19 through 21, and further includes a gate dielectric material deposited on multiple surfaces of the channel body and on the intervening layer, the gate dielectric material being distinct from the insulator material of the intervening layer.

Example 26 includes the subject matter of Example 25, wherein the insulator material of the intervening layer is a low-k dielectric.

Example 27 includes the subject matter of Example 25, wherein the insulator material of the intervening layer is silicon dioxide.

Example 28 includes the subject matter of any of Examples 25 through 27, wherein the gate dielectric material is on at least sidewalls of the channel body, and the integrated circuit further comprises a gate electrode material on the gate dielectric material, the insulator material filling a gap between the channel body and the sub -fin.

Example 29 includes the subject matter of any of Examples 25 through 27, wherein the gate dielectric material surrounds the channel body, and the integrated circuit further comprises a gate electrode material on the gate dielectric material and surrounding the channel body, the insulator material, the gate dielectric material, and the gate electrode material collectively filling a gap between the channel body and the sub-fin.

Example 30 includes the subject matter of any of Examples 19 through 29, wherein the channel body is silicon germanium (Sii _-x Ge _x , where 0.2 < x < 1.0). Note that the channel body can be pure germanium, when x = 1.0. Example 31 includes the subject matter of any of Examples 19 through 30, wherein the sub-fin is part of the substrate.

Example 32 includes the subject matter of any of Examples 19 through 31, and further includes source and drain regions adjacent to the channel body.

Example 33 includes the subject matter of any of Examples 19 through 32 wherein the integrated circuit is part of a mobile computing device.

Example 34 is a method for forming an integrated circuit, the method comprising: providing a channel body including a first group IV semiconductor material; providing a sub -fin below the channel body and extending upward from an underlying substrate, the sub-fin including a second group IV semiconductor material different from the first group IV semiconductor material, wherein the sub-fin is provided prior to the channel body being provided; forming a gap between the channel body and the sub-fin; providing an intervening layer of insulator material in the gap between the channel body and the sub -fin, the intervening layer in contact with at least the top of the sub-fin; and providing trench isolation in contact with lower sidewalls of the sub-fin, wherein the trench isolation is provided prior to the intervening layer being provided.

Example 35 includes the subject matter of Example 34, wherein the intervening layer is also in contact with upper sidewalls of the sub -fin that are not in contact with the trench isolation.

Example 36 includes the subject matter of Example 34 or 35, wherein the first group IV semiconductor comprises germanium and the second group IV semiconductor material is silicon (Si) and the intervening layer is in direct contact with the Si.

Example 37 includes the subject matter of any of Examples 34 through 36, wherein the intervening layer includes an oxide or nitride material.

Example 38 includes the subject matter of any of Examples 34 through 36, and further includes a gate dielectric material on multiple surfaces of the channel body and on the intervening layer, the gate dielectric material being the same as the insulator material of the intervening layer.

Example 39 includes the subject matter of Example 38, wherein the gate dielectric material surrounds the channel body, and the method further comprises providing a gate electrode material on the gate dielectric material and surrounding the channel body, so as to provide a gate-all-around structure, the gate dielectric and gate electrode materials collectively filling the gap between the channel body and the sub-fin.

Example 40 includes the subject matter of Example 38 or 39, wherein the insulator material of the intervening layer is a high-k dielectric.

Example 41 includes the subject matter of any of Examples 34 through 36, and further includes providing a gate dielectric material deposited on multiple surfaces of the channel body and on the intervening layer, the gate dielectric material being distinct from the insulator material of the intervening layer.

Example 42 includes the subject matter of Example 41, wherein the insulator material of the intervening layer is a low-k dielectric.

Example 43 includes the subject matter of Example 41, wherein the insulator material of the intervening layer is silicon dioxide.

Example 44 includes the subject matter of any of Examples 41 through 43, wherein the gate dielectric material is on at least sidewalls of the channel body, and the method further comprises providing a gate electrode material on the gate dielectric material, so as to provide one of a double-gate or tri-gate structure, the insulator material filling the gap between the channel

Example 45 includes the subject matter of any of Examples 41 through 43, wherein the gate dielectric material surrounds the channel body, and the method further comprises providing a gate electrode material on the gate dielectric material and surrounding the channel body, so as to provide a gate-all-around structure, the insulator material, the gate dielectric material, and the gate electrode material collectively filling the gap between the channel body and the sub-fin.

Example 46 includes the subject matter of any of Examples 34 through 45, wherein the channel body is silicon germanium (Sii _-x Ge _x , where 0.2 < x < 1.0) and the sub-fin is silicon (Si). Note that the channel body can be pure germanium, when x = 1.0.

Example 47 includes the subject matter of any of Examples 34 through 46, wherein the first group IV semiconductor material includes germanium (Ge) at a concentration of at least 20 atomic percent.

Example 48 includes the subject matter of any of Examples 34 through 47, wherein the first group IV semiconductor material has a first band gap that is lower than a second band gap of the second group IV semiconductor material. Example 49 includes the subject matter of any of Examples 34 through 48, wherein the substrate includes the second group IV semiconductor material.

Example 50 includes the subject matter of any of Examples 34 through 46, and further includes providing source and drain regions adjacent to the channel body, such that the channel body is between the source region and the drain region.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.