"Remote Reconf igur able FPGA based GNSS SDR receiver"

Technical Field

The present application describes a Global navigation satellite system ( GNSS ) software-defined radio ( SDR) receiver based on a field-programmable gate array ( FPGA) and processing system .

Background art

Document IN00806K02015 , describes a system for dynamically configuring circuits in the logic fabric of an FPGA. A communication interface for remote trans fer of smaller Dynamic Partial Reconfiguration ( DPR) files to the FPGA is also presented in this patent . In the aforementioned document , the combination of remote communication with an FPGA is described and validated . With this in mind, more patent application documents regarding remote FPGA reconfiguration are presented .

Document US2020321965 AA propose a method for programming a FPGA via a network, and a network configuration to carry out the method . The authors highlight that , in the state of the art , there are two update methods : indirect update via Joint Test Action Group ( JTAG) or direct update via the FPGA itsel f . However, both of these methods present drawbacks concerning performance , complexity, costs , and alternatively, they propose a di f ferent method for programming the FPGA, via a network operated system according to a predetermined communications protocol . A communication channel is established between the FPGA and an external master, where the FPGA receives the programming image in a sequence of frames . The programming image is contained in the payload section . Afterwards the FPGA is set , and the programming data contained in the payload is written into the FPGA. The stages of receiving the FPGA programming image and parsing the frames are performed by a statically programmed or hardwired logic module .

Finally, document CN106886438 A discloses the use of an update method via WI FI . Similar to the previous presented documents , the main obj ective is the communication between the FPGA and an external source . Analogously to the previously mentioned patents the core novelty is the capability to remotely update the FPGA.

Therefore , it becomes clear that remote configuration is feasible for appl ications in other technology sectors , such as GNSS . GNSS receivers are highly dependent on preimplemented algorithms . The present invention aims to circumvent this dependency with flexible SDR technology that can be remotely updated . The remote/over-the-air reconfiguration capabilities of the FPGA associated with the flexibility of a GNSS SDR receiver bring forward the potential of real-time adj ustments to receiver operation .

Summary

The present invention describes a FPGA GNSS SDR receiver system comprising a processing system; and a programmable logic module ; wherein the processing system is configured to receive a configuration message , and based on instructions present in said configuration message , perform a dynamic partial reconfiguration to the programmable logic module through a processor configuration access port . In a proposed embodiment of present invention, the processing system comprises a security module , a dynamic partial reconfiguration module and a Global navigation satellite system software-defined radio receiver module .

Yet in another proposed embodiment of present invention, the programmable logic module compri ses a reconfigurable logic module and a static logic module .

Yet in another proposed embodiment of present invention, the FPGA GNSS SDR receiver system comprises a RAM module , a ROM module and a Processor Configuration Access Port .

Yet in another proposed embodiment of present invention, the dynamic partial reconfiguration module is configured to send a partial bitstream of the configuration message from the ROM memory to the RAM module and to the programable logic module through the processor configuration access port .

Yet in another proposed embodiment of present invention, the configuration message comprises one of a first message type comprised of configuration data, or one of an second message type comprised of upgrade data .

Yet in another proposed embodiment of present invention, the configuration data allows the dynamic partial reconfiguration module to choose each bitstream stored on RAM module and ROM module that will configure the reconfigurable logic module .

Yet in another proposed embodiment of present invention, the upgrade data allows the dynamic partial reconfiguration module to configure the reconfigurable logic module for the new upgrade configuration .

The present invention further describes method to operate the FPGA GNSS SDR receiver system according to any of the previous description, comprising the steps of the communication security module , receiving a configuration message comprised of configuration data sent by a server with the new configurations , decrypting it , and validating its authenticity and integrity, forwarding it to the dynamic partial reconfiguration module ; the dynamic partial reconfiguration module copying bitstreams of the message from ROM module to the RAM module in case of said bitstreams are not present in the RAM module ; dynamic partial reconfiguration module chooses a set of bitstreams that match the configurations received in the message and reconfigures the needed modules inside the RLM; dynamic partial reconfiguration module changes the configuration of the GNSS SDR receiver module to match new received configuration .

In another proposed embodiment of present invention, the method to operate the FPGA GNSS SDR receiver system according to any of the previous description, comprises the steps of the communication security module , receiving a configuration message comprised of upgrade data sent by a server with the new configurations , decrypting it , and validating its authenticity and integrity, forwarding it to the dynamic partial reconfiguration module where the request to update the onboard architecture , is received; the dynamic partial reconfiguration module starts the process of replacing the stored bitstreams , erasing the old ones from the ROM module and afterwards it copies the new bitstreams on the message to said ROM module ; the system configured with a new version of the architecture , will proceed with the reconfiguration of the reconfigurable logic module .

General Description

The present application describes a FPGA GNSS SDR receiver .

Traditional real time Global Navigation Satellite System ( GNSS ) receivers rely on inherently static implementations . With the advent of GNSS moderni zation, the traditional approach for new receiver development would be the design and production of the receiver with minimum component reuse . This characteristic is a limiting factor for the development of GNSS receivers that require constant upgradability and adaptability to various application settings and to regional restrictions . More speci fically, a Remote Reconfigurable FPGA based GNSS SDR receiver is capable of Dynamic Partial Reconfiguration ( DPR) , in order to remotely update its design on demand and without the need of discontinuing complete system operation .

Partial Reconfiguration enables portions of the FPGA to be reconfigured during runtime , while the remaining system continues its normal operation . This characteristic allows for critical real-time continuous updates while guaranteeing minimum receiver functionality during the reconf iguration process . Additionally, DPR provides granularity to the system and continuous communication link between the FPGA and an external server during partial reconfiguration . One of the main advantages of using DPR coupled with Software- Defined Radio ( SDR) is the use of upgradable GNSS-speci f ic Digital Signal Processors ( DSP ) accelerators which can be deployed over-the-air . These DSP accelerators are used to of fload compute- intensive operations in the GNSS receiver chain . With hardware updates the need for corresponding software/ firmware updates is also required . A technology that can fit the software flexibility requirement is SDR . The combination of DPR and SDR allows for complete adaptability which covers the hardware and software needs of the receiver .

Brief description of the drawings

For better understanding of the present application, figures representing preferred embodiments are herein attached which, however, are not intended to limit the technique disclosed herein .

Fig . 1 - illustrates the overal l developed FPGA GNSS SDR receiver, wherein the reference numbers are related to .

10 - system / FPGA GNSS SDR receiver ;

20 - processing module ;

30 - programmable logic module ;

101 - communication security module ;

102 - dynamic partial reconfiguration ( DPR) module ;

103 - Global navigation satellite system ( GNSS ) software-defined radio ( SDR) receiver module ;

104 - RAM module ( DDR) ;

105 - ROM module / Flash configuration storage / nonvolatile memory;

106 - Processor Configuration Access Port ( PCAP ) ;

107 - Reconfigurable logic module (RLM)

108 - Static logic module ( SLM)

200 - configuration message / software / partial bit files update package ;

300 - wireless transmission ; 1001 - update A / store;

1002 - update B / transmit;

1071 - RLM HW 1;

1072 - RLM HW 2;

1073 - RLM HW 3;

1074 - RLM HW 4;

1075 - RLM HW N;

1081 - SLM HW 1;

1082 - SLM HW 2;

1083 - SLM HW N.

Description of Embodiments

With reference to the figures, some embodiments are now described in more detail, which are however not intended to limit the scope of the present application.

The proposed FPGA GNSS SDR receiver (10) architecture is comprised of two main modules: the processing module (20) and the programmable logic module (30) .

The processing module (20) incorporates a module responsible for DPR management (102) , a module responsible for the GNSS software stack (103) and a module for communication security (101) .

The DPR module (102) is responsible for sending the partial bitstream of the configuration message (200) from the nonvolatile memory (105) to the RAM module (104) . When the bitstreams of the configuration message (200) are remotely updated to the RAM module (104) , the DPR module (102) is configured to send the partial bitstreams from the RAM (104) to the reconfigurable region, i.e., the programable logic module (30) , through the processor configuration access port

(106) .

The GNSS-SDR module (103) runs the GNSS signal processing chain and controls the operation of DSP hardware accelerators. Examples of GNSS signal processing conducted in the GNSS SDR stack (103) are: navigation algorithms, position algorithms, position-velocity-time (PVT) computation, pseudo-range and observable processing.

Regarding the programmable logic module (30) , two main regions are defined: a reconfigurable logic module (107) and a static logic module (108) . The static logic module (108) can' t be updated and runs operations that were preconfigured. Contrary to the static module (108) , the reconfigurable logic module (107) can be updated on demand, being this update conducted with the bitstreams contained in a configuration message (200) , which is received through the Processor Configuration Access Port (106) . The reconfigurable logic module (107) comprises at least one RLM hardware module (1071) , up to a maximum of N RLM hardware modules (1075) . Identically, the static logic module (108) comprises at least one SLM hardware module (1081) , up to a maximum of N SLM hardware modules (1083) .

Finally, the communications security is handled by a commercial off-the-shelf (COTS) security module (101) . This module (101) incorporates all the security subsystems that allow the remote reconfigurable receiver security features of an Internet-of-things (loT) system. The overall hardware operation of the developed system (10) mainly consists of two operation modes, orchestrated by the DPR software module (102) .

The first operation mode of the FPGA GNSS SDR receiver (10) comprises the configuration of the Reconfigurable logic module (107) hardware to an "already existing configuration", and the second operation mode updates the RLM (107) with "new remotely received bitstreams".

These bitstreams are partial bitstreams, meaning that they only configure a part of the architecture deployed inside the FPGA (10) . In particular, these bitstreams implement algorithms that process the GNSS signal (e.g., acquisition, and tracking modules of the SDR system) , being therefore considered as "hardware configurations" for the modules inside the RLM (107) .

In resume, in the first operation mode, the message (200) will only carry configuration data for the system (10) , telling the system (10) on how to configure the SDR receiver module (103) and the RLM (107) hardware to meet the requirements of a specific use case. The configuration in the message (200) will be used by the DPR module (102) to reconfigure the FPGA using the stored bitstreams in memory as well as the SDR module (103) .

Setting the configuration to an "already existing configuration" means that the partial bitstreams of the message (200) used to reconfigure the FPGA (10) are already present in the system and not deployed over-the-air . These configurations allow the RLM (107) hardware to change according with runtime field conditions. The two operation modes are required because, when sending new configurations to the system (10) , the server sends a lightweight message (200) only with the data configurations, and only sends the full message (200) when it is required to update the system. So, the system (10) operates with the hardware configuration version that is present in the system in the first operating mode, and when the entity that controls the system (10) wants to upgrade it to a new version, it uses the second operating mode for sending new configurations for the RLM (107) hardware.

This is important for several situation requirements, p.e., new algorithm deployment, new GNSS configurations regarding constellations, more efficient design updates, new features, etc. Once the system (10) has a huge part of their computational intensive tasks offloaded to RLM (107) hardware, it is possible to achieve flexibility in the DPR (102) module. That implies that the server pre-configures the modules and send it to the system (10) deployed in a remote field to be able to update the system architecture remotely .

Particularly, in the first operation mode, a configuration message (200) is sent by a server to a receiver (10) through wireless transmission (300) , said message (200) comprising partial configuration data which will be stored in the FPGA GNSS SDR receiver (10) . Once an initialization command present in the partial configuration controls of the message (200) is received, the system (10) performs a dynamic partial reconfiguration (102) of the reconfigurable RLM (107) module, where the bitstreams stored in the system (105, 104) are copied over the PCAP (106) to configure the modules inside the RLM (107) . Additionally, the software configurations contained in the configuration message (200) are applied to the GNSS SDR module (103) , enabling it to proper operate with the new reconfigurable RLM (107) . This is all done while the system ensures its normal operation, so there will be a mechanism to iteratively update the system, keeping the system working with the minimal requirements possible. The configuration of the system is not done all at once, in order to keeping it online. So, just a few modules of the RLM (107) will be updated at time. This process is done iteratively, until all the overall desired configuration is achieved. This can be done because the system deployed inside the RLM (107) is very modular and independent from each other. For instance, to upgrade the acquisition algorithm of a frequency of one GNSS constellation, firstly some spare modules will be reconfigured with the new algorithms, and when operational, connecting that to the SDR module (103) and switching off the old version of the algorithms of that frequency. Doing so, will provide the existence of spare RLM (107) reserved for the upgrades.

In the second operation mode, the FPGA GNSS SDR receiver (10) is again updated through wireless transmission (300) .

A configuration message (200) is also sent by a remote server with the new bitstreams and the desired configurations. Then, these bitstreams are stored (1001) in a non-volatile memory block, i.e., an ROM module (105) . Afterwards, the bitstreams are transmitted (1002) to the RAM module (104) and the dynamic partial reconfiguration is performed. As with the first operation mode, the GNSS-SDR software configurations are adapted to cater to the needs of the new hardware.