BACKGROUND ART Voltage regulator circuits can serve numerous purposes in integrated circuit devices. One particular application can be as a regulated internal power supply voltage for certain sections of an integrated circuit device. Even more particularly, voltage regulators can supply a power supply voltage to memory cell arrays within memory devices, such as dynamic random access memories (DRAMs) and static RAMs (SRAMs), as but two of the many possible applications.

Among the various types of voltage regulators are replica biased voltage regulators. Generally, in a replica biased voltage regulator a voltage established in one portion of a circuit (e. g., one leg), is replicated, typically by larger sized devices, to present a load (output) voltage. The load voltage is regulated by having it track the replica voltage as close as possible.

Prior art replica biased voltage regulators basically use active (dynamic) line regulation and passive (static) load regulation. Such approaches can achieve a good high-frequency transient response at the expense of poor DC load regulation.

In order to improve on DC load regulation and to prevent overshoots, either permanent or switched dummy loads have been proposed. Thus, existing replica biased voltage regulators have active (dynamic) line regulation and passive (static) load regulation. Various improvements have been proposed in order to better control output voltage over the load current range. These involve the use of fast voltage comparators in order to switch on/off dummy loads or additional current sourcing elements.

One example of an approach employing a switched dummy load is shown in FIG. 11. FIG. 11 shows a conventional replica biased voltage regulator circuit in a schematic diagram designated by the general reference character 1100.

In the example of FIG. 11, a voltage regulator circuit 1100 can include a

dummy load (Rdummy), which can be switched into the output path when an output voltage (Vpwr) exceeds a reference voltage (Vref). Conversely, dummy load (Rdummy) can be isolated from an output when the output voltage (Vpwr) falls below the reference voltage (Vref). In this way, switched dummy load (Rdummy) can regulate output voltage (Vpwr) to a particular range.

Alternatively, in order to prevent Vpwr from dropping under increased current load conditions, the inclusion of switched P-type devices have been proposed, as presented in FIG. 12 and U. S. Patent No. 6,373, 231, issued to Lacey et al. on April 16,2002.

In the example of FIG. 12, a voltage regulator circuit 1200 can include p- type switching device P1 in addition to a permanent dummy load Rdummy. When an output voltage (Vpwr) exceeds a reference voltage (Vref), p-type device P1 can be turned off reducing current supplied to load device (Vdummy) and thus lowering output voltage. Conversely, when the output voltage (Vpwr) falls below the reference voltage (Vref), p-type device P1 can be turned on, increasing current supplied to load device (Vdummy) and thus raising the output voltage (Vpwr). In this way, a switched current supply can regulate output voltage (Vpwr) to a particular range.

The above conventional arrangements can suffer from drawbacks. First, <BR> <BR> active load regulation (e. g. , switching in of load device, or switching on of current supplies) is not a proportional response or timewise continuous. This means that regulation only happens during periods of time when the load current is either extremely low or extremely high, as opposed to load regulation taking place at all times. Since voltage comparators (Comp) are used, the regulation provided can be considered a"winner takes all"type of regulation, as opposed to having proportionality between load current variation and compensation current.

Second, conventional switching load regulation can have an undesirable lag in response. Even if fast comparators are used, current technologies cannot guarantee response times faster than 1-2 nanoseconds. This may be insufficient in certain applications (e. g. , fast SRAMs). That is, this load regulation mechanism can work poorly in the high frequency domain (1 OMHz-1 GHz), since even fast voltage comparator driven feedback loops still have a response time on the order of a few nanoseconds.

Third, the above arrangement requires deploying extra voltage comparators.

This can increase operating current consumption.

In light of the above, it would be desirable to arrive at a voltage regulator that does not suffer from the above drawbacks of conventional approaches.

More particularly, it would be desirable to provide a replica biased voltage regulator having active (dynamic) load regulation and reduced output impedance in both the low and high frequency domains.

DISCLOSURE OF INVENTION The present invention can include a voltage regulator circuit having a negative feedback loop that alters a supply current in response to a comparison between a replica voltage and a predetermined reference voltage. In addition, a current conveyor circuit can be coupled to a replica node and an output node and provide an output voltage. The current conveyor circuit can operate to force the replica voltage and output voltage to mirror one another.

The present invention can also include a voltage regulator circuit that includes a current conveyor circuit having replica leg that provides a replica voltage and an output leg, arranged in parallel with the replica leg, that provides a regulated output voltage. The replica leg and output leg can have cross coupled active devices that provide fast positive feedback for forcing the replica voltage and output voltage to essentially track one another. The voltage regulator circuit can further include at least one load supply transistor arranged in parallel with the output leg for providing a current to the output node that follows the current in the output leg.

The present invention can further include a voltage regulator circuit that includes a negative feedback loop that alters a current provided to a replica voltage node in response to differences between the replica voltage and a reference voltage to provide low frequency regulation of the replica voltage. In addition, the voltage regulator circuit can include a current conveyor circuit that includes a voltage mirror circuit that forces an output voltage to essentially follow the replica voltage to provide high frequency regulation of the output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a voltage regulator according to a first embodiment.

FIG. 2 is a schematic diagram of a conventional voltage regulator circuit model.

FIG. 3 is a timing diagram showing a waveform utilized to simulate the transient response of the circuits shown in FIGS. 1 and 2.

FIG. 4 is a timing diagram showing a comparative response between the circuits of FIG. 1 and the circuit of FIG. 2.

FIG. 5 shows a section of FIG. 4.

FIG. 6 shows a section of FIG. 5.

FIG. 7 shows another section of FIG. 5.

FIG. 8 shows an instantaneous response of a node Vnet4 in the circuit shown in FIG. 1.

FIG. 9 is a graph showing the output impedance of the circuit of FIG. 1 versus the circuit of FIG. 2.

FIG. 10 is schematic diagram of another embodiment of the present invention.

FIG. 11 is a schematic diagram of a first conventional voltage regulator circuit.

FIG. 12 is a schematic diagram of a second conventional voltage regulator circuit.

MODE (S) FOR CARRYING OUT THE INVENTION Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments describe a replica biased voltage regulator that can provide continuous and proportional load regulation. In addition, such a voltage regulator can provide a quasi- instantaneous response to high-frequency load transients that can be superior to that of the conventional examples noted above.

A replica biased voltage regulator according to a first embodiment is set forth in FIG. 1 and designated by the general reference character 100. A voltage regulator 100 can include an amplifier 102, a supply section 104, a current

conveyor 106, a replica load 108, a supplemental load supply 110, and a load 112. A replica voltage (Vrep) can be generated at one node Vnet5, while an output voltage (Vload) can be generated at a node Vnet6.

Amplifier 102 can be an operational amplifier that can serve in a negative feedback loop as will be described below. A noninverting input of amplifier 102 can receive a reference voltage (Vref) while an inverting input can receive a replica voltage (Vrep).

A supply section 104 can provide current to at least two different legs of voltage regulator 100. Such a current supply can be scaled so that the current provided for an output leg (N3/N5) can be larger than that of the replica leg (N4/N6). In the very particular example of FIG. 1, supply section 104 includes n- channel transistors N1 and N2 having drains connected to power supply voltage Vcc, and gates commonly connected to the output of amplifier 102. Transistor N1 can be scaled to be"n"times as large as transistor N2. That is, a size ratio for transistors N1 : N2 can be n: 1, where n is greater than 1. Transistor N2 can provide a current for a replica leg, while transistor N1 can provide a current for an output leg as well as supplemental load device 110.

A current conveyor 106 can provide a replica voltage (Vrep) on a replica leg and an output voltage (Vload) on an output leg. However, unlike conventional arrangements, such circuit legs are arranged as"voltage mirrors", with the replica voltage (Vrep) essentially being forced to track the output voltage (load), and vice versa.

In the very particular example of FIG. 1, current conveyor 106 can include n-type transistors N4 and N6 arranged in series with one another to form a replica leg, and transistors N3 and N5 arranged in series to provide an output leg. The gate of transistor N4 can be connected to its drain, the gate of transistor N6 can be connected to the drain of transistor N5, and the gate of transistor N5 can be connected to the drain of transistor N6. Thus, transistors N5 and N6 can be cross coupled with respect to one another. The replica voltage (Vrep) can be provided at the source of transistor N6 and the output voltage (Vload) can be provided at the source of transistor N5.

Transistors (N3, N4, N5, N6) of current conveyor 106 are preferably <BR> <BR> matched devices, having the same properties (e. g. , threshold voltage) and same

size. As will be described below in more detail, such an arrangement provides for rapid"positive feedback"response that forces Vrep = Vload.

A replica load 108 can generate a replica voltage (Vrep) according to a current supplied from replica leg (N4, N6). A replica load 108 is represented in FIG. 1 by resistor Rrep and capacitor Crep, in parallel, but could take alternate forms as understood by one skilled in the art.

Similarly, a load 112 can generate an output voltage (Vload) according to a current supplied from replica leg (N4, N6). An output load 112 is represented in FIG. 1 by capacitor Cload as well as nondepicted load resistance drawing current Iload.

A supplemental load supply 110 can provide current to output node (Vnet6), and can be sized to be proportional to devices in the output leg. More particularly, given a size ratio for N1 : N2 of n : 1, a ratio for N5: N7 can be 1: (n-1).

As noted above, an amplifier 102 can provide negative feedback with respect to replica voltage (Vrep). In particular, as the replica voltage (Vrep) falls below a reference voltage (Vref) an output voltage provided by amplifier 102 can increase, and additional current can flow through the replica leg, resulting in a higher replica voltage (Vrep). Conversely, as the replica voltage (Vrep) rises above a reference voltage (Vref), an output voltage provided by amplifier 102 can decrease, reducing current flowing through the replica leg, resulting in a lower replica voltage (Vrep).

The voltage mirroring effect of a current conveyor 106 according to the embodiment of FIG. 1 will now be described in more detail. It will be assumed that devices N3, N4, N5 and N6 are identical and have the same DC operating current. Thus, all devices N3-N6 have the same transconductance (gm3=gm4=gm5=gm6). Accordingly, the following relations hold : (1) gm3* (Vnet2-Vnet3) =gm5* (Vnet4-Vload) (2) gm4* (Vnet2-Vnet4) =gm6* (Vnet3-Vrep) (3) Vnet2-Vnet3=Vnet4-Vload (4) Vnet2-Vnet4=Vnet3-Vrep (5) Vload=Vrep

Therefore, because of the connection of the gates of N3, N4 to node Vnet2, the current conveyor 106 forces the output voltage (Vload) to be equal to the replica voltage (Vrep), and vice-versa, in the AC small signal domain. At the same time, however, replica voltage (Vrep) should be kept essentially constant, either by the negative feedback loop, if within the unity gain bandwidth of amplifier 102, or by capacitor Crep, if beyond it. In this way, the circuit conveyor 106 can transfer the low output impedance, from the replica to the load.

Because the output capability of the circuit (e. g., Iload) is higher than the replica current within replica leg (N4, N6), transistor N7 can take over any extra load current needed. Such an arrangement is possible due the sizing of transistors, as noted above, (e. g., N1 and N2 scaled n: 1, while N7 and N3-N6 are scaled (n-1): 1).

Accordingly, due to the operation of current conveyor 106, a variation of output voltage (Vload) is going to produce a similar variation in replica voltage (Vrep), which is then going to be corrected for by the line regulation negative feedback loop noted above. Looked at in another way, load regulation can be provided by transferring the output voltage (Vload) information to the negative feedback loop. Thus, if a load current (Iload) increases and Vload drops, this leads to a drop in the voltage at node Vnet3, followed by a drop in replica voltage (Vrep). Such a drop causes an increase in the voltage on the gates of N1, N2 and a subsequent correction of the output voltage (load).

The response of the voltage regulator circuit according to the embodiment of FIG. 1, may be further understood with a more detailed analysis. A more detailed analysis yields the following output impedance formula: g", is the transconductance of transistors N3-N6 aO is the gain of the amplifier 102 a0 = 2qfo, where 0 is the cutoff frequency of the operational amplifier I-gm/Crep<BR> 2t72 = nao gm/Cload

In light of the above analysis, in order to minimize the output impedance, it would be desirable to use large-bandwidth current conveyor transistors and operational amplifiers (increase aOarO), as well as large replica load capacitance (Crep) values (decrease zu,). A modest DC gain, of about 30dB, can be sufficient for the wide band operational amplifier. The load capacitance Cload introduces its own pole in the output impedance expression, helping the high frequency transient response.

In one particular implementation, the operational amplifier 102 unity-gain bandwidth is 55MHz, while the gain is 28dB.

Referring still to the embodiment of FIG. 1, in the low and medium frequency domain, output impedance drops by a factor ao with respect to the output impedance of a conventional replica biased voltage regulator, like that described above.

Beyond the loop unity gain bandwidth (aou0) the output impedance levels off and then it drops due to the poles introduced by the replica branch capacitor (U1) and the load capacitor (tau2).

Therefore, as previously noted, in order to minimize Zout (s) up to as high a frequency as possible, we need to use large bandwidth operational amplifiers (increase ars0) and large replica branch capacitor (decrease 1). Of course, an increased load capacitor can help with handling fast current transients (decrease s2).

The embodiment set forth in FIG. 1 can have several advantages over conventional arrangements, like those described above in FIGS. 11 and 12.

In particular, the voltage regulator 100 does not involve a second feedback loop. This can result in smaller current consumption than conventional arrangements. This can make the voltage regulator 100 applicable to mobile applications which typically seek lower current and/or power consuming devices.

Further, a voltage regulator 100 has only one negative feedback loop. This can eliminate stability issues that can arise due to loop-to-loop coupling.

In addition, in the voltage regulator 100, local positive feedback in the current conveyor is extremely fast, allowing for essentially instantaneous response

to high frequency transients. This is in contrast to conventional arrangements that can introduce operational amplifier response delay.

The embodiment disclosed can thus address the shortcomings of existing solutions listed above in the BACKGROUND OF INVENTION. More particularly, the embodiment of FIG. 1 includes: continuous and proportional load regulation by virtue of the load voltage information being transferred to the linear negative feedback loop ; good high frequency response, courtesy of the local positive feedback; and reduced current consumption, since no additional amplifiers (e. g., comparators) are needed.

One particular set of results is presented in the Table 1 below to illustrate the load regulation feature of the first embodiment. The example indicates a case in which a reference voltage has been set to 1. 300V. Corner Old circuit output voltage New circuit output voltage (Conditions) (FIG. 2) (FIG. 1) Load 3mA 30Ma 60mA 3mA 30mA 60mA current 2. 9V/140°C 1. 501 V 1. 315V 1. 199V 1. 343V 1. 313V 1. 301 V 3. 7V/140°C 1. 510V 1. 326V 1. 211 V 1. 353V 1. 324V 1. 313V 2. 9V/-40°C 1.448V 1. 308V 1. 221 V 1. 327V 1. 308V 1. 303V 3. 7V/-40°C 1. 451 V 1. 313V 1. 228V 1. 331 V 1. 314V 1. 310V Table 1 Table 1 shows how the example of FIG. 1 can provide advantageously better regulation than a conventional model shown in FIG. 2.

In order to simulate transient behavior, a simulation was conducted with a pulsed current waveform having a DC component of 10mA and peak value of 90mA. As will be shown in more detail below, the voltage regulator of the embodiment of FIG. 1 produced an output drop decrease from 130 mV peak-to- peak (for the case of FIG. 1) to 60 mV peak-to-peak. Such conditions were compared to a model representing one particular conventional voltage regulator shown in FIG. 2.

FIG. 3 is a timing diagram that shows a load current (Iload) waveform utilized to simulate a transient response.

FIG. 4 is a timing diagram showing a power supply response (Vcc) and an output voltage (Vpwr) for both the conventional case of FIG. 2 ("OLD CIRCUIT") as well as that of FIG. 1 ("NEW CIRCUIT").

FIG. 5 is a section of the Vpwr responses of FIG. 4, expanded along the vertical axis (voltage). This view also shows an input reference voltage"REFERENCE", which can correspond to reference voltage (Vref) of FIGS. 1 and 2.

FIG. 6 is a section of the Vpwr responses of FIG. 5, expanded along the horizontal axis (time). FIG. 7 shows another section of the Vpwr responses of FIG. 5, expanded along the horizontal axis (time), along with the reference voltage input (Vref). FIGS. 6 and 7 also clearly show the reduction in peak-to-peak voltage from about 130 mV ("old circuit") to about 60 mV ("new circuit").

FIG. 8 shows instantaneous response of node"Vnet4"in the current conveyor 106 to a drop in the load voltage (Vload) caused by the high frequency transient of the comparative simulations of FIGS. 3-7. FIG. 8 also shows the output voltage (Vpwr).

FIG. 9 comparatively shows the new circuit (FIG. 1) versus old circuit (FIG.

2) output impedance curves in the frequency domain. It is noted that the about 65% drop in high frequency output impedance accurately matches the 65% reduction in the HF output ripple presented in FIGS. 6 and 7.

It is noted that in the embodiment of FIG. 1, a certain voltage"overhead"may be needed to accommodate the series connected transistors of the current conveyor 106. That is, a minimum voltage difference between the drains of transistors N2/N1 and the sources of transistors N5/N6 may be needed. If normal n-channel transistor threshold voltages are too large, the extra necessary voltage overhead can be compensated for by using native devices, either in the n-type followers of current supply section 104 (N1, N2) or in the current conveyor N3-N7. In addition or alternatively, the gates of the N-type followers can be"pumped"by applying a voltage higher than a supply voltage Vcc.

While the embodiment of FIG. 1 can provide for improved voltage regulation, in some applications such regulation may only be needed in particular modes. One

example of a circuit that can disable high speed transient responses is shown FIG.

10.

A second embodiment is set forth in FIG. 10, and designated by the general reference character 1000. A second embodiment 10 can include the same general components as the first embodiment of FIG. 1, so like sections will be referred to by the same reference character but with the first digit being a"10" instead of a"1".

In the arrangement of FIG. 10, a current conveyor 1006 can be essentially bypassed, effectively reverting the voltage regulator 1000 to existing designs (e. g., model of FIG. 2). As shown, p-type transistor P1 and P2 switches can be used to this effect. When the signal BYPASSB transitions low, transistors P1 and P2 can turn on, short circuiting the current conveyor 1006 as well as the supplemental load supply 1010.

Such a feature may be advantageously employed to reduce current consumption in modes where regulation may not be required. As but one example, in a memory application, tight regulation may not be required in a low power data retention mode.

It is understood that the example of FIG. 1 is but one embodiment of the present invention and should not be construed as limiting the invention thereto.

For example, while an operational amplifier 102 can be a 2-stage circuit, optimizing such an operational amplifier could result in better results.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.