Title:
RESET CONTROL CIRCUIT, APPARATUS CONTROL DEVICE, AND CONTROL SYSTEM
Document Type and Number:
WIPO Patent Application WO/2010/089810
Kind Code:
A1
Abstract:
Each reset control circuit is arranged as a connection interface between a signal line for connecting a plurality of processors executing an existing program with the respective processors. Various signals including an instruction signal transmitted to all the processors via the signal line are received. The received instruction signal is transmitted to a processor of the connection destination. Switching is performed between a reset permitting state and a reset inhibiting state according to the signal transmitted from the processor of the connection destination in accordance with the transmitted instruction signal. If the existing signal is received in the reset permitting state, a reset signal for performing a reset is transmitted to the processor of the connection destination.
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Inventors:
KAKO MASANORI
KIKUE HISASHI
KOHARA MASARU
KIKUE HISASHI
KOHARA MASARU
Application Number:
PCT/JP2009/001965
Publication Date:
August 12, 2010
Filing Date:
April 30, 2009
Export Citation:
Assignee:
PANASONIC CORP (JP)
KAKO MASANORI
KIKUE HISASHI
KOHARA MASARU
KAKO MASANORI
KIKUE HISASHI
KOHARA MASARU
International Classes:
G06F1/24; G05B9/02; G06F15/177
Foreign References:
| JPH09319467A | 1997-12-12 | |||
| JPH08308008A | 1996-11-22 | |||
| JP2000020498A | 2000-01-21 |
Attorney, Agent or Firm:
NAKAJIMA, Shiro et al. (JP)
Shiro Nakajima (JP)
Shiro Nakajima (JP)
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