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Title:
RESIST PATTERN INSPECTION METHOD, RESIST PATTERN MANUFACTURING METHOD, SUBSTRATE SELECTION METHOD, AND MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE SUBSTRATE OR PRINTED CIRCUIT BOARD
Document Type and Number:
WIPO Patent Application WO/2024/024484
Kind Code:
A1
Abstract:
This resist pattern inspection method comprises an appearance inspection step for inspecting the appearance of a resist pattern on the basis of light emitted from a substrate whereon the resist pattern is formed. This resist pattern manufacturing method comprises: a resist pattern formation step for forming a resist pattern on a substrate; and a light-emitting material adhering step for adhering a light-emitting material to a surface of a conductor of the substrate. This substrate selection method comprises: the appearance inspection step for inspecting the appearance of the resist pattern on the basis of the light emitted from the substrate whereon the resist pattern is formed; and an evaluation step for evaluating the resist pattern on the basis of the appearance inspection in the appearance inspection step. This manufacturing method for a semiconductor package substrate or a printed circuit board comprises a conductor pattern formation step for forming a conductor pattern by etching or plating the substrate, the resist pattern of the substrate having been evaluated in the substrate selection method as meeting a standard.

Inventors:
KATO TETSUYA (JP)
Application Number:
PCT/JP2023/025480
Publication Date:
February 01, 2024
Filing Date:
July 10, 2023
Export Citation:
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Assignee:
RESONAC CORP (JP)
International Classes:
G01N21/956; G01N21/88; G03F7/20; H05K3/00; H05K3/06; H05K3/18
Foreign References:
JPH04213372A1992-08-04
JP2003243290A2003-08-29
JP2004233054A2004-08-19
JP2000193596A2000-07-14
JPH0294491A1990-04-05
JP2014009969A2014-01-20
JP2012233790A2012-11-29
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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