Title:
RESISTIVE RANDOM-ACCESS MEMORY, MEMORY DEVICE, AND MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2022/145251
Kind Code:
A1
Abstract:
The present invention reduces a leakage current of a MOS transistor which performs writing. This resistive random-access memory includes a memory cell, a write drive unit, a write control unit, and a well potential adjustment unit. The memory cell comprises a resistive random-access element. The write drive unit performs writing of data by applying a write voltage to the memory cell. The write control unit outputs a write control signal which controls the writing to the write drive unit. The well potential adjustment unit adjusts a well potential of a well region where an element which constitutes the write drive unit is arranged according to the write voltage at the time of writing.
Inventors:
TAKAHASHI HARUKO (JP)
KURODA MASAMI (JP)
TEZUKA HIROYUKI (JP)
KURODA MASAMI (JP)
TEZUKA HIROYUKI (JP)
Application Number:
PCT/JP2021/046488
Publication Date:
July 07, 2022
Filing Date:
December 16, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G11C11/16; G11C5/14; G11C13/00
Domestic Patent References:
| WO2010070895A1 | 2010-06-24 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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