RESISTIVE RANDOM-ACCESS MEMORY FORMED WITHOUT FORMING

VOLTAGE REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the priority of and incorporates by reference each of the following applications:

U.S. Prov. Ser. No. 61/828,667 filed May 29, 2013; and

U.S. Prov. Ser. No. 61/859,764 filed July 29, 2013.

The above-referenced provisional patent applications are collectively referenced herein as "the commonly assigned incorporated applications."

FIELD

[0002] The present invention generally relates mainly to resistive random- access memory devices. More particularly, some embodiments relate to resistive random-access memory formed without forming voltage, but rather using preformed pathway structures for enhancing mobility of charged species.

BACKGROUND

[0003] FIGs. 1 A-1 B are cross-section diagrams illustrating the forming process of a known resistive random-access memory (RRAM) device. RRAM (or memristor) device 100 has a bulk switching layer 1 12 (typically a transition metal oxide) between a top electrode 140 and bottom electrode 1 10. The bulk switching layer 1 12 is ordinarily non-conducting. However, by applying a sufficiently large voltage (a "forming voltage") across the top and bottom electrodes, conduction path(s) are formed within the bulk switching layer. The application of the large forming voltage, which exceeds the breakdown voltage, is depicted in FIG. 1A. FIG. 1 B shows the resulting conduction paths 120. Once the conduction paths are formed, they may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by an appropriately applied voltage (the "switching voltage").

[0004] As shown in FIG. 1 B, the paths taken by the charged

ions/vacancies/electrons take a haphazard path under an applied electric field. The difference in the path length can affect the voltage and current characteristics of the RRAM/memristor 100. For example, from a very simplistic physical iew, for transition metal-oxide switching iayer(s), a large number of positively charged oxygen vacancies (Vo+) can exist near the TE 140 (large number of Vo+ make the transition metal-oxide more conducting as there are less oxygen and more metal ions) and with an applied electric field, the Vo+ migrate toward BE 1 10. This forms a conducting filament along the path created by the forming voltage in the transition metal oxide switching layer that is highly resistive resulting in a low resistance state (LRS); with reverse bias, where the TE is negative, the Vo+ migrate back toward the TE resulting in a high resistance state (HRS).

[0005] A basic challenge that is common to conventional RRAM/memristors (and phase change memories) are that the charged species migrate along crystal grains, dislocations, and other crystaliographicai defects that occur during deposition of these films by various methods. Due to the randomness or pseudo- randomness of the grain boundaries and other defects, the migration or drift of the charged species (ions/vacancies/electrons) under an applied electric field occur in a haphazard way, going in the general direction toward the electrodes (along the electric field directions or lines) but taking the path of least resistance by making detours around areas of higher resistance. Subjecting the device to the high forming voltage in order to breakdown the high resistance regions to create low resistance paths, which are not usually the shortest paths between the top and bottom electrodes. The forming process and the haphazard nature of the path for the charged species to migrate under an applied electric field are not desirable features for large-scale memory/computing arrays for system applications.

[0008] FIG. 2 is a graph illustrating typical IV characteristics for conventional RRAM devices. Significant variations in the IV characteristics are often exhibited both in repeatability of the same RRAM device as well as between different RRAM devices within the same chip. In FIG. 2 two such different IV characteristic curves 210 and 212 are shown. Also shown in FIG. 2 is an example IV curve 220 illustrating the forming process. The variation in switching voltage Vs1 and variations in the resistivity of the states (high resistance state (HRS) and low resistance state (LRS) are shown in the slopes of the IV characteristics. The measured current Im1 changes at a given measurement voltage Vm1 . The variations in the HRS and LRS, as well as variations in the switching voltages to transit from HRS to LRS and from LRS to HRS, are not desirable from a system point of view as an algorithm needs to be developed to interrogate each memory to determine its operating point dynamically for a single memory element. Factoring in several billion to a few trillion memory elements, these variations can slow down the performance of the entire data storage and retrieval process.

[0007] The subject matter claimed herein is not limited to embodiments that solve any specific disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced,

SUMMARY

[0008] According to some embodiments, a resistive random-access memory device is described. The device includes a top electrode; a bottom electrode; and a material region disposed between the top and bottom electrodes, The material region has one or more enhanced mobility pathway structures configured to provide enhanced mobility of charged species, such that resistance between the top and bottom electrodes through the material region can be increased and decreased by applying a switching voltage between the top and bottom electrodes. The enhanced mobility pathway structures are initially formed without application of a voltage to the material region equal to or greater than a breakdown voltage for the material region. According to some preferred embodiments, the enhanced mobility pathway structures are initially formed without application of a voltage equal to or greater than three times the switching voltage. According to some some preferred embodiments, the enhanced mobility pathway structures are initially formed without application of any formation voltage.

[0009] According to some embodiments, the enhanced mobility pathway structures include an interface between first and second materials having different bandgap energies. The difference in bandgap energies enhances mobility of the charged species along the interface. According to some embodiments, the pathway structures include two adjacent interfaces, with a lower bandgap energy materia! being sandwiched between two higher bandgap energy materials. The resulting structure creates a potential well structure for charged species thereby enhancing mobility of charged species through the pathway structure. According to some embodiments, the enhanced mobility pathway structures include an interface between two portions of one material having different stress states at the interface thereby enhancing mobility of the charged species aiong the interface. According to some embodiments, the device further includes a charged species reservoir structure configured to provide charged species to decrease resistance within the pathway structures upon application of the switching voltage.

[0010] According to some embodiments, the enhanced mobility pathway structures include defects caused by an ion implantation process. The ion implantation process can be carried out before or after the top electrode is formed. According to some embodiments, the device further includes a charged species reservoir structure formed by the ion implantation process. The reservoir structure is configured to provide charged species to decrease resistance within the pathway structures upon application of the switching voltage. According to some embodiments the material region is formed in situ using the ion implantation process.

[0011] According to some embodiments, a method of fabricating a resistive random-access memory device is described. The method includes: forming a bottom electrode; forming a material region; forming a top electrode; and forming one or more enhanced mobility pathway structures configured to provide enhanced mobility of charged species such that resistance between the top and bottom electrodes through the material region can be increased and decreased by applying a switching voltage between the top and bottom electrodes. The forming of the enhanced mobility pathway structures does not include application of a voltage to the material region equal to or greater than a breakdown voltage for the materia! region.

[0012] According to some embodiments, a resistive random-access memory device is described that includes: a top electrode formed from a top electrode material; a bottom electrode formed from a bottom electrode material; and a materia! region disposed between the top and bottom electrodes. The material region is formed using an ion implantation process into the top, bottom, or both electrode materials. The material region has one or more enhanced mobility pathway structures configured to provide enhanced mobility of charged species, such that resistance between the top and bottom electrodes through the material region can be increased and decreased by applying a switching voltage between the top and bottom electrodes, According to some embodiments, the enhanced mobility pathway structures include a first interface between a first material and a second material; the first and second materials having different bandgap energies and the difference in bandgap energies enhances mobility of the charged species along the interface.

[0013] According to some embodiments, a method of fabricating a resistive random-access memory device is described that includes: forming a bottom electrode from a bottom electrode material; forming a top electrode from a top electrode material material; performing an ion implantation process into the top and/or bottom electrode materials, thereby forming a material region from the top and/or bottom electrode materials; and forming one or more enhanced mobility pathway structures within the material region, The pathway structures are configured to provide enhanced mobility of charged species such that resistance between the top and bottom electrodes through the material region can be increased and decreased by applying a switching voltage between the top and bottom electrodes. According to some embodiments, the forming of the enhanced mobility pathway structures uses the same ion implantation process and the enhanced mobility pathway structures include defects caused by the ion implantation process. According to some other embodiments, the enhanced mobility pathway structures are formed using a second ion implantation process which causes defects that enhancing mobility of the charged species.

[0014] As used herein the term "resistive random-access memory" and "RRAM" refers to any random access memory that relies on change of resistance and/or conductance, and in general includes devices such as RRAMs (or ReRAMs), memristors, and phase change memory devices. The term "memory" and "memories" refers in general to both digital and analog memory devices.

[0015] As used herein, the term "charged species" refers to charged particles, such as electrons, protons, ions, holes, as well as vacancies.

[0018] As used herein, the term "ion implantation" refers to implantation of any charged particles including ions and electrons. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To further clarify the above and other advantages and features of the subject matter of this patent specification, specific examples of embodiments thereof are illustrated in the appended drawings, it should be appreciated that these drawings depict only illustrative embodiments and are therefore not to be considered limiting of the scope of this patent specification or the appended claims. The subject matter hereof will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0018] FIGs. 1 A-1 B are cross-section diagrams illustrating the forming process of a known resistive random-access memory (RRAM) device;

[0019] FIG, 2 is a graph illustrating typical IV characteristics for conventional RRAM devices:

[0020] FIG, 3 is plot showing the IV characteristics of RRA /memristor devices, according to some embodiments;

[0021] FIGs. 4A-4G and 5A-5F are series of cross sections showing basic nanofabrication steps using a Park's block copolymer to generate nanohoie and nanopiilers, according to some embodiments;

[0022] FIG, 6 is an energy-bandgap diagram illustrating aspects of a heterojunction interface, according to some embodiments;

[0023] FIG. 7 is an energy-bandgap diagram illustrating aspects of a double heterojunction interface, according to some embodiments;

[0024] FIG. 8 is an energy-bandgap diagram illustrating aspects of a homojunction interface, according to some embodiments;

[0025] FIGs. 9A and 9B are cross sections showing aspects of enhanced mobility pathways structures according to some embodiments;

[0026] FIG. 10 is a top view showing aspects of enhanced mobility pathway structures positioning, according to some embodiments;

[0027] FIG. 1 1 shows a lateral hetero/homo junction interface with a high mobility channel structure, according to some embodiments;

[0028] FIGs. 12A-12D are diagrams showing aspects of ion implantation in a switching layer used to create an enhanced mobility pathway structure for RRAM devices, according to some embodiments; [0029] FIGs. 13A-13B are diagrams showing the use in multiple implantation energies and/or multiple ion species used to generate enhanced mobility pathway structures, according to some embodiments;

[0030] FIGs. 14A-14B are schematic cross sections illustrating aspects of using high dosage ion implantation to form a buried layer, according to some

embodiments;

[0031] FIGs. 15A-15B are cross sections showing aspects of using ion implantation to extend info the electrodes and overlap at the interface with the switching layer(s), according to some embodiments;

[0032] FIG. 16 is a cross section showing an example of two species of ion implantation, according to some embodiments;

[0033] FIGs. 17A-17B are cross sections illustrating an ion implantation followed by a tunnel or other layer epitaxial grown, according to some

embodiments; and

[0034] FIGs. 18A and 18B are cross sections illustrating aspects of forming a switching layer in-situ using ion implantation, according to some embodiments.

DETAILED DESCRIPTION

[0035] A detailed description of examples of preferred embodiments is provided below. While several embodiments are described, it should be understood that the new subject matter described in this patent specification is not limited to any one embodiment or combination of embodiments described herein, but Instead encompasses numerous alternatives, modifications, and equivalents. in addition, while numerous specific details are set forth in the following description in order to provide a thorough understanding, some embodiments can be practiced without some or ail of these details. Moreover, for the purpose of clarity, certain technical material that is known in the related art has not been described in detail in order to avoid unnecessarily obscuring the new subject matter described herein. it should be clear that individual features of one or several of the specific embodiments described herein can be used in combination with features or other described embodiments. Further, like reference numbers and designations in the various drawings indicate like elements. [0038] According to some embodiments enhanced ion/ acancy mobility channels are provided for the resistive random access memory, memristor and phase change memory (electron and hole paths) for a more definitive conduction path rather than more random conductive paths resulting from applied forming voltages.

[0037] According to some embodiments, the vacancies and ions travel at a single or double heterojunction or homojunction interface where there is a potential well for the vacancies, ions, electrons and/or holes to travel. This high mobility channel provides a more definitive path for the conducting filament to follow, rather than in a random nature. The random nature for conducting filaments formed by conventional methods, much like a lightning bolt, result in variances of the IV (current -voltage) characteristics of the resistive random access memory (RRAM) or memristor as shown in FIG. 2. In addition, according to some embodiments, mobility of the species at the hetero/homo junction interface can be more than 100X-1000X greater than the mobility of species (ions and vacancies) through a bulk transition metal oxide (TMO) film.

[0038] According to some embodiments, the high-mobility pathways take the form of crystaliographical defects in the switching layer(s) of a resistive random access memory (RRAM), or memristors, or phase change memory using ion implantation.

[0039] According to some embodiments, ion implantation, or any other method such as focused ion beam, electron beam, high energy accelerators, or x-rays, is used to create a region of defects where the charged ions, vacancies, electrons, and/or holes can flow under an applied electric field more directly between the top and bottom (or between two electrodes) electrodes in a more direct path than the rather-haphazard pathways formed using conventional breakdown-forming voltages. The techniques described herein also result in less variability in the current voltage (IV) characteristics of the RRAM/memristor and can eliminate or greatly simplify the forming process.

[0040] RRAM devices with the high-mobility pathways according to some embodiments, can be faster by 100-1000X or more, operate at a lower field that is not so close to breakdown field, have lower device capacitance (since the top and bottom electrodes can be spaced further apart), operate at a lower power, and exhibit less variance in the iV characteristics. Furthermore, according to some embodiments, reliability is improved as is the number of switching cycles.

[0041] FIG, 3 is a plot showing the IV characteristics of RRAM/memristor devices, according to some embodiments. IV curve 310 shows is for

RRAM/memristors with pre-formed enhanced mobility pathway structures providing enhanced mobility of charged species, according to some embodiments. The IV characteristics are highly reproducible without significant variations within a single device after multiple (e.g. thousands or millions) of state change cycles.

Furthermore, the characteristics are highly consistent from device to device within the entire memory/CPU array. The RRAM/memristor typically is in the HRS as fabricated. Depending on switching material and electrodes, the device can be unipolar or bipolar. A bipolar case being shown in FIG. 3, and where a typical transition metal oxide switching material is used with charged oxygen vacancies and oxygen ions migrating under an applied electric field.

[0042] In conventional RRAM/memristors, a forming process is needed to "activate" the device. The forming voltage is a high voltage with a high current compliance applied, typically in the range of tens of volts with compliance current in 1 s to 100s of microamps range. This forming voltage causes a breakdown of the initial as-fabricated high-resistance switching material to a low resistance state. The breakdown occurs, either at the interface between the electrode and the switching material, within the switching material itself, or at multiple locations. Once formed, the memory element can switch between the low resistance state (LRS) and high resistance state (HRS). Although the forming process is necessary for conventional devices, it is highly undesirable. Being a breakdown process, it can degrade the reliability of the device, and it is unpredictable. Furthermore, with billions or trillions of memory elements, the forming process can be time consuming and require extra high voltage/current circuits in a high density memory/CPU (computer processing unit) array or system.

[0043] The RRAM memory element can switch from LRS to HRS (referred to as a "reset") and from HRS to LRS (referred to as a "set"). In FIG. 3, the reset voltage (LRG to HRS) is ~Vs2 and the set voltage (HRS to LRS) is Vs1 . The direction of the bias, the polarity of the set and reset voltages are all dependent on the switching layer material, the interface of the switching layer material to the electrodes, and the electrode material Itself. As shown in FIG. 3, in the case of transition metal oxide switching layer(s) biasing to the set voltage Vs1 , (e.g. the top electrode (TE) positively biased with respect to the bottom electrode (BE)) causes positively charged oxygen vacancies (Vo+) to migrate toward the BE in the from of a conducting filament. This migration causes the memory element to switch from HRS curve 320 to LRS curve 322. At the reset voltage -Vs2, where the TE is negatively biased with respect to the BE, the memory element switch from LRS curve 322 to HRS curve 320. A simplistic physical view of the reset process is that the conducting filament retracts somewhat from the BE due to Vo+ migrating toward the TE. The states (HRS and LRS) are measured at Vm1 (or at -Vm2). According to some embodiments, a ratio of current between HRS and LRS at Vm1 (or -Vm2) is 10 or more. According to some embodiments, a ratio of greater than 100 is obtained. According to some embodiments, the LRS curve shows a non- linearity, According to some embodiments, the ratio of the steepest slope of the LRS curve to the shallowest slope of the LRS curve is greater than 2. According to some embodiments, that ratio is 10 or greater. The nonlinearity of the LRS curve reduces the effect of device to device leakage current in a crossbar array architecture. For example in a cross bar memory array configuration, if adjacent memory elements are all in the LRS, then measuring the state of one of the memory elements can also have a current contribution from adjacent memory elements that are also in the LRS. Without the desired non-linearit of the LRS curve, this cross talk in current can cause errors in reading the state of a memory element.

[0044] Formation of conductive filaments (CF) via migration of charged ions/vacancies/electrons under an applied electric field (or current) are found in many material systems. Examples include: metal oxides, metal nitrides, metal sulfides, metal carbides, carbon, organic polymers, semiconductors, semimetals, chalcogenides to name a few. Some of the most common are transition metal oxides, transition metal nitrides and chalcogenides.

[0045] The formation of conductive filaments is mostly from electrochemical processes. Examples include: oxidation and reduction, nitridation (nitrogen vacancies in transition metal nitrides, TIN, VN, WN, GaN, AIN, TaN, and NbN), sulfidation (sulfur vacancies of transition metal sulfides), and carbidation (carbon vacancies or carbon changes from amorphous to poiycarbon, to diamond like carbon) of transition metal oxides, nitrides, sulfides, carbides, and other solid state electrolytes such as TiOx, HfOx, TaOx, NiOx, ZrOx, VOx, ZnOx WOx, SnOx, InOx, InSnOx, CuO TaNxOx, BiTiOx, TIN, TaN, GaN, A1N, WN, VN, SiC, VC, TaC, ZrC, NbC, TiC, WC, ZnS, CuS, InS, CdTe, and GeS. In the case of transition metal oxides, nitrides, carbides, and sulfides, the material becomes more conducting or less conducting due to the vacancies. For example, in transition metal oxides, the more oxygen vacancies the more conducting the metal-oxide material is. Similarly, the fewer oxygen vacancies, the less conducting the metal oxide layer is.

Cha!cogenide material exhibits a phase change mostly due to thermal effects. An electrical current causes a rapid rate of change in local temperature due to ohmic heating that changes the phase of the chalcogenide material from more conducting to less conducting, and also from less conduction to more conduction. Other processes such as migration of Li, Na ions can also be used to form conducting filaments.

[0048] A basic challenge that is common to conventional RRAM/memrisiors (and phase change memories) are that the solid electrolyte or switching material does not have a predetermined path for the migration of the ions/vacancies and electrons. These charged species migrate along crystal grains, dislocations, and other crystailograpbical defects that occur during deposition of these films by various methods, such as atomic layer deposition (ALD). chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy ( BE), laser ablation deposition (LAD), sputtering, and thermal deposition. Due to the randomness or pseudo-randomness of the grain boundaries and other defects, the migration or drift of the charged species

(ions/vacancies/electrons/holes) under an applied electric field occur in a haphazard way (see, e.g. FIG. 1 B), going in the general direction toward the electrodes (along the electric field directions or lines), but taking the path of least resistance making detours around area of higher resistance. Subjecting the device to a high forming voltage is often necessary to breakdown the high resistance regions to create a low resistance path that is not usually the shortest path between the top and bottom electrodes. The forming process and the haphazard nature of the path for the charged species to migrate under an applied electric field are not desirable features for large-scale memory/computing arrays for system applications.

[0047] According to some embodiments, predetermined path(s) are provided for charged species to migrate along under an applied electric field. According to some embodiments, the charged species have a predetermined short path between the top and bottom electrodes. Furthermore, the forming voltage application can be eliminated since the low resistance paths are already established.

[0048] According to some embodiments, the variance in the IV characteristics is reduced by limiting where the vacancies and ions can travel from 3D (3- dimensions) to 2D (2-dimensions) and making the high mobility channel as "thin" as possible in the second dimension. It should be noted that the mobility in the 2D space is more or less uniformly high so that the ions and vacancies would follow the shortest path along a field line, whereas in contrast in the 3D space, the mobility is very low and the path followed by the ions and vacancies is more or less random in nature and may not be the shortest path between the top and bottom electrode. According to some embodiments, the pathway shape can be further reduced to 1 D using a process of introducing defects by energetic charged particle bombardment of the switching layer (e.g. ion implantation).

[0049] According to some embodiments, hetero and homo junctions are used to create high mobility channels for ions and vacancies. According to some embodiments, nanoholes and/or nanopiilars of 5 to 100 nm in diameter are created. The sidewalis of the nanoholes or the sidewails of the nanopiliers are coated with single or multiple layers of switching material and non switching materia! that may be the same material (homojuncation) or different material (heterojunction). The materials can have a similar bandgap or different bandgap. in one example, TMO material is used as a switching material and is combined with non-T O material such as SiC, SiNx, (non-oxidation and reduction electrochemical processes) that causes the TMO material to become more conductive and less conductive due to movements of oxygen ions and vacancies. The species (vacancies and ions) travel at the homo/hetero junction interfaces where the species mobility can be 100 to 1000 times greater than the mobility of the species in a bulk switching layer film. Due to the 2D nature of the interface, the randomness of the various paths the species can take is reduced by one dimension. Further, the mobility of the ions and vacancies is improved by orders of magnitude. This leads to a greatly reduced variance of the IR characteristics of the RRAM/memristor devices, both individually over time, and from device to device.

[0050] In addition due to the orders of magnitude (at least 2-3 orders) higher species mobility at the hetero/homo interface, the RRA /memristor can operate at orders of magnitude faster speed, lower voltage (and therefore lower power), lower junction capacitance, and higher reliability (due to lower voltage and current), over a larger number of switching cycles.

[0051] According to some embodiments, using different bandgap materials such as ZrOx (bandgap of 6.5 eV), AIOx (bandgap of 8.5 eV), TiOx (bandgap of 3.4 eV), ZnOx (bandgap of 3.3 eV), allows potential wells to form in the heterojunction interfaces that can further assist the mobility of the charged species (vacancies and ions, electrons and holes). These potential wells act as a high mobility channel for the charged species. Variations in the heterojunction structures can be made. For example, a double heterojunction can be made where a high-low-high or low-high- lovv bandgap material comprising of T O interfaced with other materials that are non-TMO such as SiNx. In some examples, one layer can be an oxygen oxidation- reduction switching layer such as TMO, while others can be nitrides or carbides such as SiC. According to some embodiments, the low bandgap material can form the high mobility channel for the species. The TMO material can be a mixture of stoichiometric and non-sfoichiometric material, or a combination thereof such as part of stoichiometric and part non-stoichiometric. According to some

embodiments, elements can be added such as Pt, Au, C, Ga, and/or In in the form of nanopartic!es and/or quantum dots. The material can be incorporated within the TMO material, for example, using co-sputtering, co-evaporation, eo-ALD, co-AVD (atomic vapor deposition) and/or co-PLD (pulsed laser deposition} and or ion implantation. According to some embodiments, the non TMO material can also be incorporated in a layer-by-layer method, such as by atomic layering for example.

[0052] FIGs. 4A-4G and 5A-5F are series of cross sections showing basic nanofabrication steps using a Park's block copolymer to generate nanohoie and nanopillers, according to some embodiments. See, Block Copolymer

Lithography: Periodic Arrays of ;10 ¹¹ Holes in 1 Square Centimeter; Miri Park, Christopher Harrison, Paul M. Cbaikin, SCIENCE VOL. 276 30 MAY 1997, p 1401 (hereinafter "Park et. ai"), which is incorporated herein by reference.

[0053] FIGs. 4A-4G are a series of cross sections showing basic

nanofabrication steps for nanohoie-based enhanced conduction structures, according to some embodiments. Fabrication starts with a substrate that is not conducting, for example quartz or SI02 on a silicon substrate. A bottom electrode 410 (BE) is formed of Pt (or TiNx, TaNx, Cu, Ru, W, Ai, Cr, Mo, Au, AL Ti, Ti silicide, Pt siiicide, or a composite of the metals and nitrides and silicides) with a width ranging from 2 to 1000 nm and thickness ranging from 10 to 1000 nm.

According to some embodiments, the width can be varying: wide away from the crossbar and narrow at the crossbar to reduce electrode resistance. (See FIG. 10 for an illustration of crossbars.) A silicon nitride (SiNx) layer 412 Is formed by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering deposition, or using other techniques such as AVD, PLD, e-beam or thermal evaporation. The SiNx layer 412 thickness ranges from 2 nm to 1000 nm. Referring to FIG. 4B, using Park's block copolymer lithography process B (see Park et al.) together with R!E (reactive ion etching) nanoholes 420 are defined in the SiNx layer 412. in FIG. 4C, ALD, PECVD, AVD, PLD, sputtering, electron beam (e-Beam) or thermal deposition techniques can be used to deposit a TMO switching layer 430 which for this example can be TiOx (other TMO layers such as TaOx, InOx, RuOx, WOx, ZnOx, ZrOx, HfOx, GaOx, with or without added metal or semiconductor nanoparticles/quantum dots to name a few can also be used), followed by RIE (reactive ion etching) to remove the TiOx on the planar surfaces (surfaces parallel to the substrate surface), but not significantly on the side wall of the nanohole. A subsequent TMO layer 432 such as ZrOx or HfOx can then be deposited by the above techniques, ALD/PLD/sputtering for example, and again followed by RIE to remove ZrOx/HfOx on the planar surfaces. The TMO and non- TMO layers can have thicknesses ranging from 0.1 to 10 (or 20 nm) nm. According to some embodiments, a non-TMO material can be used for layer 432, such as SiOx. This is also possible since it has oxygen ions and can act as an oxygen ion reservoir or sink for the switching TMO layer 430. As will be discussed infra, any of a wide variety of homo or hetero interface types can be used to allow species such as oxygen vacancies and oxygen Ions to travel in a high mobility channel. According to some embodiments, an added potential well further facilitates the high mobility channel at the interface homo/heterojunction, as it will act as a trough for the charged species. The potential well lowers local potential at the interface and therefore attracts the species of ions, vacancies, electrons and holes.

[0054] The process continues to alternate between deposition of TMO or non- T O layers followed by RIE removal of TMO or non-TMO materials at the planar surfaces to create layers of TMO and/or non-TMO (which can be SiOx, SiNx, SiC, GeOx, or C in diamond like structure) on the sidewall of the nanohole. In FIG. 4D, a third layer 434 is shown within the nanohole. Note that according to some embodiments, although three layers 430, 432 and 434 are shown in general, other numbers of layers can be used. Additionally, other combinations of TMO/TMO, TMO/non-TM. and non-TMO/non-TMO layers can be used. After the sidewall layers are complete, a top electrode (TE) 440 is deposited by e-beam evaporation, thermal evaporation, sputtering, PECVD, ALD, as shown in FIG. 4E. The TE 440 can be a composite of Ti, Pt, Cr, TiNx, TaNx, Mo.Au, Ru, silicide, Al. Cu, or Zr, and have a width of 2-1000 nm and thicknesses of 10-1000 nm or more. As in the case of the BE 410, the width of the electrode can vary, for example wider away from the junction and more narrow at the junction to reduce electrode line resistance. FIG. 4F shows some example materials used in the nanohole, according to some embodiments. The Oxygen vacancies travel along the interfaces 450, 452 and 454 as shown by the arrows, where the bandgaps are not equal. Oxygen vacancies travel in the "potential well" in the interfaces. FIG. 4G shows a top view of the device in the case where the nanohole has a circular cross-section

[0055] FIGs. 5A-5G are a series of cross sections showing basic

nanofabrication steps for nanopiilar-based enhanced conduction structures, according to some embodiments. According to some embodiments, a Park's block copolymer Ithography process is used to nano-fabricate nanopillars on silicon nitride or similar dielectric such as silicon dioxide, or silicon carbide. As in the case of nanoholes in FIGs. 4A-4F, the substrate can be quartz or silicon with an insulating layer such as SI02. The first few steps are similar to nanohole process, such as forming a bottom electrode (BE) 510 and depositing a dielectric layer 512 such as silicon nitride of thickness ranging from 5 to 1000 nm. In FIG. 5B, the technique described in Park et al. is used to generate nanopillars 520 (referred to as "dots" in Park et al.) using block copolymer and RIE. The nanopillars 520 can be 2-1000 nm in height. An example of 10 nm is shown in FIG. 5B. The nanopillar 520 is formed on the BE 510. The pillar 520 can in fact blanket the BE 510 and surrounding areas on the substrate since only those nanopillars or nanoholes contacted by the TE will be active, it is therefore not necessary to position the nanopii!ars/nanohoies just beneath the crossbar junctions of the BE and TE. As in the nanoholes, a combination of deposition and etching is used to form homo and hetero material junctions on the sidewali of the nanopillar. In FIG. 5C, layers 530, 532 and 534 are shown, although other numbers of layers can be used, according to some embodiments. The deposition can be created using ALD, PECVD, AVD, PLD, sputtering, e-beam, or thermal evaporation of materials such as TiOx, SiOx, HfOx, AIOx, ZrOx, TaOx, WOx, NbOx, RuOx, 8iC, or SINx. The materials can be stoichiometric or non-stoichiometric, or combination thereof, such as partially stoichiometric and partially non-stoichiometric with or without the inclusion of metal and semiconductor nanoparticies and or quantum dots. RIE is used to remove the materia! from the planar surfaces to create a layer of T O and non-TMO homo/hetero interfaces on the sidewali of the nanopillar 520. The thickness of the TMO and or non-TMO can range from 0.1 to 10 nm or more. In FIG. 5D, a dielectric 538, such as silicon nitride, is deposited by ALD or other methods mentioned above. To planarize the surface, a combination of deposition, etching and cbemica! mechanical polishing (CMP) can be used, in FIG. 5E, the top electrode (TE) 540 is formed which can be made of metals, semiconductors or combination of metal and semiconductor, including Ti, Pt, Cr, TiNx, TaNx, o,Au, Ru, si!icide, Al, Cu, and Zr. The width can be 2-1000 nm wide, and thicknesses can be 10-1000 nm or more. The fop and bottom electrodes 510 and 540 can be formed using photolithography, nanoimprint lithography, or e-beam lithography for both the nanohole and nanopillar RRA /memristors, using similar techniques and material as for the nanohole RRAM/memristors.

[0058] It should be noted that only these the basic steps are shown for purposes of clarity, and that many other steps are left out such as surface preparation, lithography, block copolymer processing and lithography, thermal annealing, passivation, plasma etching and surface treatments, lift off of metal dielectric films, etching of metal and dielectric films, pianarization, CMP process, wet etching, and oxidation.

[0057] Further detail with respect to heterojunctin and homojunction interfaces will now be provided, according to some embodiments. As used herein

"heterojunction interface" refers to a junction between two materials having different bandgaps and/or different atomic composition, while "homojunction interface" refers to a junction between two materials having the same bandgap and/or same atomic composition. The material can be crystalline, poiycrysta!line, micro-crystalline, amorphous, glass, ceramic, dielectric, graphite, or graphene, material doped with other material such as Au, Ag, Bi, Nb, or nanopartic!es.

According to some embodiments, combinations of such materials are used.

[0058] Vacancies, ions, electrons and holes have a much higher mobility at interfaces than in the bulk material. Oftentimes, the interface mobility increase is two to three orders of magnitude or greater. According to some embodiments, using materials of different bandgaps in a heterojunction, a potential well can be formed to further guide the ions, vacancies, electrons and holes along the high mobility channel. The interface can be between two different materials. According to some embodiments, a homojunction can be used between two portions of the same material having different stress. Stress on material can be achieved by deposition conditions. At such interfaces there is a stress field that can also give rise to high mobility channel and attract ions and species (such as oxygen vacancies and charged ions). Many of the embodiments described herein discuss material with different bandgaps. However, according to some embodiments, instead of different bandgaps, interfaces with the same bandgaps can also be used that have different stress, different lattice constant, different atomic composition, and/or different doping, to give rise to a stress and/or electric and/or composition (defects) gradient that can increase the mobility of the charged species, such as charged ions and vacancies.

[0059] Although the electrodes are biased with a range from -30 to +30 volts depending on the device, most operate at -4 to +4 V for bipolar RRAM/memristors and 0 to +4 or 0 to -4 V for unipolar RRAM/memristors. Oxygen vacancies behave generally as positive charge, and oxygen ions behave generally as negative charge. Note that although main embodiments are described herein in the context of oxygen vacancy in electrochemical oxidation and reduction processes for the RRA /memristors devices, according to some embodiments, the mobility enhanced pathway structures described herein are applied other devices. For example, according to some embodiments, mobility enhanced pathway structures are used with RRAM/memristors operating on different mechanisms such as copper-nitride (E.g. see, Zhu, W., Zhang, X., Fu, X., Zhou, Y., Luo, S. and Wu, X. (2012), Resistive-switching behavior and mechanism in copper-nitride thin films prepared by DC magnetron sputtering. Phys. Status Soiidi A, 209: 1996-2001 doi: 10.1002 / pssa.201228175, which is incorporated by reference), Nitride memristors, and unipolar switching in carbon (Fu, Unipolar Resistive Switching Properties of Diamondlike Carbon-Based RRAM Devices, Electron Device Letters, IEEE (Volume:32, issue: 6 }, June 201 1 , which is incorporated by reference). According to some embodiments, mobility enhanced pathway structures are used with non-oxygen based switching devices. An interface high mobility channel for these non-oxygen based RRAM/memristors will also greatly enhance the mobility by orders of magnitude which can significantly improve its reproducibility, reliability, speed and reduce variance of the individual devices and device to device variances and power consumption.

[0080] FIG. 6 is an energy-bandgap diagram illustrating aspects of a heterojunction interface, according to some embodiments. FIG. 6 shows a single heterojunction between material 810 and material 612. In the example shown, material 610 is ZrOx and material 612 is TiOx. Potential wells for ions and vacancies along the length of the junction interface 620 serve as a high mobility channel. The field at the interface of the heterojunction 820 can be caused by the difference between the energies of the bandgaps of the two different materials and/or the difference in the stress field at the interface 620 due to the difference in lattice constants and/or composition and/or due to different processing conditions, in addition, higher defect density at the interface may also assist with the increase in mobility of ions and vacancies. The electric potential and/or stress fields and/or high defect density can contribute to enhancing the mobility of the charged species such as charged ions and vacancies.

[0061] FIG, 7 is an energy-bandgap diagram illustrating aspects of a double heterojunction interface, according to some embodiments. FIG. 7 shows a case of a double interface where in a "high-low-hign" configuration. Materials 710 and 714 both have higher bandgaps than material 712. The lower "sandwiched" bandgap material 712 is used to form a high mobility interface channel. The thickness of the low bandgap material 712 can be 0.01 to 2 nm. The high-low-high structure is particularly effective in enhancing mobility since Ions and vacancies are "collected" or "trapped" to some degree in the high mobility region where they are guided along the high mobility channel. Also in this case, according to some embodiments, stress and/or defects can also contribute to increase in mobility of the species. According to some embodiments, a low-high-low bandgap structure is used rather than a high-low-high.

[0062] Double heterojunction interfaces provide a high mobility channel for ions, vacancies, electrons and holes. In the example shown in FIG. 7, large bandgap TMO's (e.g. ZrOx) are sandwiching a smailar bandgap TMO (e.g. TiOx) in a high-low-high bandgap configuration. According to some embodiments, a Non- TMO material can also be used. Examples of suitable non-TMO layers include SiC or SiNx, as long as a source of mobile ions and or vacancies are provided near the TE or BE, such as a reservoir of ions and or vacancies. This reservoir can be a TMO layer material near the TE and or BE such that ions/vacancies can be injected into the high mobility channels. According to some embodiments, a low- high-low bandgap structure is provided which is essentially a back-to-back configuration of that shown in FIG. 6.

[0083] FIG. 8 is an energy-bandgap diagram illustrating aspects of a

homojunction interface, according to some embodiments. Homojunction interfaces may be used where the materials are the same type of material. During

processing, however, TMO-1 (810) is first deposited on the sidewali of either a nanohole or nanopiliar followed by RIE etching to remove TMO-1 from the planar surfaces. Then, TMO-2 (812) which is the same material as TMO-1 but deposited on the sidewali of the nanohole or nanopiliar at a subsequent processing step. During processing steps between deposition of TMO-1 and TMO-2, the surface of TMO-1 may have changed and an interface 820 exists between TMO-1 and TMO- 2. It should be noted that according to some embodiments, a double homojunction is used with the addition of TMO- 3 that can be very thin (e.g. 0.1-2 nm between TMO-1 and TMO-2). Also, due to different processing conditions stress may be introduced intentionally or unintentionally that can further improve the mobility of the species at the interfaces of the homojunctions.

[0064] According to some embodiments, contributors to increased charged species mobility include: electric potential due to energy differences; stress due to materia! and processing conditions; defect densities; surface states and surface state potentials. Although single and double junctions have been described herein, in general there is no limit to going beyond double hetero/homo junction interfaces. Furthermore, according to some embodiments, a mixture of hefero and homo junctions are implemented.

[0065] The formation of potential wells and/or stress fields in heterojunction and homojuction interfaces is of particular importance. The potential/stress wells trap and guide the ions and vacancies within the well, confining the paths that the ions and vacancies can take during the formation/destruction of the conducting channel. This reduces the variations in the IV characteristics of the

RRAM/memristor due to the random multiple paths it can take in a 3-dimension bulk switching layer.

[0068] FIGs. 9A and 9B are cross sections showing aspects of enhanced mobility pathways structures according to some embodiments. In FIG. 9A, the addition of tunnel or Schottky layer 904 at the end of the high mobility channel structures 920, such that as the conducting filament (CF) is formed the CF will come into contact with the tunnel layer 904 which can be tailored for the desired on and off resistance of the RRA 900. The "on" resistance is also referred to as the low resistance state (LRS), and the "off resistance is also referred to as the high resistance state (HRS). The Schottky layer 904 can provide a rectifying diode characteristic which is desirable in crossbar memory architecture to reduce fringing current paths from neighboring memory elements. According to some

embodiments, Schottky layer 904 can be SiC, SI3N4, C-diamond, or graphene. According to some embodiments, Schottky layer 904 can also be amorphous Si, Ge, SiC, GaAs, InP, grapheme, or C-diamond. The tunnel layer 902 can be 0.01 to 2 nm thick and the Schottky layer 904 can be 0.1-1000 nm thick and can be placed at either the BE (910) end, TE (940) end, or at both ends.

[0067] According to some embodiments, the hetero/homo junctions may be made from material, such as SiC, which does not participate in switching with a certain species, and does not switch with transition metal oxides such as TiOx, TaOx, HfOx, for example. In FIG. 9B, the hetero/homo junctions 922 may be formed with non-switching materia! such as SIC, S13N4, diamond like carbon, grapbene, GaAs, Si, and/or SiN. A reservoir of the switching ions in the form of monolayer 906 of TiOx, TaOx, or HfOx for example, is deposited near the BE (910) and/or TE (940). The monolayer(s) 906 is formed with a thickness of 0.01 -1 nm approximately such that the ions/vacancies can be injected into the high mobility hetero/homo junctions 922. According to some embodiments, any combination of hetero or homo junction can be used based on: all non-switching material, all switching material, or part switching and part non-switching material.

[0068] According to some embodiments, since the pathway structures of the charged species (ions and vacancies) are defined, the formation of tunneling and/or Schottky diodes are reproducible and will give less variance in the IV characteristics of the RRAM/memristor.

[0069] Also, due to the high mobility channel of the hetero/homo junction interfaces, the RRAM/memristors do not rely on "forming" voltages that typically are close to or above the breakdown voltage for the bulk switching layer. This "forming" process is required for bulk switching layers of conventional devices to form the "breakdown path", which is a low resistance path through most of the bulk material for ionic conduction. The actual switching occurs within 1-2 nanometers to the electrode. The randomness of the "breakdown path" in conventional devices causes the variance in the IV characteristics of prior art bulk film RRAM/memristors within a single devices and from device to device. The conventional "breakdown path" dimensions are not controllable, and often these devices operate at high current of 1-100 microamps or more, which reduces reliability and reproducibility of the RRAM/memristor. The conventional "forming" step is an undesirable effect in RRAM/memristor and increases the cost of manufacturing.

[0070] With hetero/homo junction interfaces providing a high mobility channel for the ions/vacancies, "forming" at high voltages (10-30V) and high current (1 -100 or more microamps) are advantageously not relied upon, since the high mobility channels for conducting the species (ions and vacancies) are pre-defined by the purposely formed hetero/homo junction interfaces. The RRAM/memristor, according to some embodiments, can also operate at a lower current of less than or equal to approximately 1 microamp and voltages of 0.5-5 volts (depending if tunnel and or Schottky layers are included. Thus lower overall energy operation can be attained. Since the device did not suffer exposure to a breakdown voltage (or close to it), the RRAM will be more reliable and the IV characteristics reproducible.

[0071] The crossbar capacitance of each RRAM/memristor element will also be reduced since with 2-3 orders of higher mobility, the top and bottom electrodes can be separated by a larger distance. According to some embodiments, the electrode separation is at least 10X greater than a comparable bulk switching layer device. This not only is a reduction in device capacitance, but also a reduction in adjacent electrode fringing capacitance due to greater height/total distance separation.

[0072] FIG. 10 is a top view showing aspects of enhanced mobility pathway- structures' positioning, according to some embodiments. At each crossbar point, a nanohole or nanopiliar (920, 922, 924 and 926) is formed between the top and bottom electrodes. Note that although the nanohoies/pi!iars are shown in FIG. 10, in practice they will be buried beneath the top electrode structures. According to some embodiments, there are multiple nanoholes/nanopil!ars at each cross point and need not be uniformly spaced, depending on the width of the electrode and density of the nanoholes/nanopiliars. According to some other embodiments, the nanoholes/nanopiliars can blanket the entire surface covering the BE prior to TE formation, this way the fabrication is very tolerant to manufacturing errors, such as in alignment. Nanoscale alignment will not be necessary. The BE and TE can be made from (and combinations thereof) Mo, TIN, Pt, Ai, Cu, Ti, Ta, TaN, W, Au, Ru, Zr, Cr, Ni, to name a few.

[0073] FIG, 1 1 shows a lateral hetero/homo junction interface with a high mobility channel structure, according to some embodiments, in the lateral embodiment of FIG. 1 1 , the TE (1 140) and BE (1 1 10) electrodes are now on the same surface (despite the "top" and "bottom" labels). The device 1 100 can be fabricated on a silicon substrate 1 1 12 (or quartz or sapphire substrates) that has a layer 1 1 14 of silicon nitride deposited on it by PECVD, for example to a thickness of 100 to 5000 nm. For example, switching layers 1 1 18 and 1 1 18 are made of TaOx and HfOx, respectively, each having a thickness of between 0.1 to 1000 nm. According to some embodiments, one or more of 1 1 18 or 1 1 18 is made of a non- switching material. The electrodes 1 1 10 and 1 140 are defined by photolithography (or nanoimprint lithography or e-bearn lithography). If the metal/semiconductor used for the electrodes are the same, then a single step lithography can suffice, However, if the electrode metai/semiconductor are different then a two step lithography to define the electrodes will be necessary. The process of defining the electrodes can be by etching (where the metal/semiconductor are first deposited then followed by lithography and dry etching, ion milling, or wet chemical etching) or by lift-off process (where the patterns of the electrode are defined on photoresist for example, the photoresist is then developed and via's are opened in the photoresist in the shape of the electrode pattern). Metals and/or semiconductors are then deposited and the resist is then dissolved away in solvent, leaving behind the metal/semiconductor pattern in the shape of the electrode. According to some embodiments, a more sophisticated method of lift-off technique can be achieved using a combination of photoresist and dielectric to minimize contamination due to photoresist. The process is repeated if the electrodes are of different material. Finally the top layer switching material 1 1 18, HfOx is formed with thickness ranging from 0.1 to 1000 nm. in the case shown in FIG. 1 1 , layer 1 1 18 is patterned similar to the methods of patterning the electrodes. In certain cases the top switching layer 1 1 18 can be blanket deposition over the entire substrate, in case the top layer is not a switching layer, (e.g. where only one switching layer is used) then SiNx or SiC, with thickness ranging from 0.1-1000 nm, can be blanket deposited over the entire substrate except for places where additional electrical contacts need to be made to the memory array/device. The deposition methods, electrodes, switching and non-switching layers are similar to processes and metal/semiconductors mentioned for fabricating the nanohole and nanopiliar RRAM/memristors.

[0Θ74] According to some embodiments, the layers 1 1 16 and 1 1 18 in FIG. 1 1 can also be multiple layers, not just limited to a single or double layers. In general, multiple betero/homo junction interfaces can be formed with any combination of hetero and homo junctions and switching and non-switching layers (TMO and non TMO layers). In addition ions and vacancies reservoirs layers can also be located adjacent to the electrodes to inject ions and vacancies into the high mobility channels made from switch and non switching layers or any combinations of switching and non switching layers. The betero/homo junction interface form a high mobility channel and the species are predominantly transported along this high mobility channel shown by the dotted arrow 1130 in F!G. 1 1 .

[0075] The gap between the electrodes 1 1 10 and 1 140 in FIG. 1 1 can be 1 -100 nm. The electrodes can 10-5000 nm thick and 1 -5000 nm wide. According to some embodiments, the width can vary away from the gap to a wider width than at the gap width to decrease electrode resistance.

[0076] According to some embodiments, enhanced mobility pathway structures can be created using high-energy particles accelerated in a single and/or multiple direction(s). According to some embodiments, the pathway structures used for the migration of charged vacancies, ions, electrons and/or holes under an applied electric field are created via ion implantation of heavy ions such as Au, Pb, Fe, Bi, Hg, or Pt (or lighter ions such as H, O, N, Ar, He, Si, P, C, As, B, Ti, Hf, Ta, or Al), through the switching layer with or without the TE in place, FIGs. 12A-12D are diagrams showing aspects of ion implantation in a switching layer used to create an enhanced mobility pathway structure for RRAM devices, according to some embodiments, in FIG. 12A, ion beam 1250, which in this case is Au ions, implant the ions in switching layer 1212. For typical RRAM/memristor structures of 2-20 nm switching layer thickness, accelerating energies of approximately 20 to 100 KeV are appropriate for an ion such as Au (only about 0.4 of the accelerating energy for Au is need for Fe to achieve the same depth for example) to penetrate the thickness of switching layer 1212 entirely. A dose of greater than 1 x10 ¹⁴ ions/cm ² at 50 KeV for Au will result in a concentration of Au of approximately 1 x10 ²⁰ Au ions/cm ³ . The dosage can be adjusted to achieve the optimal density of defects for desired IV characteristics for a particular application. For example, a dose as high as 5x10 ¹⁶ ions/cm ² or higher can be used to create a region of very high density defects, which results in extremely low switching voltages. With less defect density (by using a lower implantation dose of Au ions for example), the switching voltage may be higher. The switching voltage can also be adjusted via the accelerating energy in addition to the dose. In a single chip/array, by adjusting the KeV and or the dose, multiple switching voltages can be made. In addition, to KeV and dose, the choice of ions (e.g. Au, Fe, Al, Ga, Si, B, P, or As) can also affect the defect to the switching layers to further adjust the switching parameters of the RRAM/memristor (and phase change memories). According to some embodiments, impiant mask 1252 is used, as shown in FIG. 12A. In the case of FIG. 12A, the top electrode layer 124 is formed before the implantation process. According to some other embodiments, the implantation is carried out before the formation of the top electrode layer. FIG. 12B shows the resulting ion implanted region 1220 which has enhance mobility of charged species both due to the implanted ions as well as the crysta!lographic defect structures from the

implantation process. According to some embodiments, the implantation process implants the ions directly info the bottom electrode 1210, with the crystallographic damage structures remaining in switching layer 1212.

[0077] Referring again to FIG. 12A, breakdowns and reliability failures often occur at the edge of a device where the edge of the electrodes are often areas of high electric field concentration and the active layers are exposed that can result in excessive leakage current. According to some embodiments, the ion implantation of ions and resulting crystaliographical defects can be patterned using an ion implantation mask 1252 that is thicker than the penetration depth of the

accelerated ions by greater than 3x the stopping coefficient thickness of the material. The mask 1252 can be Au, poiyimide, photoresist, dieiectrics such as SiOx, SiNx, for stopping approximately 95% or more of the ions, in the case of Au ions, the penetration depth as mentioned earlier is approximately one nm for every 5 KeV in Al-oxide, to penetrate 10 nm will require 50 KeV approximately. To mask the areas from ion implantation, mask thickness of greater than 30 nm in material similar to Al-oxide or denser, will stop greater than 95% of the ions, mask thickness of 5X or greater than 50 nm will stop more than 99% of the ions. This will generate implanted ions and defects in areas away from the edges as schematically shown in a cross section of the device.

[0Θ78] FIGs. 12C-12D illustrate cases where a non switching material 1252 used together with a reservoir iayer 1254 of TiOx, TaOx or HfOx, where ions and vacancies can be injected into the channeling defects created by ion implantation beam 1250 of high energy particles with the application of an external electric field. The reservoir can be monoiayer(s) 1254 of the transition metal oxides located adjacent to the TE 1240 and or BE 1210.

[0079] Layers of switching and non-switching material can be combined in any combination, according to some embodiments, to optimize the RRAM or memristor or phase change memory. For example if TaOx is the switching material, SiC or SiN, non-switching with transition metal oxide ions and vacancies, can be combined with TaOx, or with a multiple of switching and non-switching materials.

[0080] The tailoring of the crystailographicai and non crysfai!ographica! defects in the switching layer allow the charged vacancies, ions, electrons and/or holes a predetermined path to migrate from regions in the switching layer(s) toward either the TE or BE. According to some embodiments, a non-switching material such as SiC, SiNx, for example and with ion/vacancy reservoir adjacent to the TE and or BE (such as a monolayer or more of TiOx or HfOx, or TaOx for example) can be used in switching layers. The switching layers can also include combinations of switching and non-switching materials. The predetermined defects generated by ion implantation in the switching layer result in more reproducible IV characteristics with less variability for the RRA /memristor and also eliminates reliance on the forming process to breakdown high resistivity regions by the application of a high voltage and current. Note that the forming voltage is conventionally substantially higher than the voltage and current for set and reset of the RRAM/memristor. According to some embodiments, tailored defect region for the migration of charged vacancies, ions, electrons and/or holes is referred to as a "channeling path".

[0081] FIGs. 13A-13B are diagrams showing the use in multiple implantation energies and/or multiple ion species to generate enhanced mobility pathway structures, according to some embodiments. Ion beam 1350 includes multiple energies and multiple ion species being implanted to generate a defect spatial region and doping spatial profile with impurities such as Au, Si, P, B, Ge, Pt, W, Ti, Fe, Bi, 0, C, or S, to tailor the defect region for vacancies, ions, electrons and/or holes transport and impurities, in this way, the switching characteristics such as non!inearity, set and reset switching voltages, HRS and LRS and ratios can be tailored, all while avoiding the high-vo!tage/high current conventional forming process. The multiple implant energies and species of beam 1350 can create a spatial distribution of predetermined defects and impurities of various ion species in zone 1320 within the switching layer 1312 and at the interfaces of the switching layer(s) 1312 and the electrodes 1310 and 1340 and within the electrodes themselves. According to some embodiments, the multiple implant energies ranging from 1 KeV to 200 KeV corresponding approximately to an average Gaussian shaped spatial depth profile where the peak of the Gaussian profile is referred to as the average depth, from approximately 0.1 to 40 nm. Doses can also range from 1 x10 ¹³ ions/cm ² to 1 x10 ¹⁷ ions/cm ² .

[0082] The irnplant(s) can be just within the switching layers 1312, and/or at the interface between the switching layers 1312 and the electrodes and/or into the electrodes 1310 and/or 1340. As in earlier cases, ions can be implanted through the TE 1340. The implant(s) can have different ion species, different implant energies and different dose for the optimal RRAM/memristor performance. Ion species such as Bi, Er, Li, Na, Yt, and Yb can be included singly or in combination with other elements that can be co-implanted to facilitate the switching

characteristics of the RRA and memristors. in general, any stable elements on the Periodic Table can be used for the implantation process using single or multiple charged ions.

[0083] An advantage of implanting multiple species is that the switching layer(s) can be established after the device is made. For example, bottom and top electrode 1310 and 1340 can sandwich a material 1312 such as AI2O3 (SIC or diamond like carbon, are also possible). The switching ions, for example Ti and 0 are then implanted at a doping level of greater than 1 x10 ²² ions/cm ³ , which can be at single or multiple accelerating energies to create a defect and doping spatial profile that is in the AI2O3 layer 1312 and can extend into the interface with the electrode 1310 and into the electrodes 1310 itself. According to some

embodiments this can also extend into the TE 1340 interface with 1312 and also within TE 1340 itself. Other ions can also be used together with Ti and O such as Au to create the crysta!lographica! defects and to have Au ions in the N2G3 layer in order to assist in the formation of the conducting filament. Other ions for the switching can be Hf and O, Ti and N, Ta and O, Ga and N, Al and/or N. Ions such as Bi, Er, Yt, Yb, Au, Pb, V, NL W, Nb, Au, Ag, Cu, S, C, O, N, in, or Zn can be added to assist in the formation of the conducting filaments and/or to participate in the switching process. Top and bottom electrode materials can be Mo, TIN, TaN, Pt, Au, Ti, Ta, Ru, AICu, Al, Cu, V, W, Si, SiGe, and/or silicide, resulting in either unipolar or bipolar switching. [0084] Placing the switching ions/vacancies after the fabrication of the top and bottom electrodes eliminate the uncertainty of processing contaminations at the electrode switching layer interface during the lithographic steps of masking and etching of the electrodes. The ion implantation process can minimize and to an extent neutralize the contamination with additional ions/vacancies and defects that can eliminate the reliance on the conventional forming process for

RRAM/memristors.

[0085] FIGs. 14A-14B are schematic cross sections illustrating aspects of using high dosage ion implanafion to form a buried layer, according to some

embodiments. At high doses - a doping level of 1 x10 ²² ions/cm ³ or higher (or lower in cases where there is already a high concentration of ions and/or vacancies) a buried layer of TiOx, HfOx, VOx, TiNx, GaNx, CuSx, or ZnSx for example can be formed to provide a source of vacancies and ions. In addition a buried crystalline layer such as Si02 , AI2O3, SiC, SiN, TIN, GaN tunnel layers can also be formed, often called mesotaxy, with or without thermal annealing,

According to some embodiments the buried layer is amorphous rather than crystalline. Once the the layers are buried or on the surface, high energy ion implantations as in Fig. 12A B and 13 can be implemented to form defect and doping regions where charged vacancies, ions and electrons/holes can drift under an applied electric field. Mobile ions such as Li, Na , H, K, to name a few can also be implanted for conductive filament formation in layer(s) consisting of transition metal oxides, nitrides, carbides, sulfides,fluorides, chlorides semiconductors such a Si, Ge, GaAs, !nP, to name a few and CaF ₂ , NaCI, KCI, SiGe, GeS, ZnS, CdTe, for example (these material can also be the switching material without the addition of Li, Na, K, F, ions for example). In FIG. 14A chystai!ographic defects and species are distributed in region 1420 from high-dose ion implant. The resulting buried layer 1422 is formed between the switching layer 1412 and bottom electrode 1410. In the case of FIG. 14B, the defects and species result in buried layer 1424 that resides between top electrode 1440 and switching layer 1412.

[0088] FIGs. 15A-15B are cross sections showing aspects of using ion implantation to extend info the electrodes and overlap at the interface with the switching iayer(s), according to some embodiments, in these examples, the implanted region exists both in the electrode, at the electrode-switching layer interface and the switching !ayer(s). This improves the electrode-switching layer interface, removing any high electrical resistivity regions/barriers. Ion species implanted at the electrode-switching layer interfaces can include 0 ions for example if the electrode is Ti to create a TiOx layer in the electrode and the switching layer is TiOx for example. The other electrode can be Ti or other electrode material such as Pt, W, Nb, Au, to name a few. The implantation of ion species into the electrode and the interface of the electrode and switching layer(s) improves the electrode to switching layer contact and can minimize and to an extend eliminate barriers of high electrical resistivity that often requires the undesirable additional process of forming. The implanted ions can be species other than the electrode material and its vacancies (oxygen, nitrogen, sulfur, carbon, hydrogen, chlorine, fluorine for example) such as Au, Pt, Ag, Ta, Si, B, P, As, in for example, such that defects and/or metal/semiconductor ions can minimize interface barriers. In certain cases, a barrier is desirable, and purposely fabricated (not due to processing contamination), such as a tunnel barrier, in which case it can be buried with ion implantation single or multiple ion species and energies, to create a tunnel barrier of TIN, SiN, SiC, AIOx, C, TiOx, TaOx, WOx, or WNx. The tunnel barrier is different from the switching layer material. For example, if the switching layer material is transition metal oxide such as TiOx, HfOx, TaOx, VOx, WOx, the tunnel layer can be TIN, TaN, SiC, AIN, Si, Ge, for example. The implanted ions can penetrate both the TE and BE or just the TE or just the BE. Buried implanted layers can be at both the TE and BE or just TE or BE. FIG. 15A shows an example of buried layer 1522 and/or buried species between the BE 1510 and the switching layer 1512. FIG. 15B shows an example of buried layer 1524 formed between TE 1540 and switching layer 1512.

[0Θ87] FIG. 16 is a cross section showing an example two species of ion implantation, according to some embodiments, in this example the HfOx switching layer 1612 is sandwiched between with a Ti top electrode 1640 and TIN bottom electrode 1610. O ions are implanted into the Ti electrode 1640, the interface with HfOx, and into HfOx layer 1812. N ions implanted into the TIN electrode 1610, the interface with HfOx, and into HfOx 1612 as shown in the schematic. This technique improves the contacts of the electrodes 1610 and 1640 to the switching layer 1612 and provides vacancies/ions for injection into the high mobility channels. According to some embodiments, Hf ions can also be implanted at one or both interfaces and or into the HfOx switching layers. Defects generated by ion implantation are not shown, the defects help facilitate eiectromigration of the vacancies and ions and electrons under an applied electric field, With the improved contact to switching layer, lower contact resistance, the switching layer thickness can be increased to adjust the switching voltage to the desired value. Current RRAM/memristors have thicknesses of the switching layer ranging from 2 to 25 nm, this can be increase for example to 5 to 50 or more nanometers (nm).

[0088] FIGs. 17A-17B are cross sections illustrating an ion implantation followed by a tunnel or other layer epitaxial grown, according to some

embodiments. The tunnel layer 1714 (insulator layer, can be dielectric, air, vacuum) or diode layer (in which case the layer is a semiconductor) can also be grown epitaxialiy after the ion implanted crystal!ographical defects are generated in the switching layer(s) 1712 and followed by the deposition of an electrode 1740 on the tunnel or diode layer 1714 which can be done within the same processing chamber or in situ.

[0089] The tunnel layer 1714 can be a layer that does not support propagation of the conducting filament; for example in a transition metal oxide switching layer such as TiOx, TaOx, or HfOx. The tunnel layer can be a carbide, nitride, oxide (not the same transition metal, for example AIOx or AI2O3), sulfide layer or diamond like carbon layer. The tunnel layer can also be a vacuum or gas cell. The diode layer can be microcrystaliine Si, Ge, SiGe, GaN or any semiconductor. Both the tunnel layer and diode layer can be epitaxialiy grown by atomic layer deposition, chemical vapor deposition, laser ablation deposition, plasma enhance chemical vapor deposition, sputtering and thermal evaporation for example.

[0Θ90] According to some embodiments, in addition to masking the ion implanted defects and ions, using multiple ion implant species and energies and doses, species such as TiOx, TaOx HfOx, TiNx, or TaNx can be implanted into a non switching material such as AI2O3, SiC, Si3N ₄ , CaFi. GaAs, AIM, Si, diamond like carbon and other stoichiometric material such as GaN, where all the vacancies, ions are implanted after (or before) the TE and BE electrodes and any tunnel or diode layers are grown and deposited in a selective area away from the edges. "Non switching material" refers to a material used to accommodate the conducting filament formation ions and vacancies but does not itself participate significantly in the formation of the conducting filaments) material. The ion implantation of the ions and generating the defects after the TE and BE {and possibly tunnel and diode layers also) are formed is advantageous in that the switching material is added last and can be implanted at the interface to the electrode and matrix material such that there is minimum contamination at the interface and the device is functional without further intrusive processing of the active layer, Some connecting eiectrodes may be added for particular applocafions or connecting to CMOS (complementary metal oxide semiconductor) or other ASIC (application specific integrated circuits) circuits. This can be accomplished with or without patterning the ion implantation for selective area ion implantation.

[0091] According to some embodiments, ion implantation can also be used to create stress such that the interface between implanted area and non implanted area can have a stress field that can be a high mobility channel for electro- migrating ions and vacancies under an applied electric field.

[0092] FIGs. 18A and 18B are cross sections illustrating aspects of forming a switching layer in-situ using ion implantation, according to some embodiments. A buried TiOx switching layer 1812 is formed in-situ between a TE 1840 and BE 1840. A BE 1810 such as Pt for example is first deposited, followed by a TE layer 1840 such as Ti. Oxygen ions are than implanted into the TE 1840 to convert some of the Ti layer into TiOx switching layer 1812 with or without thermal anneal processes. At this point, the device is a RRAM with an in situ TiOx switching layer. Pathways for enhanced mobility channels can then be added, according to some embodiments using one or more of the other techniques described herein, Advantages of this in-situ process include that the switching layer(s) and the interfaces between the switching layer(s) and the electrodes are not exposed to any processing environment that can cause contamination and thereby degrade the RRAM.

[0093] In at least some embodiments, the enhanced mobility pathways in the materia! region disposed between said top and bottom electrodes follow straight directions from one to the other of the top and bottom electrodes and are initially formed by a physical manipulation of the material region that excludes application of a voltage to the material region equal to or greater than a breakdown voltage for the material region. The term "straight directions" in this context denotes directions that are straight or at least markedly straighter than the directions of pathways that are formed through the known process of applying formation voltage that equals or exceeds the breakdown voltage of the material region, such as illustrated in FIG. 1 B.

[0094] In some embodiments, the enhanced mobility pathways are formed by a physical manipulation of the material region, such as by processes described above including ion implantation, formation of holes/pillars, etc , wherein the physical manipulation takes place at a time when the material region is in a state free of enhanced mobility pathways caused by applying breakdown voltage across the material region, and wherein the material region remains in said state after said physical manipulation. In this context, the term "free" denotes the absence of enhanced mobility pathways intentionally caused by applying breakdown voltage across the material region, although it does not exclude one or more possible pathways that might be caused by inherent defects or discontinuities in the material.

[0095] This patent application refers to certain theories in explaining the nature and operation of devices, but it should be clear that such theories are based on current understanding and do not affect the actual operation of the disclosed devices even if future developments prove the theories incorrect. This patent specification also refers to numerical ranges of parameters, and it should be understood that insubstantial departures from such ranges are still within the spirit of the disclosed advancements.

[0096] Although the foregoing has been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be made without departing from the principles thereof. It should be noted that there are many alternative ways of implementing both the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the body of work described herein is not to be limited to the details given herein, which may be modified within the scope and equivalents of the appended claims.