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Title:
RESISTIVE RANDOM ACCESS MEMORY (RRAM) WITH MULTICOMPONENT OXIDES
Document Type and Number:
WIPO Patent Application WO/2018/009157
Kind Code:
A1
Abstract:
A memory including a top electrode and a bottom electrode; and an oxide layer including a plurality of intimately mixed oxides throughout the oxide layer. A memory including a top electrode and a bottom electrode; an oxygen exchange layer; and an oxide layer between the oxygen exchanger layer and the bottom electrode, wherein the oxide layer includes of a plurality of intimately mixed oxides. A method including forming a bottom electrode; forming an oxide layer on the bottom electrode wherein the oxide layer includes a plurality of intimately mixed oxides throughout the oxide layer; forming an oxygen exchange layer (OEL) on the oxide layer; and forming a top electrode on the OEL.

Inventors:
MUKHERJEE, Niloy (16781 NW Vetter Drive, Portland, Oregon, 97229, US)
KARPOV, Elijah V. (3964 NW Brookview Way, Portland, Oregon, 97229, US)
PILLARISETTY, Ravi (925 NW Hoyt Street, Apt. 226Portland, Oregon, 97209, US)
CLARKE, James S. (5676 NW 204th Place, Portland, Oregon, 97229, US)
Application Number:
US2016/040893
Publication Date:
January 11, 2018
Filing Date:
July 02, 2016
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
INTEL CORPORATION (2200 Mission College Boulevard, Santa Clara, California, 95054, US)
International Classes:
H01L45/00; G11C13/00
Domestic Patent References:
WO2015147801A12015-10-01
WO2016105673A12016-06-30
Foreign References:
US20140167042A12014-06-19
US20110089393A12011-04-21
US20140264238A12014-09-18
Attorney, Agent or Firm:
BRASK, Justin, K. et al. (Schwabe, Williamson & Wyatt1211 SW 5th Ave., Suite 190, Portland OR, 97204, US)
Download PDF:
Claims:
CLAIMS

1. A memory comprising:

a top electrode and a bottom electrode; and

an oxide layer between the top electrode and the bottom electrode comprising a plurality of intimately mixed oxides throughout the oxide layer.

2. The memory of claim 1, wherein the plurality of oxides comprise ones of tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide

3. The memory of claim 1, wherein the oxide layer comprises hafnium oxide and tantalum oxide.

4. The memory of claim 1, wherein the oxide layer comprises tantalum oxide and titanium oxide.

5. The memory of claim 1, wherein the oxide layer comprises hafnium oxide and titanium oxide.

6. The memory of claim 1, wherein the oxide layer comprises tantalum oxide and tungsten oxide

7. The memory of claim 1, wherein the oxide layer is derived from a sputter target.

8. The memory of claim 1, wherein the memory is a resistive access memory.

9. A system comprising:

a processor;

a memory, coupled to the processor, according to any one of claims 1-8; and a communication module, coupled to the processor, to communicate with a computing node external to the system.

10. A memory comprising:

a top electrode and a bottom electrode; an oxygen exchange layer; and

an oxide layer between the oxygen exchanger layer and the bottom electrode, wherein the oxide layer comprises of a plurality of intimately mixed oxides. 11. The memory of claim 10, wherein the plurality of oxides comprise ones of tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide

12. The memory of claim 10, wherein the oxide layer comprises hafnium oxide and tantalum oxide.

13. The memory of claim 10, wherein the oxide layer comprises tantalum oxide and titanium oxide.

14. The memory of claim 10, wherein the oxide layer comprises hafnium oxide and titanium oxide.

15. The memory of claim 10, wherein the oxide layer comprises tantalum oxide and tungsten oxide 16. The memory of claim 10, wherein the oxide layer is derived from a sputter target.

17. The memory of claim 10, wherein the memory is a resistive access memory.

18. A method compri sing :

forming a bottom electrode;

forming an oxide layer on the bottom electrode wherein the oxide layer comprises a plurality of intimately mixed oxides throughout the oxide layer; and

forming a top electrode on the oxide layer. 19. The method of claim 18, wherein forming the oxide layer comprises sputter depositing the oxide layer.

20. The method of claim 18, wherein the plurality of cations are selected from tantalum, hafnium, titanium and tungsten.

21. The method of claim 18, wherein prior to forming the top electrode, the method comprises forming an oxygen exchange layer (OEL) on the oxide layer.

AMENDED CLAI MS

received by the International Bureau on 09 May 2017 (09.05.2017)

1. A memory comprising:

a top electrode and a bottom electrode; and

an oxide layer between the top electrode and the bottom electrode comprising a plurality of intimately mixed oxides throughout the oxide layer.

2. The memory of claim 1, wherein the plurality of oxides comprise ones of tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide.

3. The memory of claim 1, wherein the oxide layer comprises hafnium oxide and tantalum oxide.

4. The memory of claim 1, wherein the oxide layer comprises tantalum oxide and titanium oxide.

5. The memory of claim 1, wherein the oxide layer comprises hafnium oxide and titanium oxide.

6. The memory of claim 1, wherein the oxide layer comprises tantalum oxide and tungsten oxide.

7. The memory of claim 1, wherein the oxide layer is derived from a sputter target.

8. The memory of claim 1, wherein the memory is a resistive access memory.

9. A system comprising:

a processor;

a memory, coupled to the processor, according to any one of claims 1-8; and a communication module, coupled to the processor, to communicate with a computing node external to the system.

10. A memory comprising:

a top electrode and a bottom electrode; an oxygen exchange layer; and

an oxide layer between the oxygen exchanger layer and the bottom electrode, wherein the oxide layer comprises of a plurality of intimately mixed oxides.

11. The memory of claim 10, wherein the plurality of oxides comprise ones of tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide.

12. The memory of claim 10, wherein the oxide layer comprises hafnium oxide and tantalum oxide.

13. The memory of claim 10, wherein the oxide layer comprises tantalum oxide and titanium oxide.

14. The memory of claim 10, wherein the oxide layer comprises hafnium oxide and titanium oxide.

15. The memory of claim 10, wherein the oxide layer comprises tantalum oxide and tungsten oxide.

16. The memory of claim 10, wherein the oxide layer is derived from a sputter target.

17. The memory of claim 10, wherein the memory is a resistive access memory.

18. A method compri sing :

forming a bottom electrode;

forming an oxide layer on the bottom electrode wherein the oxide layer comprises a plurality of intimately mixed oxides throughout the oxide layer; and

forming a top electrode on the oxide layer.

19. The method of claim 18, wherein forming the oxide layer comprises sputter depositing the oxide layer.

20. The method of claim 18, wherein the plurality of intimately mixed oxides comprise cations selected from tantalum, hafnium, titanium and tungsten.

21. The method of claim 18, wherein prior to forming the top electrode, the method comprises forming an oxygen exchange layer (OEL) on the oxide layer.

Description:
RESISTIVE RANDOM ACCESS MEMORY (RRAM) WITH MULTICOMPONENT

OXIDES

TECHNICAL FIELD

Semiconductor devices and, in particular, non-volatile memory.

BACKGROUND

Resistive random access memory (RRAM or ReRAM) relies on a class of materials that generally switch in a one-time event from an insulating state to a low resistive state by way of a "forming" event. In the forming event, the device goes through "soft breakdown" in which a localized filament forms in a dielectric layer located between two electrodes. The filament tends to shunt current through the filament to form a low resistance state. The RRAM switches from a low to a high resistive state (by disbanding the filament) and from a high to a low resistive state (by reforming the filament) by applying voltages of different polarities to the electrodes to switch the state. Thus, conventional RRAM can serve as a memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of embodiments will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Figure 1 shows a cross-sectional side view of an embodiment of a RRAM stack. Figure 2 shows a cross-sectional side view of a portion of a substrate having a bottom electrode of a RRAM stack formed thereon.

Figures 3 shows the structure of Figure 2 following the formation of an oxide layer on the bottom electrode

Figure 4 shows the structure of Figure 3 following the formation of an optional oxygen exchange layer on the oxide layer.

Figure 5 shows the structure of Figure 4 following the formation of a top electrode on the structure.

Figure 6 is a flow chart of an embodiment for forming a RRAM stack illustrated in Figures 2-5.

Figure 7 shows a schematic side view of a sputter-chamber having the substrate of Figure 2 therein and the formation of an oxide layer on a bottom electrode by a sputter deposition technique.

Figure 8 shows a cross-sectional side view of another embodiment of RRAM stack.

Figure 9 shows a schematic of an embodiment of a memory array.

Figure 10 shows a schematic of a system including an embodiment of a RRAM stack.

Figure 11 shows a schematic of another system including an embodiment of a RRAM stack.

Figure 12 shows a schematic of a further system including an embodiment of a RRAM stack.

DETAILED DESCRIPTION

Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various

embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer of a semiconductor device is necessarily shown. "An embodiment", "various embodiments" and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments "First", "second", "third" and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

"Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.

Figure 1 shows a schematic cross-sectional side view of an embodiment of a RRAM stack. In this embodiment, RRAM stack 100 includes top electrode 101, optional oxygen exchange layer (OEL) 11 1, oxide layer 121, and bottom electrode 131. Oxygen vacancies 144 in oxide layer 121 tend to have a higher concentration in region 141 and a relatively lower concentration in region 142 when OEL 1 1 is used. Oxygen vacancies 144 are created by subjecting RRAM stack 100 to an anneal. An annealing process encourages scavenging of oxygen by OEL 1 11 thereby producing vacancies 144 The vacancies cluster near the OEL/oxide interface (interface between OEL 11 1 and oxide layer 121) because that is where the scavenging takes place. The vacancies collectively form a filament that serves as a memory. Biasing top electrode 101 and bottom electrode 131 with one polarity may purposely remove vacancies in area 143 to disband or disrupt the filament and create a high resistance state (a "0" memory state). Reversing the bias to top electrode 101 and bottom electrode 131 with an opposite polarity may reform vacancies in area 143 to reform the filament and create a low resistance state (a " 1" memory state).

In an embodiment, top electrode 101 includes at least one of a metal such as tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), palladium (Pd) or platinum (Pt) or a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAIN), and tantalum aluminum nitride (TaAIN). Similarly, bottom electrode 131 includes at least one of a metal such as W, Pd, Pt, Ru, Mo or Ir, or a metal compound such as TiN, TiAIN, and TaAIN. Additionally, electrodes 101, 131 may include multiple layers of materials with differing properties. In one embodiment, a material of top electrode 101 and bottom electrode 131 may be similar.

In an embodiment, optional OEL 1 11 includes a metal such as one or more of the following: hafnium (Hf), titanium (Ti), tantalum (Ta), erbium (Er), and gadolinium (Gd).

In an embodiment, oxide layer 121 includes more than one intimately mixed oxide throughout oxide layer 121. More than one oxide means two, three, four or more oxides, where each of the more than one oxide has a cation that is different from the cation of the other oxide(s) in the intimate mixture. Examples of oxides include, but are not limited to, more than one of hafnium oxide (HfOx), silicon dioxide (S1O 2 ), aluminum oxide (AI 2 O 3 ), titanium oxide (TiOx), tantalum oxide (TaOx), gadolinium oxide (GdOx), erbium oxide (ErOx), niobium oxide (NbOx), tungsten oxide (WOx), zinc oxide (ZnOx), indium-tin oxide (InSnO), and indium-gallium-zinc oxide (InGaZnOx). Examples of oxide layer 121 of more than one intimately mixed oxide include, but are not limited to, where the oxide layer includes at least hafnium oxide and tantalum oxide; where the oxide layer includes at least tantalum oxide and titanium oxide; where the oxide layer includes at least hafnium oxide and titanium oxide; and where the oxide layer includes at least tantalum oxide and tungsten oxide. In one embodiment, the more than one oxide are intimately mixed or alloyed throughout oxide layer 121 in the sense that one oxide is not differentiated from another in oxide layer 121. The intimately mixed oxides may be formed in one embodiment by a radio frequency (RF) physical vapor deposition (sputter) process of a "true alloy" target. A "true alloy" target is formed of powders of different oxides (e.g., micron-sized particles) that are well mixed, dried, pressed under a high pressure and then sintered at high temperature (e.g., greater than 1000°C) for several hours. The sputter deposition from a true alloy target produces an oxide layer with different oxides in intimate proximity. In contrast, an example of differentiated oxides is layers of different oxides where such different oxides might be intermingled at an interface but are otherwise differentiated from one another. Another example of

differentiated oxides for an oxide layer may be characterized as a "digital alloy" oxide layer formed, for example, by an atomic layer deposition (ALD) process. In such a process, precursors of different oxides are pulsed in a layer by layer process to produce a film. The resulting ALD produced film is not subject to sintering at a high temperature as described with respect to the "true alloy" target used in a PVD process as such sintering could damage an underlying circuit substrate on which the film in this context might be formed. Thus, the film is made of layers.

In an embodiment, oxide layer 121 directly contacts optional OEL 111. The direct contact allows for scavenging of oxygen from oxide layer 121 and the resultant creation of vacancies 144. In another embodiment, oxide layer 121 of more than one intimately-mixed oxide may be formed with a sufficient number of vacancies so that OEL 11 1 may be eliminated and oxide layer 121 directly contacts top electrode 101 and, on an opposite side, bottom electrode 131.

Referring to Figure 1, RRAM stack 100 is a functioning nonvolatile memory in that in a first state, when energy is applied to top electrode 101 at a first polarity, the first and second pluralities of oxygen vacancies form a first filament have a first electrical resistance; and in a second state, when energy is applied to top electrode 101 at a second polarity, which is opposite the first polarity the first and second pluralities of oxygen vacancies form a different filament configuration or discontinuity thereby causing the higher resistivity. In the second state the plurality of oxygen vacancies at area 142 is at a low concentration (second concentration) and in the first state the plurality of oxygen vacancies at area 142 is at a concentration that is greater than the second concentration.

Figures 2-5 illustrate a method of forming a RRAM stack according to an embodiment. Figure 6 presents a flow chart of the method illustrated in Figures 2-5.

Figure 2 shows a cross-sectional substrate 210 that may be any material that may serve as a foundation on which a RRAM stack may be constructed. Representatively, substrate 210 is a portion of a larger substrate such as a wafer. In one embodiment, substrate may have as its base a semiconductor material such as silicon. Such a semiconductor base may be bulk silicon or, in another embodiment, a semiconductor on insulator (SOI) structure. Formed on and/or in a base of substrate 210 may optionally be a number of circuit device as well as conductive lines or traces and insulating layer(s). Disposed on a surface of substrate 210, the surface optionally including a dielectric material such as silicon dioxide or a dielectric material having a dielectric constant less than silicon dioxide (a low k material) is bottom electrode 231. Bottom electrode 231 is a conductive material such as a metal or alloy of metal. Examples of suitable metals include, but are not limited to, W, Pd, Pt, u, Mo and Ir. Bottom electrode 231 may also be a conductive ceramic material, such as TiN, TiAIN and TaAlN. Bottom electrode 231 may further include a number of layers of different metals, alloys and/or conductive ceramic materials. One way to form bottom electrode 231 is by a chemical vapor deposition process (block 310, Figure 6).

Figure 3 shows the structure of Figure 2 following the formation of an oxide layer on the bottom electrode (block 320, Figure 6). In one embodiment, oxide layer 321 is formed by a physical vapor deposition method such as a radio frequency (RF) sputtering method. According to one method, a ceramic target is used in the sputter deposition method. The ceramic target includes more than one oxide (e.g., two, three, four different oxides) intimately mixed together. Different oxides in this context are oxides having cations that are different than another oxide in the intimate mixture. Representatively, the multiple oxide target is a "true alloy. " A "true alloy" may be formed by thoroughly mixing powders of different oxides (e.g., micron-sized powders of oxides having different cations) together, pelletizing the mixture under high pressure then annealing the pellet in a furnace for a sufficient period of time to form a ceramic structure. One example is an anneal at 1000°C for 2 or more hours. The result is a target of a microscopic uniform alloy. The target is formed of more than one intimately mixed oxide at a unit cell microscopic level.

Figure 7 shows a schematic representation of a sputter chamber including substrate 210 in a volume thereof together with a ceramic target. Ceramic target 420 is composed of more than one intimately mixed oxide. A volume of chamber 410 includes substrate 210 and target 420 separated by shutter 430. Target 420 is bombarded by inert gas ions, such as argon ions (Ar+) causing the removal of target species that condense on substrate 210 as a film (an oxide film) of similar stoichiometry to that of the target material. The process may be performed in an oxygen atmosphere and a flow rate of oxygen into chamber may be controlled to control oxygen vacancy formation in the oxide file. An RF sputter process biases substrate 210 (the anode) and target 420 (the cathode) at, for example, 13.56 megaHertz (Mhz). In one embodiment, an RF sputter process employs magnetron sputtering that generates a magnetic field near the target area that causes traveling electrons to spiral along magnetic flux lines near target 420 and thus confines a plasma near the target area without damaging the film being formed on substrate 210.

An oxide layer of more than one intimately or alloyed oxide offers an ability to tailor performance and reliability of a RRAM stack or cell. Generally, metal oxide candidates for RRAM technology such as tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide offer particular combinations of performance relative to reliability. None alone offers high performance (fast or low voltage/current switching) and very high reliability (non-volatility, endurance) required for advanced internet of things (IoT) applications, particularly at scaled technology nodes of 40 nanometers (nm) and smaller. Combining/alloying multiple oxides offers the potential of producing oxides that satisfy both performance and reliability targets for advanced scaled IoT nodes 40 nm and beyond. The RFPVD method of forming a film of multiple intimately mixed oxides also provides reproducibility as the cation composition in the target is reproduced in the film. Other advantages of sputtering include a more intimately mixed alloy can be deposited more easily compared to other techniques such as ALD, CVD, etc. and sputtering results in clean films with fewer impurities than films formed by other deposition methods. Sputtering also has the highest throughput and is thus the least expensive deposition technique at the industrial scale. In addition, performing of a PVD method in an oxygen atmosphere allows control over vacancies in the oxide layer of a RRAM stack so that an OEL in the stack becomes unnecessary. Representatively, during formation of an oxide layer on a bottom electrode (e.g., oxide layer 321 in Figure 3), a vacancy gradient may be introduced by, for example, providing an oxygen atmosphere in a chamber as the oxide layer is initially formed and than reducing the oxygen atmosphere as a thickness of the layer approaches its target thickness.

Referring again to the method illustrated in Figures 2-5 and the flow chart of Figure 6, following formation of oxide layer 221 on bottom electrode 231, optional OEL or layers may be formed on oxide layer 221. Figure 4 shows the structure of Figure 3 following the formation of OEL 211. OEL layer may be formed of a metal material such as Hf, Ti, Ta, Er, and Gd and may be formed by a chemical vapor deposition process (block 330, Figure 6).

Figure 5 shows the structure of Figure 4 following the formation of a top electrode on the structure (block 340, Figure 6). Figure 5 shows top electrode 201 of, for example, a metal or alloy of metals such as W, Ru, Mo and Ir or a conductive metal compound such as TiN, TiAIN and TaAlN. Following formation of the individual layers of the RRAM stack, the stack may be patterned to specific dimensions (e.g., xy-dimensions) using masking and etching techniques (block 350, Figure 6). Representative dimensions for a RRAM stack such as shown in Figure 5 include an x-dimension of 20 nm to 400 nm; a y-dimension of 20 nm to 400 nm and a z-dimension of 20 nm to 100 nm. Following formation of the RRAM stack, the RRAM stack may be annealed to encourage scavenging of oxygen by OEL 221 A representative anneal is 400°C for 30 minutes.

Figure 8 shows an embodiment of RRAM stack without an OEL and formed by a method similar to that described above. Figure 8 shows RRAM stack 500 including top electrode 501 and bottom electrode 531 that can be materials as described above with reference to Figure 1. RRAM stack 500 includes oxide layer 521 disposed between top electrode 501 and bottom electrode 531 and directly contacting each electrode. Oxide layer 521, in one embodiment, includes more than one oxide that are intimately mixed and formed by a PVD (sputtering) technique. Figure 8 shows oxygen vacancies 544 in oxide layer 521. Oxygen vacancies 544 are shown, in this example, concentrated in region 541 adjacent top electrode 501 while little or no oxygen vacancies are present in region 542 adjacent bottom electrode 531. Region 542 of oxide layer 521 may be formed in an oxygen atmosphere in a sputter chamber (e.g., PVD sputtering in an oxygen rich environment) while region 541 of oxide layer 521 may be formed in an atmosphere with less oxygen (an oxygen starved environment).

Any such RRAM stack as described above may be used in a memory cell by connecting one portion or node of the stack (e.g., top electrode 101 of Figure 1) to a bit-line and another node of the stack (e.g., bottom electrode 131 of Figure 1) to a source or drain node of a switching device, such as a selection transistor (e.g., a 1T1R configuration). The other of the source and drain node of the selection transistor may be connected to a source line of the memory cell. The gate of the selection transistor may connect to a word-line. Such a memory cell may utilize resistance to store memory states. The RRAM stack may connect to a sense amplifier. A plurality of the RRAM memory cells may be operably connected to one another to form a memory array, wherein the memory array can be incorporated into a non-volatile memory device. It is to be understood that the selection transistor may be connected to the top electrode or the bottom electrode of a RRAM stack. Figure 9 shows RRAM stack 600 may be used in a memory cell (and memory array). One portion or node of the stack (e.g., top electrode 101 of Figure 1) is connected to a column decoder and another node of the stack (e.g., bottom electrode 131 of Figure 1) is connected to a row decoder in a crossbar/crosspoint array.

Figures 10-12 illustrate systems that may include any of the above-described embodiments. Figures 10-12 include block diagrams of systems 1000, 1100, 1200, respectively in accordance with embodiments. Each of those systems may include millions to billions with typical memory arrays ranging from a few kilobits (1 bit = 1 cell) to several gigabits of the above-described memory cells/stacks (e.g., RRAM stack 100 of Figure 1 or RRAM stack 500 of Figure 8). The memory cells may be included in, for example, elements 1010, 1030, 1170, 1132, 1190, 1210, 1240, 1280, and the like. Systems 1000, 1100, 1200 may be included in, for example, a mobile computing node such as a cellular phone, smartphone, tablet, Ultrabook®, notebook, laptop, personal digital assistant, and mobile processor based platform. The stability and power efficiency of such memory cells accumulates when the memory cells are deployed in mass and provides significant performance advantages (e.g., longer memory state storage in a broader range of operating temperatures) to such computing nodes.

Referring now to Figure 10, shown is a block diagram of an example system with which embodiments can be used. As seen, system 1000 may be a smartphone or other wireless communicator or any other IoT device. Baseband processor 1005 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 1005 is coupled to an application processor 1010, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 1010 may further be configured to perform a variety of other computing operations for the device.

In turn, application processor 1010 can connect to a user interface/display 1020, e.g., a touch screen display. In addition, application processor 1010 may connect to a memory system including a non-volatile memory, namely flash memory 1030 and a system memory, namely dynamic random access memory (DRAM) 1035. In some embodiments, flash memory 1030 may include secure portion 1032 in which secrets and other sensitive information may be stored. As further seen, application processor 1010 also connects to capture device 1045 such as one or more image capture devices that can record video and/or still images.

Universal integrated circuit card (UICC) 1040 includes a subscriber identity module, which in some embodiments includes a secure storage 1042 to store secure user information. System 1000 may further include security processor 1050 that may connect to application processor 1010. Multiple sensors 1025, including one or more multi-axis accelerometers may connect to application processor 1010 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 1095 may be used to receive, e.g., user biometric input for use in authentication operations.

As further illustrated, a near field communication (NFC) contactless interface 1060 is provided that communicates in a NFC near field via NFC antenna 1065. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.

Power management integrated circuit (PMIC) 1015 connects to application processor

1010 to perform platform level power management. To this end, PMIC 1015 may issue power management requests to application processor 1010 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 1015 may also control the power level of other components of system 1000.

To enable communications to be transmitted and received such as in one or more IoT networks, various circuitries may be connected between baseband processor 1005 and antenna 1090. Specifically, radio frequency (RF) transceiver 1070 and wireless local area network (WLAN) transceiver 1075 may be present. In general, RF transceiver 1070 may be used to receive and transmit wireless data and calls according to a given wireless

communication protocol such as 3 G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition GPS sensor 1080 may be present, with location information being provided to security processor 1050 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals, e.g., AM FM and other signals may also be provided. In addition, via WLAN transceiver 1075, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.

Referring now to Figure 11, shown is a block diagram of a system in accordance with another embodiment. Multiprocessor system 1100 is a point-to-point interconnect system such as a server system, and includes first processor 1170 and second processor 1 180 coupled via point-to-point interconnect 1 150. Each of processors 1170 and 1180 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1174a and 1174b and processor cores 1 184a and 1 184b), although potentially many more cores may be present in the processors. In addition, processors 1170 and 1180 each may include respective secure engine 1 175 and 1185 to perform security operations such as key management, attestations, IoT network onboarding or so forth.

First processor 1170 further includes memory controller hub (MCH) 1172 and point- to-point (P-P) interfaces 1176 and 1178. Similarly, second processor 1180 includes MCH 1182 and P-P interfaces 1186 and 1 188. MCH 1172 and 1 182 connect the processors to respective memories, namely memory 1132 and memory 1134, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 1170 and second processor 1180 may be connected to chipset 1 190 via P-P interconnects 1152 and 1154, respectively. As shown in Figure 11, chipset 1 190 includes P-P interfaces 1194 and 1198.

Furthermore, chipset 1190 includes interface 1192 to couple chipset 1 190 with high performance graphics engine 1138, by P-P interconnect 1 139. In turn, chipset 1190 may be connected to first bus 1 1 16 via interface 1196. Various input/output (I/O) devices 11 14 may be coupled to first bus 11 16, along with bus bridge 1118 which connects first bus 11 16 to second bus 1120. Various devices may be coupled to second bus 1120 including, for example, keyboard/mouse 1122, communication devices 1126 and data storage unit 1128 such as a non- volatile storage or other mass storage device. As seen, data storage unit 1128 may include code 1 130, in one embodiment. As further seen, data storage unit 1 128 also includes trusted storage 1 129 to store sensitive information to be protected. Further, audio I/O 1124 may be connected to second bus 1120.

Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor IoT devices. Referring now to Figure 12, shown is a block diagram of wearable module 1200 in accordance with another embodiment. In one particular implementation, module 1200 may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1200 includes core 1210 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1210 may implement a trusted execution environment (TEE). Core 1210 connects to various components including sensor hub 1220, which may be configured to interact with a plurality of sensors 1280, such as one or more biometric, motion

environmental or other sensors. Power delivery circuit 1230 is present, along with nonvolatile storage 1240. In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (10) interfaces 1250, such as one or more interfaces compatible with one or more of USB/SPI/I2C/GPIO protocols, may be present. In addition, wireless transceiver 1290, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms Wearable and/or IoT devices have, in comparison with a typical general purpose central processing unit (CPU) or a grahpics processing unit (GPU), a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.

EXAMPLES

The following examples pertain to further embodiments.

Example 1 is a memory including a top electrode and a bottom electrode; and an oxide layer between the top electrode and the bottom electrode including a plurality of intimately mixed oxides throughout the oxide layer.

In Example 2, the plurality of oxides of the method of Example 1 or 2 includes ones of tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide.

In Example 3, the oxide layer of the method of Example 1 or 2 includes hafnium oxide and tantalum oxide.

In Example 4, the oxide layer of the method of Example 1 or 2 includes tantalum oxide and titanium oxide.

In Example 5, the oxide layer of the method of Example 1 or 2 includes hafnium oxide and titanium oxide.

In Example 6, the oxide layer of the method of Example 1 or 2 includes tantalum oxide and tungsten oxide.

In Example 7, the oxide layer of the method of Examples 1-6 is derived from a sputter target.

In Example 8, the memory of the method of Examples 1-7 is a resistive access memory.

Example 9 is a system including a processor; a memory, coupled to the processor, according to any one of claims 1 -8, and a communication module, coupled to the processor, to communicate with a computing node external to the system.

Example 10 is a memory including a top electrode and a bottom electrode; an oxygen exchange layer; and an oxide layer between the oxygen exchanger layer and the bottom electrode, wherein the oxide layer includes of a plurality of intimately mixed oxides. In Example 11, the plurality of oxides of the memory of Example 10 include ones of tantalum oxide, hafnium oxide, titanium oxide and tungsten oxide.

In Example 12, the oxide layer of the memory of Example 10 or 1 1 includes hafnium oxide and tantalum oxide.

In Example 13, the oxide layer of the memory of Example 10 or 1 1 includes tantalum oxide and titanium oxide.

In Example 14, the oxide layer of the memory of Example 10 or 1 1 includes hafnium oxide and titanium oxide.

In Example 15, the oxide layer of the memory of Example 10 or 1 1 includes tantalum oxide and tungsten oxide.

In Example 16, the oxide layer of the memory of Examples 10-15 is derived from a sputter target.

In Example 17, the memory of the memory of Examples 10-16 is a resistive access memory.

Example 18 is a method including forming a bottom electrode, forming an oxide layer on the bottom electrode wherein the oxide layer includes a plurality of intimately mixed oxides throughout the oxide layer; and forming a top electrode on the oxide layer.

In Example 19, forming the oxide layer of the method of Example 18 includes sputter depositing the oxide layer.

In Example 20, the plurality of cations of the method of any of Examples 18-20 is selected from tantalum, hafnium, titanium and tungsten.

In Example 21, prior to forming the top electrode, the method of Example 18 includes forming an oxygen exchange layer (OEL) on the oxide layer.

The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate, the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.